b33f0bcb4a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 46.853m | 372.606ms | 199 | 200 | 99.50 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.590s | 35.385us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.640s | 60.422us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.420s | 562.771us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.840s | 33.548us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.570s | 126.790us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.640s | 60.422us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.840s | 33.548us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 254 | 255 | 99.61 | |||
| V2 | random_reset | rv_timer_random_reset | 41.801m | 324.452ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 4.577m | 764.462ms | 49 | 50 | 98.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 36.363m | 1.401s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 36.363m | 1.401s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 53.664m | 478.230ms | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.640s | 19.354us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.150s | 702.972us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.150s | 702.972us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.590s | 35.385us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.640s | 60.422us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.840s | 33.548us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.830s | 77.946us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.590s | 35.385us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.640s | 60.422us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.840s | 33.548us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.830s | 77.946us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 289 | 290 | 99.66 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.930s | 529.940us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.420s | 815.321us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.420s | 815.321us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 23.215m | 63.300ms | 18 | 50 | 36.00 |
| V3 | TOTAL | 18 | 50 | 36.00 | |||
| TOTAL | 586 | 620 | 94.52 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.61 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.55 |
UVM_ERROR (cip_base_vseq.sv:828) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
0.rv_timer_stress_all_with_rand_reset.10704820692953313996869279970561228829261545261913330053222095307787516272114
Line 578, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 124039945045 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10025 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 124039945045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.99943868628002362471340158585324928107581733882219794757211518195270293845161
Line 353, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 39678642002 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 39678642002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
27.rv_timer_disabled.7703938364394756077926831176236240100585627135523991799502742172643298885897
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/27.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
182.rv_timer_random.371974801068184013064906570542760521182726751136342930457327631089938358792
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/182.rv_timer_random/latest/run.log
Job ID: smart:2f7e806a-a62c-4a2b-ab9d-8a19459e53af