eb56ef55d0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 55.083m | 178.820ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.580s | 19.688us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.630s | 110.816us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.270s | 350.847us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.870s | 46.697us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.480s | 113.542us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.630s | 110.816us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.870s | 46.697us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 8.696m | 53.855ms | 49 | 50 | 98.00 |
| V2 | disabled | rv_timer_disabled | 5.856m | 215.598ms | 48 | 50 | 96.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 31.435m | 8.488s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 31.435m | 8.488s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.194h | 451.665ms | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.600s | 22.681us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.130s | 2.875ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.130s | 2.875ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.580s | 19.688us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.630s | 110.816us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.870s | 46.697us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.870s | 173.681us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.580s | 19.688us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.630s | 110.816us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.870s | 46.697us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.870s | 173.681us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 287 | 290 | 98.97 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.000s | 866.114us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.410s | 115.435us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.410s | 115.435us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 17.853m | 92.739ms | 16 | 50 | 32.00 |
| V3 | TOTAL | 16 | 50 | 32.00 | |||
| TOTAL | 583 | 620 | 94.03 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.59 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.43 |
UVM_ERROR (cip_base_vseq.sv:828) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
0.rv_timer_stress_all_with_rand_reset.81298496778932284201901574241000052231028474131545472552826380922206162300385
Line 343, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 28889777892 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 28889777892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.68586088187541266510255702064799971341344200039184668273605104876793204190001
Line 285, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 29373813170 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 29373813170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 32 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
Test rv_timer_disabled has 2 failures.
26.rv_timer_disabled.25965596908899999607817235163690027046328317964117233733370759386170152088052
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/26.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.rv_timer_disabled.3094894421251505257743133119428952387675997776375308888523449981911056764100
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/31.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_random_reset has 1 failures.
49.rv_timer_random_reset.110849717413081802373329313256121472868836084292925779319936129529480987793985
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/49.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---