RV_TIMER Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: `9edf84e236`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	58.577m	332.066ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.630s	67.087us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.650s	15.445us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.730s	1.628ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.810s	34.848us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.270s	284.532us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.650s	15.445us	20	20	100.00
		rv_timer_csr_aliasing	0.810s	34.848us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	41.115m	313.536ms	49	50	98.00
V2	disabled	rv_timer_disabled	4.850m	718.634ms	49	50	98.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	24.203m	4.779s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	24.203m	4.779s	50	50	100.00
V2	stress	rv_timer_stress_all	1.306h	603.369ms	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.610s	49.502us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.120s	866.732us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.120s	866.732us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.630s	67.087us	5	5	100.00
		rv_timer_csr_rw	0.650s	15.445us	20	20	100.00
		rv_timer_csr_aliasing	0.810s	34.848us	5	5	100.00
		rv_timer_same_csr_outstanding	0.850s	174.418us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.630s	67.087us	5	5	100.00
		rv_timer_csr_rw	0.650s	15.445us	20	20	100.00
		rv_timer_csr_aliasing	0.810s	34.848us	5	5	100.00
		rv_timer_same_csr_outstanding	0.850s	174.418us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	rv_timer_sec_cm	0.900s	318.114us	5	5	100.00
		rv_timer_tl_intg_err	1.450s	470.561us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.450s	470.561us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	17.931m	133.268ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			582	620	93.87

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.47	99.36	98.73	100.00	--	100.00	100.00	98.75

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
- Test rv_timer_stress_all_with_rand_reset has 32 failures.
  - 0.rv_timer_stress_all_with_rand_reset.80880434693679685427358273596185751077391633974321718900831658938702691487046
    Line 745, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 306200551671 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10033 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 306200551671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_timer_stress_all_with_rand_reset.33952870404250236551677802903603571330352286465422122359300350187752952262450
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 478901460 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10008 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 478901460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 30 more failures.
UVM_ERROR (cip_base_vseq.sv:749) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 4 failures:
- Test rv_timer_stress_all_with_rand_reset has 4 failures.
  - 18.rv_timer_stress_all_with_rand_reset.94495413686862949831134232998876501511959579123216162975676909172356071778405
    Line 962, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/18.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 440243335955 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 440243335955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.rv_timer_stress_all_with_rand_reset.24926016404326121309628691461964698116688580952859580925808526614614003048406
    Line 451, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/20.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16812096007 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 16812096007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test rv_timer_disabled has 1 failures.
  - 10.rv_timer_disabled.107163034507225463296270463825898435868380378194222384849514896473298137651711
    Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/10.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_timer_random_reset has 1 failures.
  - 17.rv_timer_random_reset.8966439971232549641120189983202599084285132828466022617431900129285903744590
    Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/17.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

RV_TIMER Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: 9edf84e236

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `9edf84e236`