RV_TIMER Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: `abd7ce57f2`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	36.493m	267.448ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.620s	29.781us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.610s	13.169us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.570s	4.497ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.840s	240.365us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.410s	31.490us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.610s	13.169us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	240.365us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	31.108m	115.159ms	49	50	98.00
V2	disabled	rv_timer_disabled	6.263m	962.626ms	48	50	96.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	34.826m	6.301s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	34.826m	6.301s	50	50	100.00
V2	stress	rv_timer_stress_all	1.402h	1.008s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.610s	20.531us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.010s	156.481us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.010s	156.481us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.620s	29.781us	5	5	100.00
		rv_timer_csr_rw	0.610s	13.169us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	240.365us	5	5	100.00
		rv_timer_same_csr_outstanding	0.890s	167.655us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.620s	29.781us	5	5	100.00
		rv_timer_csr_rw	0.610s	13.169us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	240.365us	5	5	100.00
		rv_timer_same_csr_outstanding	0.890s	167.655us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	rv_timer_sec_cm	0.950s	86.389us	5	5	100.00
		rv_timer_tl_intg_err	1.490s	214.959us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.490s	214.959us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	13.003m	483.825ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			574	620	92.58

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.68	99.36	98.73	100.00	--	100.00	100.00	100.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 42 failures:
- Test rv_timer_stress_all_with_rand_reset has 42 failures.
  - 0.rv_timer_stress_all_with_rand_reset.16197888149458071168299857305740932879510314866050015148668352051538323329577
    Line 553, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 314460833739 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 314460833739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_timer_stress_all_with_rand_reset.89196039243580728829641519165184357350195070210691265929473837674108668314271
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8066999329 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10046 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8066999329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 40 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test rv_timer_disabled has 2 failures.
  - 12.rv_timer_disabled.27290162986724374202054770488193908553328642905473796515051141823074495442201
    Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/12.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.rv_timer_disabled.47986719915903094139162337356155395438563568471821768124056696390358046706648
    Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/33.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_timer_random_reset has 1 failures.
  - 31.rv_timer_random_reset.7063896791439137345663805046284644257174498141569883661346010892455431881640
    Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/31.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:749) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test rv_timer_stress_all_with_rand_reset has 1 failures.
  - 31.rv_timer_stress_all_with_rand_reset.24188480263595947803260366202796962693445816386952458235966834143952917613521
    Line 513, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/31.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 46874506859 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 46874506859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

RV_TIMER Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: abd7ce57f2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `abd7ce57f2`