e9ae10fb42| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 37.038m | 1.702s | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.610s | 37.487us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.660s | 53.077us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.830s | 855.395us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.810s | 81.420us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.490s | 111.297us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.660s | 53.077us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.810s | 81.420us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 18.895m | 176.831ms | 48 | 50 | 96.00 |
| V2 | disabled | rv_timer_disabled | 5.623m | 981.923ms | 50 | 50 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 19.178m | 4.935s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 19.178m | 4.935s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.100h | 666.407ms | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.650s | 16.003us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.710s | 185.437us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.710s | 185.437us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.610s | 37.487us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.660s | 53.077us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.810s | 81.420us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.870s | 76.326us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.610s | 37.487us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.660s | 53.077us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.810s | 81.420us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.870s | 76.326us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 288 | 290 | 99.31 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.310s | 435.347us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.990s | 2.796ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.990s | 2.796ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 25.460m | 295.604ms | 18 | 50 | 36.00 |
| V3 | TOTAL | 18 | 50 | 36.00 | |||
| TOTAL | 586 | 620 | 94.52 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.57 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.32 |
UVM_ERROR (cip_base_vseq.sv:828) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
1.rv_timer_stress_all_with_rand_reset.103958847806599297931898480101739206504518679502280295505215349307887563501431
Line 307, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16831804189 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 16831804189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_timer_stress_all_with_rand_reset.63940390252321518921701516286404285667736330766151583198898064274158369284795
Line 824, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 76242488109 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 76242488109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
35.rv_timer_random_reset.1951466108282722804972646399971492755165010767056735720187487343549670392482
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/35.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.rv_timer_random_reset.82698012936241278692067049267323174881221596974668703450612816990104990000887
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/46.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---