e6706fcc7b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 45.337m | 99.865ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.620s | 38.633us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.620s | 29.677us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.660s | 1.632ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.740s | 54.294us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.400s | 59.809us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.620s | 29.677us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.740s | 54.294us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 10.819m | 333.711ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 5.173m | 524.882ms | 49 | 50 | 98.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 29.479m | 3.355s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 29.479m | 3.355s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.383h | 748.699ms | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.610s | 20.800us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.980s | 660.819us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.980s | 660.819us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.620s | 38.633us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 29.677us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.740s | 54.294us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.970s | 155.045us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.620s | 38.633us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 29.677us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.740s | 54.294us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.970s | 155.045us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 289 | 290 | 99.66 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.000s | 397.496us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.380s | 128.900us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.380s | 128.900us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 20.428m | 149.897ms | 11 | 50 | 22.00 |
| V3 | TOTAL | 11 | 50 | 22.00 | |||
| TOTAL | 580 | 620 | 93.55 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.51 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 98.98 |
UVM_ERROR (cip_base_vseq.sv:825) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
0.rv_timer_stress_all_with_rand_reset.905648610877811432233882895071480060695194275983715319407661368593443397713
Line 306, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15522143653 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 15522143653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.29369902864113257831111520210876971181876644036360409273205084727084439402003
Line 467, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 113486286948 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 113486286948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 34 more failures.
UVM_ERROR (cip_base_vseq.sv:749) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:
2.rv_timer_stress_all_with_rand_reset.43937935090148274134430525303091512261484687824990108259345392412082320310581
Line 528, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18187613520 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 18187613520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.rv_timer_stress_all_with_rand_reset.10806145935883343569876626041005314884748567379444813069623998798980639910090
Line 579, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/19.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 28486373397 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 28486373397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
18.rv_timer_disabled.100603817100980948334961671661866315715906099343996096861315351225097609070244
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/18.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---