RV_TIMER Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: `974aaab627`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	58.124m	159.600ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.570s	12.425us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.630s	29.975us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.830s	197.156us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.780s	205.692us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.390s	33.013us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.630s	29.975us	20	20	100.00
		rv_timer_csr_aliasing	0.780s	205.692us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	21.058m	147.063ms	50	50	100.00
V2	disabled	rv_timer_disabled	5.189m	418.638ms	49	50	98.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	22.880m	3.298s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	22.880m	3.298s	50	50	100.00
V2	stress	rv_timer_stress_all	1.553h	978.082ms	49	50	98.00
V2	intr_test	rv_timer_intr_test	0.620s	17.554us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.760s	1.084ms	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.760s	1.084ms	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.570s	12.425us	5	5	100.00
		rv_timer_csr_rw	0.630s	29.975us	20	20	100.00
		rv_timer_csr_aliasing	0.780s	205.692us	5	5	100.00
		rv_timer_same_csr_outstanding	0.840s	79.036us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.570s	12.425us	5	5	100.00
		rv_timer_csr_rw	0.630s	29.975us	20	20	100.00
		rv_timer_csr_aliasing	0.780s	205.692us	5	5	100.00
		rv_timer_same_csr_outstanding	0.840s	79.036us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	rv_timer_sec_cm	0.960s	388.485us	5	5	100.00
		rv_timer_tl_intg_err	1.500s	574.170us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.500s	574.170us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	42.513m	219.704ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			579	620	93.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.61	99.36	98.73	100.00	--	100.00	100.00	99.55

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:
- Test rv_timer_stress_all_with_rand_reset has 37 failures.
  - 0.rv_timer_stress_all_with_rand_reset.102725972753516705431507279897624919522235423383569393985463863550652591914424
    Line 668, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23190408550 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 23190408550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_timer_stress_all_with_rand_reset.90640839374478713701703816335518518057982015874240609142749412362970734411570
    Line 872, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 48900061078 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10009 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 48900061078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 35 more failures.
UVM_ERROR (cip_base_vseq.sv:758) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test rv_timer_stress_all_with_rand_reset has 2 failures.
  - 2.rv_timer_stress_all_with_rand_reset.66708663678817206439770892544554099067448530926928752586429526674257508174051
    Line 290, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5726344278 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 5726344278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.rv_timer_stress_all_with_rand_reset.83705386259646042169148295164782337434321484069249362423676460145937268687583
    Line 453, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/34.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33999919983 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 33999919983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test rv_timer_stress_all has 1 failures.
  - 25.rv_timer_stress_all.115223055349931693501564663277390926283416993972825703601821583096501455218234
    Line 299, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/25.rv_timer_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_timer_disabled has 1 failures.
  - 42.rv_timer_disabled.78136773574134090830358924223698321564192434538100258120981529187376054309255
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/42.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

RV_TIMER Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: 974aaab627

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `974aaab627`