RV_TIMER Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	56.639m	521.528ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.580s	30.872us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.610s	30.877us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.910s	1.638ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.780s	55.998us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.100s	24.211us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.610s	30.877us	20	20	100.00
		rv_timer_csr_aliasing	0.780s	55.998us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	17.280m	118.960ms	49	50	98.00
V2	disabled	rv_timer_disabled	4.784m	761.792ms	48	50	96.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	27.822m	6.187s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	27.822m	6.187s	50	50	100.00
V2	stress	rv_timer_stress_all	1.237h	1.387s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.640s	16.927us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.170s	168.339us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.170s	168.339us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.580s	30.872us	5	5	100.00
		rv_timer_csr_rw	0.610s	30.877us	20	20	100.00
		rv_timer_csr_aliasing	0.780s	55.998us	5	5	100.00
		rv_timer_same_csr_outstanding	0.840s	43.019us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.580s	30.872us	5	5	100.00
		rv_timer_csr_rw	0.610s	30.877us	20	20	100.00
		rv_timer_csr_aliasing	0.780s	55.998us	5	5	100.00
		rv_timer_same_csr_outstanding	0.840s	43.019us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	rv_timer_sec_cm	0.940s	85.540us	5	5	100.00
		rv_timer_tl_intg_err	1.340s	458.680us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.340s	458.680us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	26.442m	102.926ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			581	620	93.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.61	99.36	98.73	100.00	--	100.00	100.00	99.55

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
- Test rv_timer_stress_all_with_rand_reset has 34 failures.
  - 1.rv_timer_stress_all_with_rand_reset.104451541340146461000403010036089148600726323927858597081499951877057449391708
    Line 570, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 220368726885 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 220368726885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rv_timer_stress_all_with_rand_reset.60172067602698834009035865102463032503466721127966703831568453053250789342296
    Line 1086, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 305487665547 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10016 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 305487665547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 32 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test rv_timer_disabled has 2 failures.
  - 13.rv_timer_disabled.97966061835968018640256109021912119573669463172140121678111449552472925190299
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/13.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.rv_timer_disabled.72220300854810030032675372986259547948470812232328316083890325420535719543794
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/34.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_timer_random_reset has 1 failures.
  - 21.rv_timer_random_reset.11562321079191144014921673047389531386613328975933305187344104774946155431128
    Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/21.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:758) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test rv_timer_stress_all_with_rand_reset has 2 failures.
  - 3.rv_timer_stress_all_with_rand_reset.3209930653210964696098919058429418337802267330686572537638673310411071128416
    Line 884, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 74059774622 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 74059774622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.rv_timer_stress_all_with_rand_reset.48967974690135432479539642547636154661639305649548915218806240310857731322300
    Line 601, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/37.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 154213439562 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 154213439562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

RV_TIMER Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e971cd9798`