RV_TIMER Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 random rv_timer_random 56.639m 521.528ms 200 200 100.00
V1 csr_hw_reset rv_timer_csr_hw_reset 0.580s 30.872us 5 5 100.00
V1 csr_rw rv_timer_csr_rw 0.610s 30.877us 20 20 100.00
V1 csr_bit_bash rv_timer_csr_bit_bash 3.910s 1.638ms 5 5 100.00
V1 csr_aliasing rv_timer_csr_aliasing 0.780s 55.998us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_timer_csr_mem_rw_with_rand_reset 1.100s 24.211us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_timer_csr_rw 0.610s 30.877us 20 20 100.00
rv_timer_csr_aliasing 0.780s 55.998us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 random_reset rv_timer_random_reset 17.280m 118.960ms 49 50 98.00
V2 disabled rv_timer_disabled 4.784m 761.792ms 48 50 96.00
V2 cfg_update_on_fly rv_timer_cfg_update_on_fly 27.822m 6.187s 50 50 100.00
V2 no_interrupt_test rv_timer_cfg_update_on_fly 27.822m 6.187s 50 50 100.00
V2 stress rv_timer_stress_all 1.237h 1.387s 50 50 100.00
V2 intr_test rv_timer_intr_test 0.640s 16.927us 50 50 100.00
V2 tl_d_oob_addr_access rv_timer_tl_errors 3.170s 168.339us 20 20 100.00
V2 tl_d_illegal_access rv_timer_tl_errors 3.170s 168.339us 20 20 100.00
V2 tl_d_outstanding_access rv_timer_csr_hw_reset 0.580s 30.872us 5 5 100.00
rv_timer_csr_rw 0.610s 30.877us 20 20 100.00
rv_timer_csr_aliasing 0.780s 55.998us 5 5 100.00
rv_timer_same_csr_outstanding 0.840s 43.019us 20 20 100.00
V2 tl_d_partial_access rv_timer_csr_hw_reset 0.580s 30.872us 5 5 100.00
rv_timer_csr_rw 0.610s 30.877us 20 20 100.00
rv_timer_csr_aliasing 0.780s 55.998us 5 5 100.00
rv_timer_same_csr_outstanding 0.840s 43.019us 20 20 100.00
V2 TOTAL 287 290 98.97
V2S tl_intg_err rv_timer_sec_cm 0.940s 85.540us 5 5 100.00
rv_timer_tl_intg_err 1.340s 458.680us 20 20 100.00
V2S sec_cm_bus_integrity rv_timer_tl_intg_err 1.340s 458.680us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_timer_stress_all_with_rand_reset 26.442m 102.926ms 14 50 28.00
V3 TOTAL 14 50 28.00
TOTAL 581 620 93.71

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 5 71.43
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.61 99.36 98.73 100.00 -- 100.00 100.00 99.55

Failure Buckets

Past Results