c8985d6745| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 44.536m | 492.897ms | 199 | 200 | 99.50 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.580s | 17.781us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.620s | 36.910us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.380s | 564.436us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.840s | 39.010us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.360s | 60.289us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.620s | 36.910us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.840s | 39.010us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 254 | 255 | 99.61 | |||
| V2 | random_reset | rv_timer_random_reset | 19.919m | 135.422ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 5.820m | 237.746ms | 46 | 50 | 92.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 38.180m | 10.000s | 49 | 50 | 98.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 38.180m | 10.000s | 49 | 50 | 98.00 |
| V2 | stress | rv_timer_stress_all | 1.155h | 2.380s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.610s | 61.421us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.190s | 746.886us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.190s | 746.886us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.580s | 17.781us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 36.910us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.840s | 39.010us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.860s | 163.901us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.580s | 17.781us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 36.910us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.840s | 39.010us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.860s | 163.901us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 285 | 290 | 98.28 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.150s | 1.310ms | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.530s | 122.006us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.530s | 122.006us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 24.388m | 652.487ms | 16 | 50 | 32.00 |
| V3 | TOTAL | 16 | 50 | 32.00 | |||
| TOTAL | 580 | 620 | 93.55 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.64 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.77 |
UVM_ERROR (cip_base_vseq.sv:836) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
0.rv_timer_stress_all_with_rand_reset.36266984993611571948000650714295146945948304817606658442640107977201732364399
Line 713, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 123275528752 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10027 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 123275528752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_timer_stress_all_with_rand_reset.77107089146429580344765111076998824526164231115021491354225966303004254437040
Line 317, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 87060178517 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10012 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 87060178517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 32 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:
8.rv_timer_disabled.95347568863431331767933882591105053019927200534846845231475944858400609070624
Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/8.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.rv_timer_disabled.40082732282567337230099026793780432790146230482934545971965675870726095354316
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/15.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
11.rv_timer_cfg_update_on_fly.28206849006333524524016769196192543184775664379035526600004162275867002256057
Line 265, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/11.rv_timer_cfg_update_on_fly/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
130.rv_timer_random.24029554973330108724590339249546640108583850674231102226783032527117752911345
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/130.rv_timer_random/latest/run.log
Job ID: smart:f194c0c1-a1d8-43b3-a136-a807b686a866