RV_TIMER Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	45.453m	154.100ms	199	200	99.50
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.620s	24.736us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.640s	14.986us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.860s	377.257us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.840s	16.724us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.360s	38.927us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.640s	14.986us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	16.724us	5	5	100.00
V1		TOTAL			254	255	99.61
V2	random_reset	rv_timer_random_reset	19.868m	45.389ms	49	50	98.00
V2	disabled	rv_timer_disabled	5.285m	382.701ms	49	50	98.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	35.528m	5.415s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	35.528m	5.415s	50	50	100.00
V2	stress	rv_timer_stress_all	42.866m	2.404s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.650s	90.043us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.600s	198.959us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.600s	198.959us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.620s	24.736us	5	5	100.00
		rv_timer_csr_rw	0.640s	14.986us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	16.724us	5	5	100.00
		rv_timer_same_csr_outstanding	0.800s	23.183us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.620s	24.736us	5	5	100.00
		rv_timer_csr_rw	0.640s	14.986us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	16.724us	5	5	100.00
		rv_timer_same_csr_outstanding	0.800s	23.183us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	rv_timer_sec_cm	0.960s	94.339us	5	5	100.00
		rv_timer_tl_intg_err	1.390s	1.860ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.390s	1.860ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	22.338m	154.258ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			585	620	94.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.55	99.36	98.73	100.00	--	100.00	100.00	99.21

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
- Test rv_timer_stress_all_with_rand_reset has 31 failures.
  - 0.rv_timer_stress_all_with_rand_reset.10706587457190826390813785331427858111961926613707155439635990057873033746321
    Line 419, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 270817951678 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10022 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 270817951678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rv_timer_stress_all_with_rand_reset.84999790549225232495176026614716267114967220839124237871876895192910813355613
    Line 335, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12830982675 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 12830982675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 29 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test rv_timer_disabled has 1 failures.
  - 22.rv_timer_disabled.40530444200311112852502342222673838890342482098064555831777170341687287042926
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/22.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_timer_random_reset has 1 failures.
  - 49.rv_timer_random_reset.3885552112352020010777737525491533808026823901980782418787550412821340913496
    Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/49.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:755) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test rv_timer_stress_all_with_rand_reset has 1 failures.
  - 48.rv_timer_stress_all_with_rand_reset.77463431562797100685587079227567256892164352701204613051400367237416822134745
    Line 276, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/48.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2710857426 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2710857426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test rv_timer_random has 1 failures.
  - 112.rv_timer_random.37529453583463970751509124426204296862292562133043051279688644787256986656520
    Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/112.rv_timer_random/latest/run.log
```
  Job ID: smart:b181fc70-d5ea-4fd0-85a3-caaa62cbcf1f
```

RV_TIMER Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c8985d6745`