07b417ef03| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 56.724m | 104.629ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.610s | 23.922us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.590s | 105.888us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.790s | 1.627ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.830s | 75.474us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.710s | 38.522us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.590s | 105.888us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.830s | 75.474us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 27.362m | 222.969ms | 49 | 50 | 98.00 |
| V2 | disabled | rv_timer_disabled | 4.463m | 218.668ms | 45 | 50 | 90.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 23.349m | 3.905s | 49 | 50 | 98.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 23.349m | 3.905s | 49 | 50 | 98.00 |
| V2 | stress | rv_timer_stress_all | 39.120m | 7.615s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.670s | 28.149us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.180s | 2.804ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.180s | 2.804ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.610s | 23.922us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.590s | 105.888us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.830s | 75.474us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.820s | 43.006us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.610s | 23.922us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.590s | 105.888us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.830s | 75.474us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.820s | 43.006us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 283 | 290 | 97.59 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.900s | 1.423ms | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.480s | 3.869ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.480s | 3.869ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 21.505m | 180.633ms | 15 | 50 | 30.00 |
| V3 | TOTAL | 15 | 50 | 30.00 | |||
| TOTAL | 578 | 620 | 93.23 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 4 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.61 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.55 |
UVM_ERROR (cip_base_vseq.sv:836) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
0.rv_timer_stress_all_with_rand_reset.26551114994849356968032237639627088754343403762546445136078874362661011922216
Line 268, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 707928694 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 707928694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.20244501258906452102116254680263454133167775216049993405416618373401107338768
Line 273, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1723051130 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1723051130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 33 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 6 failures:
2.rv_timer_disabled.110491363431889483484778693370093660741100555193300738634765780109633064948796
Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.rv_timer_disabled.46719085533478310003362833195332605371063955129125408763424316849790227482586
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/11.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
31.rv_timer_random_reset.11717387032397401794642776520634820567123745929836340784892143997638149950407
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/31.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
12.rv_timer_cfg_update_on_fly.79568581514498932582046629169432588755422951415241549453173027087649721488546
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/12.rv_timer_cfg_update_on_fly/latest/run.log
Job ID: smart:2aea0b72-3b8a-42c0-ba6a-d805c2b39b13