07b417ef03| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 57.735m | 1.293s | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.580s | 25.020us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.620s | 25.281us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 2.760s | 1.381ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.880s | 148.109us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.530s | 637.398us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.620s | 25.281us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.880s | 148.109us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 13.979m | 64.215ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 5.435m | 783.560ms | 45 | 50 | 90.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 16.749m | 2.819s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 16.749m | 2.819s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 41.047m | 3.269s | 49 | 50 | 98.00 |
| V2 | intr_test | rv_timer_intr_test | 0.630s | 13.646us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.650s | 51.475us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.650s | 51.475us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.580s | 25.020us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 25.281us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.880s | 148.109us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 76.330us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.580s | 25.020us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 25.281us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.880s | 148.109us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 76.330us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 284 | 290 | 97.93 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.920s | 221.678us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.400s | 115.262us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.400s | 115.262us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 17.333m | 345.474ms | 15 | 50 | 30.00 |
| V3 | TOTAL | 15 | 50 | 30.00 | |||
| TOTAL | 579 | 620 | 93.39 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.55 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.21 |
UVM_ERROR (cip_base_vseq.sv:836) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
0.rv_timer_stress_all_with_rand_reset.32775509073022121857662489385830148151141744039410928181371745519697845540263
Line 329, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 168307894913 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 168307894913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_timer_stress_all_with_rand_reset.67640079470784961807251067737317538673199805860597122785029825753868217293409
Line 435, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 123999670838 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 123999670838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 32 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 6 failures:
4.rv_timer_disabled.108595088866177922497379473725411279293643839064972682870626378128073845528782
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.rv_timer_disabled.94051911473968573269774978610079853655665853320745320541495995821483405980487
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/28.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
17.rv_timer_stress_all.96106970736683367975092345210422358612130927686074679410808242369977410726306
Line 267, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/17.rv_timer_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:755) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
4.rv_timer_stress_all_with_rand_reset.99508132988356131352143880696944568943307127516198682243071260453393846382869
Line 707, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 60868822967 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 60868822967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---