3707c48f56| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 40.852m | 222.655ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.590s | 15.527us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.640s | 16.192us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.090s | 337.904us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.810s | 17.833us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.770s | 76.916us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.640s | 16.192us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.810s | 17.833us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 16.717m | 62.227ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 5.816m | 964.780ms | 46 | 50 | 92.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 20.299m | 888.277ms | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 20.299m | 888.277ms | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.660h | 1.887s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.590s | 18.810us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.970s | 382.481us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.970s | 382.481us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.590s | 15.527us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.640s | 16.192us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.810s | 17.833us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.780s | 117.423us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.590s | 15.527us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.640s | 16.192us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.810s | 17.833us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.780s | 117.423us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 286 | 290 | 98.62 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.870s | 117.222us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.410s | 166.414us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.410s | 166.414us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 15.060m | 529.100ms | 10 | 50 | 20.00 |
| V3 | TOTAL | 10 | 50 | 20.00 | |||
| TOTAL | 576 | 620 | 92.90 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.64 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.77 |
UVM_ERROR (cip_base_vseq.sv:836) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 39 failures:
0.rv_timer_stress_all_with_rand_reset.53274438109647321066607972209355328387893909917949008393633145966662406825822
Line 350, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 30344164553 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 30344164553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.31424657984579984063873715050268190426035739623088044733293695479445895312497
Line 516, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 26143124798 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 26143124798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 37 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
9.rv_timer_disabled.12307557412639159111956797109425427369232864135396173468674236369662507341436
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.rv_timer_disabled.95468947878820850917874121819371643230564190035745210242847081541282831228317
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/16.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:755) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
13.rv_timer_stress_all_with_rand_reset.30561583065249997757121195790690250079073343459987010588432394783493262934001
Line 458, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/13.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 205219421848 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 205219421848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---