RV_TIMER Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	50.660m	1.517s	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.600s	15.615us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.650s	18.166us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.470s	533.503us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.810s	51.989us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.290s	33.494us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.650s	18.166us	20	20	100.00
		rv_timer_csr_aliasing	0.810s	51.989us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	8.451m	103.337ms	49	50	98.00
V2	disabled	rv_timer_disabled	5.584m	427.451ms	49	50	98.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	35.970m	4.345s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	35.970m	4.345s	50	50	100.00
V2	stress	rv_timer_stress_all	1.167h	625.996ms	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.620s	126.522us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.840s	58.297us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.840s	58.297us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.600s	15.615us	5	5	100.00
		rv_timer_csr_rw	0.650s	18.166us	20	20	100.00
		rv_timer_csr_aliasing	0.810s	51.989us	5	5	100.00
		rv_timer_same_csr_outstanding	0.860s	162.491us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.600s	15.615us	5	5	100.00
		rv_timer_csr_rw	0.650s	18.166us	20	20	100.00
		rv_timer_csr_aliasing	0.810s	51.989us	5	5	100.00
		rv_timer_same_csr_outstanding	0.860s	162.491us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	rv_timer_sec_cm	0.940s	271.861us	5	5	100.00
		rv_timer_tl_intg_err	1.410s	215.962us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.410s	215.962us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	21.234m	126.203ms	10	50	20.00
V3		TOTAL			10	50	20.00
		TOTAL			578	620	93.23

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.64	99.36	98.73	100.00	--	100.00	100.00	99.77

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 38 failures:
- Test rv_timer_stress_all_with_rand_reset has 38 failures.
  - 0.rv_timer_stress_all_with_rand_reset.110479045745976639523937693772439026056275849824109545228354455381648050507337
    Line 431, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18885833511 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 18885833511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rv_timer_stress_all_with_rand_reset.36627888346061004392746725521010286434338405125382550618718779146741126335433
    Line 587, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 73605914355 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 73605914355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 36 more failures.
UVM_ERROR (cip_base_vseq.sv:755) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test rv_timer_stress_all_with_rand_reset has 2 failures.
  - 6.rv_timer_stress_all_with_rand_reset.41183563075771564176390169752807647249940345200902035631402509076015513431970
    Line 551, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 106542029355 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 106542029355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.rv_timer_stress_all_with_rand_reset.112343863044949971717029083973646068301881331064354653072235490106322794161623
    Line 297, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/38.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1174690533 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1174690533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test rv_timer_random_reset has 1 failures.
  - 12.rv_timer_random_reset.9461279505003104343214470725608877653128579814762855830612646561903870121747
    Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/12.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_timer_disabled has 1 failures.
  - 25.rv_timer_disabled.32278772257831164204137667854342025721346208275778234126462480974140689666153
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/25.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

RV_TIMER Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `07b417ef03`