34b8fc33e3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 41.587m | 265.653ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.860s | 16.928us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.860s | 37.851us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 4.480s | 343.813us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 1.230s | 39.203us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.910s | 111.555us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.860s | 37.851us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 1.230s | 39.203us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 19.743m | 137.843ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 8.145m | 345.616ms | 47 | 50 | 94.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 33.056m | 5.770s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 33.056m | 5.770s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.549h | 3.250s | 49 | 50 | 98.00 |
| V2 | intr_test | rv_timer_intr_test | 0.850s | 15.572us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 4.030s | 176.087us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 4.030s | 176.087us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.860s | 16.928us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.860s | 37.851us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 1.230s | 39.203us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.210s | 35.225us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.860s | 16.928us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.860s | 37.851us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 1.230s | 39.203us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.210s | 35.225us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 286 | 290 | 98.62 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.280s | 918.488us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 2.080s | 121.429us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 2.080s | 121.429us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 1.187m | 5.234ms | 15 | 50 | 30.00 |
| V3 | TOTAL | 15 | 50 | 30.00 | |||
| TOTAL | 581 | 620 | 93.71 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.60 | 99.36 | 99.04 | 100.00 | -- | 100.00 | 100.00 | 99.21 |
UVM_ERROR (cip_base_vseq.sv:867) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
0.rv_timer_stress_all_with_rand_reset.91859783461367466010821474825413223143272899290971897888106466220447932959369
Line 125, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5035089797 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10017 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5035089797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.83182211613056786807231055768505319352244955608197744255821926959423332534278
Line 70, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4775347769 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4775347769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 31 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
11.rv_timer_disabled.88202802804110611034790236753070925443355104241263873989198905170681377138909
Line 66, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_timer-sim-vcs/11.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.rv_timer_disabled.71831017017239748142373896854786662801348816500297353152276494071623315388814
Line 63, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_timer-sim-vcs/15.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
13.rv_timer_stress_all.44207188838678924382490121177627501095706514098972851175677496411350068716654
Line 97, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_timer-sim-vcs/13.rv_timer_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:771) [rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
16.rv_timer_stress_all_with_rand_reset.40512333085242203126404032352855426741988905137139979492706567658438939885504
Line 64, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_timer-sim-vcs/16.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 49080779 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 49080779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.rv_timer_stress_all_with_rand_reset.40738589155875798238606189576271849993192517371090668129499109190287607238583
Line 93, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_timer-sim-vcs/41.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3200412166 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3200412166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---