RV_TIMER Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: `0825c81be0`

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	43.135m	98.193ms	199	200	99.50
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.520s	44.722us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.830s	20.213us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.320s	195.542us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.710s	17.526us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.780s	99.092us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.830s	20.213us	20	20	100.00
		rv_timer_csr_aliasing	0.710s	17.526us	5	5	100.00
V1		TOTAL			254	255	99.61
V2	random_reset	rv_timer_random_reset	22.715m	169.305ms	49	50	98.00
V2	disabled	rv_timer_disabled	4.331m	176.731ms	49	50	98.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	15.436m	5.197s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	15.436m	5.197s	50	50	100.00
V2	stress	rv_timer_stress_all	34.433m	2.817s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.870s	39.848us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.350s	191.369us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.350s	191.369us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.520s	44.722us	5	5	100.00
		rv_timer_csr_rw	0.830s	20.213us	20	20	100.00
		rv_timer_csr_aliasing	0.710s	17.526us	5	5	100.00
		rv_timer_same_csr_outstanding	0.950s	82.948us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.520s	44.722us	5	5	100.00
		rv_timer_csr_rw	0.830s	20.213us	20	20	100.00
		rv_timer_csr_aliasing	0.710s	17.526us	5	5	100.00
		rv_timer_same_csr_outstanding	0.950s	82.948us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	rv_timer_sec_cm	0.800s	76.452us	5	5	100.00
		rv_timer_tl_intg_err	1.480s	71.575us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.480s	71.575us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.124m	6.106ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			580	620	93.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.64	99.36	99.04	100.00	--	100.00	100.00	99.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:
- Test rv_timer_stress_all_with_rand_reset has 37 failures.
  - 1.rv_timer_stress_all_with_rand_reset.13634019176844204387813515512178869359013731728017578536640268981234607683994
    Line 183, in log /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12165156124 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 12165156124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rv_timer_stress_all_with_rand_reset.101051636251912465191440814403295295579514826174909805509534709293088523109008
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 40142127171 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 40142127171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 35 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test rv_timer_random_reset has 1 failures.
  - 3.rv_timer_random_reset.110117044805691824531921171902457730859501286313083966086750171365608853594701
    Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/3.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_timer_disabled has 1 failures.
  - 33.rv_timer_disabled.73552598085553843905527721034072105052997962680516149343000886044376391326195
    Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/33.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test rv_timer_random has 1 failures.
  - 120.rv_timer_random.73335401233134008698166571498567621851094515541962338382841443875841951121098
    Log /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/120.rv_timer_random/latest/run.log
```
  Job timed out after 60 minutes
```

RV_TIMER Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0825c81be0`