e733a8ef8a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 55.761m | 218.978ms | 199 | 200 | 99.50 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.890s | 59.495us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.880s | 15.955us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 5.590s | 543.232us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 1.100s | 45.967us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 2.780s | 74.785us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.880s | 15.955us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 1.100s | 45.967us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 254 | 255 | 99.61 | |||
| V2 | random_reset | rv_timer_random_reset | 33.700m | 174.981ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 9.307m | 185.497ms | 46 | 50 | 92.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 33.271m | 5.411s | 49 | 50 | 98.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 33.271m | 5.411s | 49 | 50 | 98.00 |
| V2 | stress | rv_timer_stress_all | 2.000h | 658.404ms | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.870s | 17.470us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 4.760s | 283.185us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 4.760s | 283.185us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.890s | 59.495us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.880s | 15.955us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 1.100s | 45.967us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.230s | 376.746us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.890s | 59.495us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.880s | 15.955us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 1.100s | 45.967us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.230s | 376.746us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 285 | 290 | 98.28 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.290s | 170.186us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 2.170s | 215.921us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 2.170s | 215.921us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 1.452m | 7.275ms | 12 | 50 | 24.00 |
| V3 | TOTAL | 12 | 50 | 24.00 | |||
| TOTAL | 576 | 620 | 92.90 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.53 | 99.36 | 99.04 | 100.00 | -- | 100.00 | 100.00 | 98.75 |
UVM_ERROR (cip_base_vseq.sv:867) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 38 failures:
0.rv_timer_stress_all_with_rand_reset.88587844603095095568339346665065986774060724261803692383882477946613735365272
Line 92, in log /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8397953671 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10053 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8397953671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.16981204573933059837764105529922292770952020508933357440172318758521138490557
Line 124, in log /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2552672336 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2552672336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 36 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
5.rv_timer_disabled.57719142726900453391498845204112163400112491384001699627189071996984679938491
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/5.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_timer_disabled.81022909772498511562713576203308683026851521703028384256306279818548337803623
Line 64, in log /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/6.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Job timed out after * minutes has 2 failures:
Test rv_timer_cfg_update_on_fly has 1 failures.
12.rv_timer_cfg_update_on_fly.82775857164052445539994953856575438882604964095599298459782121512193793954631
Log /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/12.rv_timer_cfg_update_on_fly/latest/run.log
Job timed out after 60 minutes
Test rv_timer_random has 1 failures.
76.rv_timer_random.63960649042169624721169599727739528242348741577943355233484799400084405834533
Log /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/76.rv_timer_random/latest/run.log
Job timed out after 60 minutes