4674f625b3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 57.234m | 2.041s | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.610s | 63.675us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.700s | 17.143us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.380s | 286.560us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.730s | 45.049us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.420s | 25.775us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.700s | 17.143us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.730s | 45.049us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 35.751m | 205.862ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 7.820m | 1.000s | 47 | 50 | 94.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 37.984m | 7.839s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 37.984m | 7.839s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.699h | 2.239s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.650s | 16.873us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.670s | 208.075us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.670s | 208.075us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.610s | 63.675us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.700s | 17.143us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.730s | 45.049us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.770s | 15.505us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.610s | 63.675us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.700s | 17.143us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.730s | 45.049us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.770s | 15.505us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 287 | 290 | 98.97 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.460s | 486.310us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.370s | 1.162ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.370s | 1.162ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 1.453m | 5.545ms | 13 | 50 | 26.00 |
| V3 | TOTAL | 13 | 50 | 26.00 | |||
| TOTAL | 580 | 620 | 93.55 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.70 | 99.36 | 99.04 | 100.00 | -- | 100.00 | 100.00 | 99.77 |
UVM_ERROR (cip_base_vseq.sv:867) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:
0.rv_timer_stress_all_with_rand_reset.49545225953015384058049262976798871042930234564968815824388215895436601864433
Line 140, in log /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2118445731 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2118445731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.62322408430170878115634937026576694116451259571263059902231547576912106667984
Line 77, in log /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7915427947 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7915427947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 35 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
5.rv_timer_disabled.28848742869757863903243597666883745546753836511504329247173073873582017571285
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/5.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.rv_timer_disabled.71634216913860988319452811898792170352295602798473565431911419367129088028922
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/40.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.