RV_TIMER Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: `1cb1c3d135`

Branch: os_regression_2024_10_02

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	55.682m	230.733ms	199	200	99.50
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.610s	13.610us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.600s	33.659us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.470s	281.559us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.840s	37.620us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.350s	58.115us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.600s	33.659us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	37.620us	5	5	100.00
V1		TOTAL			254	255	99.61
V2	random_reset	rv_timer_random_reset	41.554m	645.461ms	50	50	100.00
V2	disabled	rv_timer_disabled	8.474m	710.832ms	47	50	94.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	28.325m	672.265ms	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	28.325m	672.265ms	50	50	100.00
V2	stress	rv_timer_stress_all	1.194h	3.105s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.630s	53.849us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.680s	58.650us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.680s	58.650us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.610s	13.610us	5	5	100.00
		rv_timer_csr_rw	0.600s	33.659us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	37.620us	5	5	100.00
		rv_timer_same_csr_outstanding	0.790s	149.138us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.610s	13.610us	5	5	100.00
		rv_timer_csr_rw	0.600s	33.659us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	37.620us	5	5	100.00
		rv_timer_same_csr_outstanding	0.790s	149.138us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	rv_timer_sec_cm	1.110s	69.957us	5	5	100.00
		rv_timer_tl_intg_err	1.350s	411.895us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.350s	411.895us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.293m	15.356ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			580	620	93.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	6	85.71
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	99.33	99.04	100.00	--	100.00	100.00	99.66

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
- Test rv_timer_stress_all_with_rand_reset has 36 failures.
  - 0.rv_timer_stress_all_with_rand_reset.90591006708306189680061051279313676797678906780241801134897012355681528399785
    Line 64, in log /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 104902604 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 104902604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_timer_stress_all_with_rand_reset.70600027861018227818433912862573926403463438989225828138939253270241538567627
    Line 71, in log /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13550272786 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13550272786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 34 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test rv_timer_disabled has 3 failures.
  - 16.rv_timer_disabled.94440834224868582090424946796698821378089996845002573281228156144488994404367
    Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/16.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.rv_timer_disabled.60684417346406745676998008506544776698103618390019537797486276133519053180848
    Line 63, in log /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/27.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Job timed out after * minutes has 1 failures:
- Test rv_timer_random has 1 failures.
  - 65.rv_timer_random.100831292441590247041051758744445076246876634662012515402904463737610995059142
    Log /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/65.rv_timer_random/latest/run.log
```
  Job timed out after 60 minutes
```

RV_TIMER Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: 1cb1c3d135

Branch: os_regression_2024_10_02

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `1cb1c3d135`