29d22a60a2| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 57.419m | 733.897ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.900s | 21.207us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.910s | 17.119us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 4.940s | 1.005ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 1.230s | 35.814us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 2.340s | 118.146us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.910s | 17.119us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 1.230s | 35.814us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 14.063m | 49.886ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 6.373m | 378.618ms | 49 | 50 | 98.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 29.927m | 6.641s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 29.927m | 6.641s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.035h | 1.267s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.880s | 29.017us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 4.190s | 676.474us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 4.190s | 676.474us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.900s | 21.207us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.910s | 17.119us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 1.230s | 35.814us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.280s | 40.099us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.900s | 21.207us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.910s | 17.119us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 1.230s | 35.814us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.280s | 40.099us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 289 | 290 | 99.66 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.850s | 301.031us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 2.330s | 1.228ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 2.330s | 1.228ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 1.698m | 10.927ms | 12 | 50 | 24.00 |
| V3 | TOTAL | 12 | 50 | 24.00 | |||
| TOTAL | 581 | 620 | 93.71 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.63 | 99.33 | 99.04 | 100.00 | -- | 100.00 | 100.00 | 99.43 |
UVM_ERROR (cip_base_vseq.sv:867) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 38 failures:
0.rv_timer_stress_all_with_rand_reset.97728496892935108930836321298422962410261977607232009995690292049436779842163
Line 115, in log /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2865249792 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2865249792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.76721620863085192639556922866198895032578181028616114920381605436502702194764
Line 121, in log /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2599312637 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2599312637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 36 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
48.rv_timer_disabled.8204821935956756343111268044250914613209609372869999662781478910259712822803
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/48.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---