7e34e67ade| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 44.051m | 374.025ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.910s | 21.075us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.900s | 31.288us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.180s | 241.518us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 1.260s | 39.099us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 2.560s | 141.402us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.900s | 31.288us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 1.260s | 39.099us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 15.643m | 85.739ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 6.092m | 612.333ms | 47 | 50 | 94.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 28.540m | 1.745s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 28.540m | 1.745s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.667h | 2.184s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.880s | 19.142us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 4.210s | 562.292us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 4.210s | 562.292us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.910s | 21.075us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.900s | 31.288us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 1.260s | 39.099us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.260s | 637.621us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.910s | 21.075us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.900s | 31.288us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 1.260s | 39.099us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.260s | 637.621us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 287 | 290 | 98.97 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.170s | 81.394us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 2.690s | 322.732us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 2.690s | 322.732us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 1.536m | 7.020ms | 13 | 50 | 26.00 |
| V3 | TOTAL | 13 | 50 | 26.00 | |||
| TOTAL | 580 | 620 | 93.55 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.71 | 99.33 | 99.04 | 100.00 | -- | 100.00 | 100.00 | 99.89 |
UVM_ERROR (cip_base_vseq.sv:867) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
0.rv_timer_stress_all_with_rand_reset.103168749033123022144963832636896514112678408192294761167372851561032850956910
Line 80, in log /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 427845836 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10039 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 427845836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_timer_stress_all_with_rand_reset.105815314020664840754668431823977929309708500831285836820890435710077109447095
Line 150, in log /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5459661119 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10010 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5459661119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 34 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
0.rv_timer_disabled.9293569184761175753609107746728699034189693122315107917410214232214733483696
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/0.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.rv_timer_disabled.104587198097603571625725846988630475265979006225080985974204244249324053606766
Line 64, in log /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/11.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:771) [rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
49.rv_timer_stress_all_with_rand_reset.64126171074950493461761662904559532617374144841459437791213844476848463672845
Line 111, in log /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/49.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8844976511 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 8844976511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---