RV_TIMER Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: `78ad89d1aa`

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	51.160m	138.716ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.960s	21.719us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.940s	44.367us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	5.710s	531.806us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.400s	35.070us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.460s	61.731us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.940s	44.367us	20	20	100.00
		rv_timer_csr_aliasing	1.400s	35.070us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	26.668m	110.977ms	47	50	94.00
V2	disabled	rv_timer_disabled	7.699m	161.832ms	44	50	88.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	18.791m	454.619ms	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	18.791m	454.619ms	50	50	100.00
V2	stress	rv_timer_stress_all	1.654h	1.524s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.970s	56.506us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	4.470s	61.655us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	4.470s	61.655us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.960s	21.719us	5	5	100.00
		rv_timer_csr_rw	0.940s	44.367us	20	20	100.00
		rv_timer_csr_aliasing	1.400s	35.070us	5	5	100.00
		rv_timer_same_csr_outstanding	1.220s	63.650us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.960s	21.719us	5	5	100.00
		rv_timer_csr_rw	0.940s	44.367us	20	20	100.00
		rv_timer_csr_aliasing	1.400s	35.070us	5	5	100.00
		rv_timer_same_csr_outstanding	1.220s	63.650us	20	20	100.00
V2		TOTAL			281	290	96.90
V2S	tl_intg_err	rv_timer_sec_cm	1.530s	158.560us	5	5	100.00
		rv_timer_tl_intg_err	2.260s	175.517us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.260s	175.517us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.358m	5.229ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			577	620	93.06

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	99.33	99.04	100.00	--	100.00	100.00	99.66

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
- Test rv_timer_stress_all_with_rand_reset has 34 failures.
  - 0.rv_timer_stress_all_with_rand_reset.51834613529919788404741016169934560177708784453149664492028917480251867946123
    Line 70, in log /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1867867281 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1867867281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_timer_stress_all_with_rand_reset.97650147470536122389565801696360211949609772946083957041305151017149582336464
    Line 73, in log /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4442130244 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4442130244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 32 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 9 failures:
- Test rv_timer_disabled has 6 failures.
  - 6.rv_timer_disabled.13940238008371261184209968264835512829590927079934322262445758405108136100581
    Line 67, in log /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/6.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.rv_timer_disabled.17004926701022310715847622479480719758874470102199912382993112951897800052
    Line 63, in log /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/22.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
- Test rv_timer_random_reset has 3 failures.
  - 17.rv_timer_random_reset.50340753371564160738980749928896533031716129283050284686725574752533051178884
    Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/17.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.rv_timer_random_reset.72912818861447569087701550579953617631399122489492708126251518294371393934280
    Line 67, in log /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/35.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

RV_TIMER Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `78ad89d1aa`