30db5a999
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | spi_device_smoke | 1.350s | 353.032us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.490s | 154.189us | 5 | 5 | 100.00 |
V1 | csr_rw | spi_device_csr_rw | 2.680s | 146.598us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | spi_device_csr_bit_bash | 43.790s | 29.869ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | spi_device_csr_aliasing | 26.790s | 457.345us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 2.900s | 57.947us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.680s | 146.598us | 20 | 20 | 100.00 |
spi_device_csr_aliasing | 26.790s | 457.345us | 5 | 5 | 100.00 | ||
V1 | mem_walk | spi_device_mem_walk | 14.910s | 2.722ms | 5 | 5 | 100.00 |
V1 | mem_partial_access | spi_device_mem_partial_access | 4.700s | 263.341us | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 115 | 100.00 | |||
V2 | base_random_seq | spi_device_txrx | 13.868m | 51.443ms | 50 | 50 | 100.00 |
V2 | fifo_full | spi_device_fifo_full | 45.167m | 186.774ms | 50 | 50 | 100.00 |
V2 | fifo_underflow_overflow | spi_device_fifo_underflow_overflow | 43.390m | 1.162s | 47 | 50 | 94.00 |
V2 | dummy_sck_and_dummy_csb | spi_device_dummy_item_extra_dly | 25.000m | 66.233ms | 50 | 50 | 100.00 |
V2 | extra_delay_on_spi | spi_device_dummy_item_extra_dly | 25.000m | 66.233ms | 50 | 50 | 100.00 |
V2 | tx_async_fifo_reset | spi_device_tx_async_fifo_reset | 0.820s | 14.499us | 50 | 50 | 100.00 |
V2 | rx_async_fifo_reset | spi_device_rx_async_fifo_reset | 0.960s | 173.482us | 48 | 50 | 96.00 |
V2 | interrupts | spi_device_intr | 1.495m | 19.898ms | 50 | 50 | 100.00 |
V2 | abort | spi_device_abort | 0.790s | 26.676us | 50 | 50 | 100.00 |
V2 | byte_transfer_on_spi | spi_device_byte_transfer | 3.860s | 5.498ms | 50 | 50 | 100.00 |
V2 | rx_timeout | spi_device_rx_timeout | 6.550s | 13.728ms | 50 | 50 | 100.00 |
V2 | bit_transfer_on_spi | spi_device_bit_transfer | 3.190s | 196.810us | 50 | 50 | 100.00 |
V2 | extreme_fifo_setting | spi_device_extreme_fifo_size | 1.234h | 86.656ms | 50 | 50 | 100.00 |
V2 | perf | spi_device_perf | 48.591m | 45.658ms | 49 | 50 | 98.00 |
V2 | csb_read | spi_device_csb_read | 0.860s | 52.024us | 50 | 50 | 100.00 |
V2 | mem_parity | spi_device_mem_parity | 1.110s | 28.913us | 19 | 20 | 95.00 |
V2 | mem_cfg | spi_device_ram_cfg | 0.800s | 16.619us | 20 | 20 | 100.00 |
V2 | tpm_read | spi_device_tpm_rw | 11.580s | 283.800us | 50 | 50 | 100.00 |
V2 | tpm_write | spi_device_tpm_rw | 11.580s | 283.800us | 50 | 50 | 100.00 |
V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 35.370s | 51.109ms | 50 | 50 | 100.00 |
spi_device_tpm_sts_read | 1.270s | 193.217us | 50 | 50 | 100.00 | ||
V2 | tpm_fully_random_case | spi_device_tpm_all | 3.220m | 48.856ms | 50 | 50 | 100.00 |
V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 57.600s | 22.575ms | 50 | 50 | 100.00 |
spi_device_flash_all | 6.850m | 339.153ms | 50 | 50 | 100.00 | ||
V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 47.990s | 60.578ms | 50 | 50 | 100.00 |
spi_device_flash_all | 6.850m | 339.153ms | 50 | 50 | 100.00 | ||
V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 47.990s | 60.578ms | 50 | 50 | 100.00 |
spi_device_flash_all | 6.850m | 339.153ms | 50 | 50 | 100.00 | ||
V2 | cmd_info_slots | spi_device_flash_all | 6.850m | 339.153ms | 50 | 50 | 100.00 |
V2 | cmd_read_status | spi_device_intercept | 15.150s | 6.331ms | 50 | 50 | 100.00 |
spi_device_flash_all | 6.850m | 339.153ms | 50 | 50 | 100.00 | ||
V2 | cmd_read_jedec | spi_device_intercept | 15.150s | 6.331ms | 50 | 50 | 100.00 |
spi_device_flash_all | 6.850m | 339.153ms | 50 | 50 | 100.00 | ||
V2 | cmd_read_sfdp | spi_device_intercept | 15.150s | 6.331ms | 50 | 50 | 100.00 |
spi_device_flash_all | 6.850m | 339.153ms | 50 | 50 | 100.00 | ||
V2 | cmd_fast_read | spi_device_intercept | 15.150s | 6.331ms | 50 | 50 | 100.00 |
spi_device_flash_all | 6.850m | 339.153ms | 50 | 50 | 100.00 | ||
V2 | flash_cmd_upload | spi_device_upload | 57.160s | 21.234ms | 50 | 50 | 100.00 |
V2 | mailbox_command | spi_device_mailbox | 45.610s | 16.513ms | 50 | 50 | 100.00 |
V2 | mailbox_cross_outside_command | spi_device_mailbox | 45.610s | 16.513ms | 50 | 50 | 100.00 |
V2 | mailbox_cross_inside_command | spi_device_mailbox | 45.610s | 16.513ms | 50 | 50 | 100.00 |
V2 | cmd_read_buffer | spi_device_flash_mode | 1.028m | 54.930ms | 50 | 50 | 100.00 |
spi_device_read_buffer_direct | 8.010s | 4.473ms | 50 | 50 | 100.00 | ||
V2 | cmd_dummy_cycle | spi_device_mailbox | 45.610s | 16.513ms | 50 | 50 | 100.00 |
spi_device_flash_all | 6.850m | 339.153ms | 50 | 50 | 100.00 | ||
V2 | quad_spi | spi_device_flash_all | 6.850m | 339.153ms | 50 | 50 | 100.00 |
V2 | dual_spi | spi_device_flash_all | 6.850m | 339.153ms | 50 | 50 | 100.00 |
V2 | 4b_3b_feature | spi_device_cfg_cmd | 13.620s | 23.726ms | 50 | 50 | 100.00 |
V2 | write_enable_disable | spi_device_cfg_cmd | 13.620s | 23.726ms | 50 | 50 | 100.00 |
V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 12.630m | 728.409ms | 50 | 50 | 100.00 |
V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 17.310m | 258.293ms | 50 | 50 | 100.00 |
V2 | stress_all | spi_device_stress_all | 1.014h | 232.776ms | 16 | 50 | 32.00 |
V2 | alert_test | spi_device_alert_test | 0.790s | 11.865us | 50 | 50 | 100.00 |
V2 | intr_test | spi_device_intr_test | 0.800s | 81.183us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | spi_device_tl_errors | 5.900s | 203.457us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | spi_device_tl_errors | 5.900s | 203.457us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.490s | 154.189us | 5 | 5 | 100.00 |
spi_device_csr_rw | 2.680s | 146.598us | 20 | 20 | 100.00 | ||
spi_device_csr_aliasing | 26.790s | 457.345us | 5 | 5 | 100.00 | ||
spi_device_same_csr_outstanding | 4.960s | 866.727us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.490s | 154.189us | 5 | 5 | 100.00 |
spi_device_csr_rw | 2.680s | 146.598us | 20 | 20 | 100.00 | ||
spi_device_csr_aliasing | 26.790s | 457.345us | 5 | 5 | 100.00 | ||
spi_device_same_csr_outstanding | 4.960s | 866.727us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 1639 | 1680 | 97.56 | |||
V2S | tl_intg_err | spi_device_sec_cm | 1.210s | 302.923us | 5 | 5 | 100.00 |
spi_device_tl_intg_err | 23.860s | 1.093ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 23.860s | 1.093ms | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 1779 | 1820 | 97.75 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 8 | 100.00 |
V2 | 36 | 36 | 31 | 86.11 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 0 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
96.93 | 99.01 | 96.23 | 98.63 | 92.06 | 97.95 | 96.16 | 98.49 |
UVM_ERROR (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch
has 30 failures:
0.spi_device_stress_all.3201214241
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_stress_all/latest/run.log
UVM_ERROR @ 112887013693 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x4a [1001010] vs 0xaf [10101111]) addr 0xec30fbb4 read out mismatch
UVM_ERROR @ 112887013693 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x20 [100000] vs 0xc3 [11000011]) addr 0xec30fbb5 read out mismatch
UVM_ERROR @ 112887013693 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x95 [10010101] vs 0x37 [110111]) addr 0xec30fbb6 read out mismatch
UVM_ERROR @ 112887013693 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x32 [110010] vs 0x61 [1100001]) addr 0xec30fbb7 read out mismatch
UVM_ERROR @ 112887513691 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x81 [10000001] vs 0xc0 [11000000]) addr 0xec30fbb8 read out mismatch
1.spi_device_stress_all.1080057683
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_stress_all/latest/run.log
UVM_ERROR @ 149085808268 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xf0 [11110000] vs 0x38 [111000]) addr 0x6334113c read out mismatch
UVM_ERROR @ 149085808268 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x4b [1001011] vs 0x24 [100100]) addr 0x6334113d read out mismatch
UVM_ERROR @ 149085808268 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x8b [10001011] vs 0x4b [1001011]) addr 0x6334113e read out mismatch
UVM_ERROR @ 149085808268 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xff [11111111] vs 0xfb [11111011]) addr 0x6334113f read out mismatch
UVM_ERROR @ 149089192924 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xcb [11001011] vs 0x80 [10000000]) addr 0x63341140 read out mismatch
... and 28 more failures.
Offending '(!dst_pulse_o)'
has 2 failures:
5.spi_device_fifo_underflow_overflow.3411790965
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/5.spi_device_fifo_underflow_overflow/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 568752072 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
"../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv", 96: tb.dut.u_rxf_overflow.DstPulseCheck_A: started at 2297053374ps failed at 2297063475ps
Offending '(!dst_pulse_o)'
UVM_ERROR @ 2297063475 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
11.spi_device_fifo_underflow_overflow.1621578709
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/11.spi_device_fifo_underflow_overflow/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 7432832388 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_INFO @ 23339376306 ps: (spi_device_txrx_vseq.sv:109) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_fifo_underflow_overflow_vseq] starting sequence 2/2
Starting assertion attempts at time 45659513199ps: level = 0 arg = tb.dut.u_txf_underflow.SrcPulseCheck_M (from inst vcs_paramclassrepository (../src/lowrisc_dv_spi_device_env_0.1/seq_lib/spi_device_base_vseq.sv:454))
Starting assertion attempts at time 45659513199ps: level = 0 arg = tb.dut.u_txf_underflow.DstPulseCheck_A (from inst vcs_paramclassrepository (../src/lowrisc_dv_spi_device_env_0.1/seq_lib/spi_device_base_vseq.sv:455))
UVM_ERROR (spi_device_scoreboard.sv:1372) [scoreboard] Check failed rx_word_q.size == * (* [*] vs * [*])
has 2 failures:
7.spi_device_rx_async_fifo_reset.2969210103
Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/7.spi_device_rx_async_fifo_reset/latest/run.log
UVM_ERROR @ 66266253 ps: (spi_device_scoreboard.sv:1372) [uvm_test_top.env.scoreboard] Check failed rx_word_q.size == 0 (2 [0x2] vs 0 [0x0])
UVM_INFO @ 66266253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.spi_device_rx_async_fifo_reset.553002093
Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/12.spi_device_rx_async_fifo_reset/latest/run.log
UVM_ERROR @ 74824475 ps: (spi_device_scoreboard.sv:1372) [uvm_test_top.env.scoreboard] Check failed rx_word_q.size == 0 (2 [0x2] vs 0 [0x0])
UVM_INFO @ 74824475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job spi_device-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 2 failures:
Test spi_device_stress_all has 1 failures.
30.spi_device_stress_all.986581392
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/30.spi_device_stress_all/latest/run.log
Job ID: smart:df1c394e-7880-42b8-b6c5-b1e0a1e741a8
Test spi_device_perf has 1 failures.
48.spi_device_perf.803289339
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/48.spi_device_perf/latest/run.log
Job ID: smart:4e28be1a-3b76-4bd6-a092-da481951e56c
UVM_ERROR (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (* [*] vs * [*]) get_sram_filled_bytes
has 1 failures:
5.spi_device_stress_all.471703885
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/5.spi_device_stress_all/latest/run.log
UVM_ERROR @ 34756303272 ps: (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (0 [0x0] vs 224 [0xe0]) get_sram_filled_bytes
UVM_ERROR @ 34756403272 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (72054618 [0x44b775a] vs 1518501173 [0x5a827d35]) Compare SPI RX data, addr: 0xe0
UVM_ERROR @ 34756553272 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (2977475820 [0xb178acec] vs 3941331128 [0xeaebf0b8]) Compare SPI RX data, addr: 0xe4
UVM_ERROR @ 34756653272 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (2391622369 [0x8e8d42e1] vs 1191734505 [0x47086ce9]) Compare SPI RX data, addr: 0xe8
UVM_ERROR @ 34756753272 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (4008918762 [0xeef33eea] vs 1354499229 [0x50bc049d]) Compare SPI RX data, addr: 0xec
UVM_ERROR (cip_base_vseq.sv:245) [spi_device_mem_parity_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
has 1 failures:
12.spi_device_mem_parity.3309069878
Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/12.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 4782731 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x64 read out mismatch
UVM_ERROR @ 4782731 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x00000064
UVM_ERROR @ 5542731 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x64 read out mismatch
UVM_ERROR @ 5542731 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x00000067
UVM_ERROR @ 6342731 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x64 read out mismatch
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 1 failures:
21.spi_device_fifo_underflow_overflow.941476191
Line 221, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/21.spi_device_fifo_underflow_overflow/latest/run.log
UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (* [*] vs * [*]) get_sram_space_bytes::
has 1 failures:
28.spi_device_stress_all.3610511095
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/28.spi_device_stress_all/latest/run.log
UVM_ERROR @ 33984844699 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (4 [0x4] vs 456 [0x1c8]) get_sram_space_bytes::
UVM_ERROR @ 34118237056 ps: (spi_device_env_pkg.sv:189) [uvm_test_top.env.scoreboard::get_tx_sram_filled_bytes] Check failed wptr >= rptr (208 [0xd0] vs 456 [0x1c8]) get_sram_filled_bytes
UVM_ERROR @ 34118922227 ps: (spi_device_scoreboard.sv:1243) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (3233868238 [0xc0c0e9ce] vs 3691106607 [0xdc01d12f]) Compare SPI TX data
UVM_ERROR @ 34118922227 ps: (spi_device_env_pkg.sv:189) [uvm_test_top.env.scoreboard::get_tx_sram_filled_bytes] Check failed wptr >= rptr (208 [0xd0] vs 464 [0x1d0]) get_sram_filled_bytes
UVM_ERROR @ 34119237082 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (12 [0xc] vs 208 [0xd0]) get_sram_space_bytes::
UVM_ERROR (cip_base_vseq.sv:365) [spi_device_intr_vseq] Check failed act_pins == exp_pins (* [*] vs * [*])
has 1 failures:
33.spi_device_stress_all.509523349
Line 222, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/33.spi_device_stress_all/latest/run.log
UVM_ERROR @ 215396613524 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 215396693524 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.intr_state reset value: 0x0
UVM_ERROR @ 215419213524 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.rxf_empty reset value: 0x1
UVM_ERROR @ 215430173524 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16 [0x10]) Regname: spi_device_reg_block.intr_state reset value: 0x0
UVM_ERROR @ 215430493524 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.rxf_full reset value: 0x0