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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.10 99.01 96.33 98.63 92.06 98.05 95.86 99.76


Total test records in report: 1786
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T802 /workspace/coverage/default/40.spi_device_read_buffer_direct.1523999500 Dec 31 01:11:20 PM PST 23 Dec 31 01:11:31 PM PST 23 7283474034 ps
T803 /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3511374753 Dec 31 01:09:44 PM PST 23 Dec 31 01:10:03 PM PST 23 1298952484 ps
T804 /workspace/coverage/default/33.spi_device_intr.1752465422 Dec 31 01:10:50 PM PST 23 Dec 31 01:11:34 PM PST 23 14563329852 ps
T805 /workspace/coverage/default/9.spi_device_txrx.3746216283 Dec 31 01:08:35 PM PST 23 Dec 31 01:12:55 PM PST 23 56071018455 ps
T806 /workspace/coverage/default/43.spi_device_csb_read.400321902 Dec 31 01:12:08 PM PST 23 Dec 31 01:12:10 PM PST 23 40162955 ps
T807 /workspace/coverage/default/35.spi_device_txrx.1815089965 Dec 31 01:10:50 PM PST 23 Dec 31 01:17:53 PM PST 23 75918739331 ps
T808 /workspace/coverage/default/6.spi_device_tpm_all.2572403265 Dec 31 01:08:24 PM PST 23 Dec 31 01:08:42 PM PST 23 4762316559 ps
T809 /workspace/coverage/default/7.spi_device_rx_async_fifo_reset.487714386 Dec 31 01:08:52 PM PST 23 Dec 31 01:08:57 PM PST 23 20413693 ps
T810 /workspace/coverage/default/9.spi_device_tpm_rw.2380526666 Dec 31 01:08:50 PM PST 23 Dec 31 01:08:54 PM PST 23 165674444 ps
T811 /workspace/coverage/default/14.spi_device_flash_all.1348683180 Dec 31 01:09:10 PM PST 23 Dec 31 01:10:14 PM PST 23 16677216894 ps
T812 /workspace/coverage/default/11.spi_device_txrx.3146705506 Dec 31 01:08:50 PM PST 23 Dec 31 01:12:55 PM PST 23 34514753818 ps
T238 /workspace/coverage/default/47.spi_device_stress_all.1940736003 Dec 31 01:12:19 PM PST 23 Dec 31 01:21:56 PM PST 23 329144868425 ps
T813 /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.775448046 Dec 31 01:12:20 PM PST 23 Dec 31 01:12:33 PM PST 23 7855697777 ps
T229 /workspace/coverage/default/26.spi_device_flash_and_tpm.2687908623 Dec 31 01:10:16 PM PST 23 Dec 31 01:20:03 PM PST 23 279515844458 ps
T814 /workspace/coverage/default/0.spi_device_dummy_item_extra_dly.2053910582 Dec 31 01:07:31 PM PST 23 Dec 31 01:16:24 PM PST 23 82090063982 ps
T815 /workspace/coverage/default/33.spi_device_flash_and_tpm.1430484308 Dec 31 01:10:55 PM PST 23 Dec 31 01:11:40 PM PST 23 1816282637 ps
T816 /workspace/coverage/default/26.spi_device_tpm_rw.1118187598 Dec 31 01:10:14 PM PST 23 Dec 31 01:10:19 PM PST 23 249482248 ps
T817 /workspace/coverage/default/23.spi_device_extreme_fifo_size.3222346974 Dec 31 01:10:31 PM PST 23 Dec 31 01:46:31 PM PST 23 181672882924 ps
T818 /workspace/coverage/default/41.spi_device_dummy_item_extra_dly.506857193 Dec 31 01:11:23 PM PST 23 Dec 31 01:15:31 PM PST 23 144650824371 ps
T819 /workspace/coverage/default/17.spi_device_flash_all.3911471863 Dec 31 01:09:36 PM PST 23 Dec 31 01:10:25 PM PST 23 2995368584 ps
T820 /workspace/coverage/default/24.spi_device_fifo_underflow_overflow.3564896373 Dec 31 01:10:17 PM PST 23 Dec 31 01:16:57 PM PST 23 253795635872 ps
T821 /workspace/coverage/default/41.spi_device_byte_transfer.1895219303 Dec 31 01:11:57 PM PST 23 Dec 31 01:12:02 PM PST 23 297944350 ps
T822 /workspace/coverage/default/45.spi_device_tpm_rw.3966723370 Dec 31 01:12:05 PM PST 23 Dec 31 01:12:07 PM PST 23 98434639 ps
T823 /workspace/coverage/default/25.spi_device_alert_test.1564186933 Dec 31 01:10:35 PM PST 23 Dec 31 01:10:45 PM PST 23 11198445 ps
T824 /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2302428456 Dec 31 01:12:25 PM PST 23 Dec 31 01:12:36 PM PST 23 5045221825 ps
T825 /workspace/coverage/default/21.spi_device_tpm_all.2032450354 Dec 31 01:09:42 PM PST 23 Dec 31 01:10:23 PM PST 23 14671094507 ps
T826 /workspace/coverage/default/8.spi_device_read_buffer_direct.1747981386 Dec 31 01:08:47 PM PST 23 Dec 31 01:08:53 PM PST 23 352755167 ps
T827 /workspace/coverage/default/18.spi_device_flash_all.72972024 Dec 31 01:09:39 PM PST 23 Dec 31 01:11:19 PM PST 23 8100929807 ps
T828 /workspace/coverage/default/40.spi_device_byte_transfer.4046565965 Dec 31 01:11:16 PM PST 23 Dec 31 01:11:23 PM PST 23 382711378 ps
T829 /workspace/coverage/default/12.spi_device_cfg_cmd.2046134720 Dec 31 01:08:55 PM PST 23 Dec 31 01:09:05 PM PST 23 481238943 ps
T830 /workspace/coverage/default/10.spi_device_tpm_rw.2162308696 Dec 31 01:09:02 PM PST 23 Dec 31 01:09:10 PM PST 23 50503378 ps
T831 /workspace/coverage/default/7.spi_device_csb_read.1866664896 Dec 31 01:08:04 PM PST 23 Dec 31 01:08:06 PM PST 23 53621018 ps
T204 /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1554213589 Dec 31 01:11:43 PM PST 23 Dec 31 01:12:01 PM PST 23 17342800207 ps
T832 /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.21613288 Dec 31 01:10:56 PM PST 23 Dec 31 01:11:19 PM PST 23 33816707849 ps
T833 /workspace/coverage/default/40.spi_device_perf.2767590600 Dec 31 01:11:19 PM PST 23 Dec 31 01:19:17 PM PST 23 69622955519 ps
T834 /workspace/coverage/default/18.spi_device_cfg_cmd.2516500380 Dec 31 01:09:36 PM PST 23 Dec 31 01:09:43 PM PST 23 4527281299 ps
T835 /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.4254657298 Dec 31 01:10:57 PM PST 23 Dec 31 01:11:00 PM PST 23 151506700 ps
T836 /workspace/coverage/default/24.spi_device_tx_async_fifo_reset.590837134 Dec 31 01:10:16 PM PST 23 Dec 31 01:10:22 PM PST 23 13547382 ps
T837 /workspace/coverage/default/44.spi_device_tx_async_fifo_reset.613625017 Dec 31 01:11:42 PM PST 23 Dec 31 01:11:44 PM PST 23 39426369 ps
T838 /workspace/coverage/default/36.spi_device_upload.1733550064 Dec 31 01:11:13 PM PST 23 Dec 31 01:11:27 PM PST 23 581163753 ps
T839 /workspace/coverage/default/42.spi_device_tx_async_fifo_reset.2431047455 Dec 31 01:12:07 PM PST 23 Dec 31 01:12:10 PM PST 23 26035163 ps
T840 /workspace/coverage/default/29.spi_device_rx_timeout.3603091922 Dec 31 01:10:20 PM PST 23 Dec 31 01:10:34 PM PST 23 2116654138 ps
T841 /workspace/coverage/default/20.spi_device_perf.3445034528 Dec 31 01:09:34 PM PST 23 Dec 31 01:19:09 PM PST 23 19212805518 ps
T842 /workspace/coverage/default/21.spi_device_stress_all.1214134432 Dec 31 01:10:00 PM PST 23 Dec 31 01:28:13 PM PST 23 355883202963 ps
T843 /workspace/coverage/default/19.spi_device_upload.1348462409 Dec 31 01:09:37 PM PST 23 Dec 31 01:09:50 PM PST 23 7926896904 ps
T844 /workspace/coverage/default/31.spi_device_intr.4134333152 Dec 31 01:10:50 PM PST 23 Dec 31 01:11:45 PM PST 23 195542280753 ps
T845 /workspace/coverage/default/3.spi_device_tpm_rw.2674137382 Dec 31 01:08:51 PM PST 23 Dec 31 01:08:56 PM PST 23 123055077 ps
T846 /workspace/coverage/default/31.spi_device_dummy_item_extra_dly.1561617832 Dec 31 01:10:50 PM PST 23 Dec 31 01:13:33 PM PST 23 13335479028 ps
T847 /workspace/coverage/default/19.spi_device_extreme_fifo_size.111133887 Dec 31 01:09:38 PM PST 23 Dec 31 01:10:34 PM PST 23 32350881314 ps
T848 /workspace/coverage/default/5.spi_device_extreme_fifo_size.1740855504 Dec 31 01:08:46 PM PST 23 Dec 31 01:48:36 PM PST 23 54101519797 ps
T255 /workspace/coverage/default/29.spi_device_extreme_fifo_size.3888332979 Dec 31 01:10:15 PM PST 23 Dec 31 02:10:41 PM PST 23 614252004573 ps
T849 /workspace/coverage/default/37.spi_device_tx_async_fifo_reset.1766195795 Dec 31 01:11:16 PM PST 23 Dec 31 01:11:19 PM PST 23 16428133 ps
T850 /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3089256588 Dec 31 01:10:54 PM PST 23 Dec 31 01:11:03 PM PST 23 2804055829 ps
T851 /workspace/coverage/default/41.spi_device_perf.975949085 Dec 31 01:11:20 PM PST 23 Dec 31 01:39:20 PM PST 23 96389530769 ps
T852 /workspace/coverage/default/28.spi_device_flash_mode.4273657920 Dec 31 01:10:15 PM PST 23 Dec 31 01:10:42 PM PST 23 4613941439 ps
T853 /workspace/coverage/default/12.spi_device_read_buffer_direct.1344902373 Dec 31 01:08:56 PM PST 23 Dec 31 01:09:08 PM PST 23 612503931 ps
T854 /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1902627296 Dec 31 01:10:53 PM PST 23 Dec 31 01:11:09 PM PST 23 6136977815 ps
T855 /workspace/coverage/default/2.spi_device_fifo_underflow_overflow.885369452 Dec 31 01:07:48 PM PST 23 Dec 31 01:13:35 PM PST 23 43151237319 ps
T856 /workspace/coverage/default/18.spi_device_byte_transfer.227760985 Dec 31 01:09:42 PM PST 23 Dec 31 01:09:54 PM PST 23 2591642639 ps
T857 /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2508096973 Dec 31 01:11:20 PM PST 23 Dec 31 01:11:38 PM PST 23 3173515544 ps
T239 /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3717709475 Dec 31 01:09:01 PM PST 23 Dec 31 01:12:00 PM PST 23 11175352839 ps
T858 /workspace/coverage/default/30.spi_device_csb_read.3864028967 Dec 31 01:10:34 PM PST 23 Dec 31 01:10:45 PM PST 23 16356908 ps
T859 /workspace/coverage/default/30.spi_device_flash_all.895357558 Dec 31 01:10:51 PM PST 23 Dec 31 01:12:46 PM PST 23 21953061107 ps
T860 /workspace/coverage/default/4.spi_device_bit_transfer.1847254827 Dec 31 01:08:14 PM PST 23 Dec 31 01:08:17 PM PST 23 95447087 ps
T861 /workspace/coverage/default/0.spi_device_intr.1954541859 Dec 31 01:07:31 PM PST 23 Dec 31 01:09:27 PM PST 23 125549859630 ps
T862 /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1556010216 Dec 31 01:08:03 PM PST 23 Dec 31 01:08:41 PM PST 23 2123901225 ps
T863 /workspace/coverage/default/13.spi_device_extreme_fifo_size.2010385562 Dec 31 01:09:13 PM PST 23 Dec 31 01:10:25 PM PST 23 74623943736 ps
T864 /workspace/coverage/default/1.spi_device_alert_test.307891676 Dec 31 01:08:31 PM PST 23 Dec 31 01:08:32 PM PST 23 24425966 ps
T865 /workspace/coverage/default/25.spi_device_rx_timeout.4042305075 Dec 31 01:10:00 PM PST 23 Dec 31 01:10:08 PM PST 23 2413538867 ps
T866 /workspace/coverage/default/18.spi_device_fifo_full.3367864182 Dec 31 01:09:36 PM PST 23 Dec 31 01:41:55 PM PST 23 32176335266 ps
T205 /workspace/coverage/default/12.spi_device_flash_and_tpm.1057598757 Dec 31 01:08:57 PM PST 23 Dec 31 01:14:50 PM PST 23 38463875592 ps
T867 /workspace/coverage/default/25.spi_device_fifo_full.4014907737 Dec 31 01:10:02 PM PST 23 Dec 31 01:17:00 PM PST 23 26904314163 ps
T868 /workspace/coverage/default/31.spi_device_alert_test.1844115366 Dec 31 01:11:12 PM PST 23 Dec 31 01:11:13 PM PST 23 63302828 ps
T869 /workspace/coverage/default/8.spi_device_tpm_rw.4043978365 Dec 31 01:08:34 PM PST 23 Dec 31 01:08:37 PM PST 23 39427416 ps
T870 /workspace/coverage/default/18.spi_device_tx_async_fifo_reset.1683381999 Dec 31 01:09:39 PM PST 23 Dec 31 01:09:46 PM PST 23 28004829 ps
T871 /workspace/coverage/default/0.spi_device_tpm_rw.3244950062 Dec 31 01:07:31 PM PST 23 Dec 31 01:07:34 PM PST 23 36220985 ps
T872 /workspace/coverage/default/36.spi_device_cfg_cmd.376044659 Dec 31 01:10:57 PM PST 23 Dec 31 01:11:04 PM PST 23 868604889 ps
T873 /workspace/coverage/default/4.spi_device_read_buffer_direct.551181503 Dec 31 01:08:03 PM PST 23 Dec 31 01:08:09 PM PST 23 6115570644 ps
T874 /workspace/coverage/default/13.spi_device_tpm_rw.258359919 Dec 31 01:08:51 PM PST 23 Dec 31 01:08:55 PM PST 23 33601518 ps
T875 /workspace/coverage/default/30.spi_device_rx_timeout.992330264 Dec 31 01:10:32 PM PST 23 Dec 31 01:10:45 PM PST 23 1392127827 ps
T225 /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1721280745 Dec 31 01:11:22 PM PST 23 Dec 31 01:12:39 PM PST 23 6511438087 ps
T876 /workspace/coverage/default/5.spi_device_abort.957060465 Dec 31 01:08:05 PM PST 23 Dec 31 01:08:08 PM PST 23 42959113 ps
T877 /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1060439383 Dec 31 01:09:38 PM PST 23 Dec 31 01:09:53 PM PST 23 2747383308 ps
T878 /workspace/coverage/default/42.spi_device_flash_mode.1335720135 Dec 31 01:11:42 PM PST 23 Dec 31 01:12:11 PM PST 23 15889370461 ps
T879 /workspace/coverage/default/26.spi_device_bit_transfer.129907274 Dec 31 01:10:53 PM PST 23 Dec 31 01:10:57 PM PST 23 90032368 ps
T880 /workspace/coverage/default/28.spi_device_dummy_item_extra_dly.2849067099 Dec 31 01:10:16 PM PST 23 Dec 31 01:14:35 PM PST 23 68524967938 ps
T881 /workspace/coverage/default/30.spi_device_abort.1814340400 Dec 31 01:10:51 PM PST 23 Dec 31 01:10:53 PM PST 23 14359138 ps
T882 /workspace/coverage/default/20.spi_device_tx_async_fifo_reset.3869711087 Dec 31 01:09:36 PM PST 23 Dec 31 01:09:39 PM PST 23 58335249 ps
T883 /workspace/coverage/default/1.spi_device_tpm_sts_read.1173471121 Dec 31 01:08:23 PM PST 23 Dec 31 01:08:25 PM PST 23 42476617 ps
T884 /workspace/coverage/default/5.spi_device_flash_mode.303828570 Dec 31 01:08:27 PM PST 23 Dec 31 01:08:41 PM PST 23 1835783484 ps
T885 /workspace/coverage/default/49.spi_device_flash_and_tpm.2193927369 Dec 31 01:12:24 PM PST 23 Dec 31 01:13:17 PM PST 23 2363666310 ps
T886 /workspace/coverage/default/49.spi_device_rx_timeout.543318152 Dec 31 01:12:18 PM PST 23 Dec 31 01:12:28 PM PST 23 465176018 ps
T887 /workspace/coverage/default/11.spi_device_intercept.177876221 Dec 31 01:08:52 PM PST 23 Dec 31 01:09:00 PM PST 23 304665876 ps
T888 /workspace/coverage/default/32.spi_device_tpm_rw.1503061549 Dec 31 01:10:55 PM PST 23 Dec 31 01:10:59 PM PST 23 111618463 ps
T889 /workspace/coverage/default/3.spi_device_tpm_sts_read.1677192439 Dec 31 01:08:37 PM PST 23 Dec 31 01:08:42 PM PST 23 286071781 ps
T890 /workspace/coverage/default/48.spi_device_tpm_rw.3064889644 Dec 31 01:12:21 PM PST 23 Dec 31 01:12:29 PM PST 23 14971493 ps
T233 /workspace/coverage/default/38.spi_device_intercept.2380519243 Dec 31 01:11:18 PM PST 23 Dec 31 01:11:28 PM PST 23 161533728 ps
T891 /workspace/coverage/default/26.spi_device_tpm_all.4026582971 Dec 31 01:10:51 PM PST 23 Dec 31 01:10:57 PM PST 23 731538435 ps
T892 /workspace/coverage/default/7.spi_device_dummy_item_extra_dly.1437642117 Dec 31 01:08:06 PM PST 23 Dec 31 01:18:12 PM PST 23 75898940604 ps
T893 /workspace/coverage/default/34.spi_device_abort.3970743738 Dec 31 01:10:53 PM PST 23 Dec 31 01:10:57 PM PST 23 15695427 ps
T298 /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1328297136 Dec 31 01:12:20 PM PST 23 Dec 31 01:12:34 PM PST 23 6215523397 ps
T894 /workspace/coverage/default/36.spi_device_bit_transfer.40481257 Dec 31 01:11:15 PM PST 23 Dec 31 01:11:18 PM PST 23 178052162 ps
T895 /workspace/coverage/default/27.spi_device_fifo_full.4091956313 Dec 31 01:10:18 PM PST 23 Dec 31 01:45:57 PM PST 23 43628947748 ps
T896 /workspace/coverage/default/24.spi_device_intercept.4028776344 Dec 31 01:10:14 PM PST 23 Dec 31 01:10:20 PM PST 23 593421801 ps
T897 /workspace/coverage/default/34.spi_device_perf.3891968025 Dec 31 01:11:15 PM PST 23 Dec 31 01:29:18 PM PST 23 16696162344 ps
T898 /workspace/coverage/default/36.spi_device_txrx.2473477013 Dec 31 01:11:56 PM PST 23 Dec 31 01:17:30 PM PST 23 45803079801 ps
T899 /workspace/coverage/default/13.spi_device_tpm_sts_read.2225904538 Dec 31 01:08:55 PM PST 23 Dec 31 01:09:02 PM PST 23 39902725 ps
T308 /workspace/coverage/default/7.spi_device_flash_and_tpm.3048306848 Dec 31 01:08:24 PM PST 23 Dec 31 01:09:08 PM PST 23 9662791158 ps
T900 /workspace/coverage/default/24.spi_device_abort.3356958421 Dec 31 01:10:03 PM PST 23 Dec 31 01:10:07 PM PST 23 22985684 ps
T901 /workspace/coverage/default/3.spi_device_extreme_fifo_size.138805470 Dec 31 01:08:07 PM PST 23 Dec 31 01:09:27 PM PST 23 16236803676 ps
T902 /workspace/coverage/default/4.spi_device_tpm_sts_read.3883961155 Dec 31 01:07:59 PM PST 23 Dec 31 01:08:01 PM PST 23 57334002 ps
T903 /workspace/coverage/default/16.spi_device_intr.3288493395 Dec 31 01:09:17 PM PST 23 Dec 31 01:09:35 PM PST 23 6614336170 ps
T904 /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1845962263 Dec 31 01:10:01 PM PST 23 Dec 31 01:10:24 PM PST 23 6423951307 ps
T905 /workspace/coverage/default/6.spi_device_rx_timeout.3713829990 Dec 31 01:08:04 PM PST 23 Dec 31 01:08:10 PM PST 23 2215687347 ps
T906 /workspace/coverage/default/47.spi_device_mailbox.2713604800 Dec 31 01:12:18 PM PST 23 Dec 31 01:13:23 PM PST 23 36175395172 ps
T907 /workspace/coverage/default/43.spi_device_abort.3578985266 Dec 31 01:11:56 PM PST 23 Dec 31 01:11:58 PM PST 23 15905746 ps
T908 /workspace/coverage/default/45.spi_device_tpm_sts_read.339632356 Dec 31 01:12:14 PM PST 23 Dec 31 01:12:18 PM PST 23 183602698 ps
T909 /workspace/coverage/default/39.spi_device_csb_read.3078690097 Dec 31 01:11:18 PM PST 23 Dec 31 01:11:23 PM PST 23 22222938 ps
T910 /workspace/coverage/default/5.spi_device_tpm_all.2806399502 Dec 31 01:08:06 PM PST 23 Dec 31 01:08:33 PM PST 23 2143861874 ps
T911 /workspace/coverage/default/49.spi_device_abort.438394542 Dec 31 01:12:20 PM PST 23 Dec 31 01:12:27 PM PST 23 14013099 ps
T912 /workspace/coverage/default/3.spi_device_bit_transfer.1084505648 Dec 31 01:08:27 PM PST 23 Dec 31 01:08:31 PM PST 23 1300728826 ps
T913 /workspace/coverage/default/8.spi_device_extreme_fifo_size.901030036 Dec 31 01:08:46 PM PST 23 Dec 31 01:51:54 PM PST 23 99834428046 ps
T914 /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3689906446 Dec 31 01:07:32 PM PST 23 Dec 31 01:07:36 PM PST 23 61407109 ps
T915 /workspace/coverage/default/35.spi_device_extreme_fifo_size.3345912305 Dec 31 01:10:55 PM PST 23 Dec 31 01:23:58 PM PST 23 219683340071 ps
T916 /workspace/coverage/default/42.spi_device_smoke.447830995 Dec 31 01:11:38 PM PST 23 Dec 31 01:11:40 PM PST 23 20841620 ps
T917 /workspace/coverage/default/45.spi_device_rx_async_fifo_reset.4213361870 Dec 31 01:12:19 PM PST 23 Dec 31 01:12:24 PM PST 23 27266756 ps
T918 /workspace/coverage/default/11.spi_device_tpm_sts_read.2610842708 Dec 31 01:08:50 PM PST 23 Dec 31 01:08:54 PM PST 23 388611775 ps
T919 /workspace/coverage/default/12.spi_device_flash_all.3937580095 Dec 31 01:08:54 PM PST 23 Dec 31 01:09:20 PM PST 23 1339288818 ps
T920 /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.787818801 Dec 31 01:11:24 PM PST 23 Dec 31 01:11:39 PM PST 23 5539760826 ps
T921 /workspace/coverage/default/27.spi_device_tpm_all.585273414 Dec 31 01:10:30 PM PST 23 Dec 31 01:11:19 PM PST 23 5937971896 ps
T922 /workspace/coverage/default/15.spi_device_mem_parity.4056401415 Dec 31 01:09:11 PM PST 23 Dec 31 01:09:14 PM PST 23 56937039 ps
T923 /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2067872123 Dec 31 01:08:36 PM PST 23 Dec 31 01:10:17 PM PST 23 7642878531 ps
T924 /workspace/coverage/default/31.spi_device_perf.3958814174 Dec 31 01:10:34 PM PST 23 Dec 31 01:26:51 PM PST 23 125385573698 ps
T925 /workspace/coverage/default/28.spi_device_flash_all.723841333 Dec 31 01:10:18 PM PST 23 Dec 31 01:11:08 PM PST 23 3856111362 ps
T926 /workspace/coverage/default/22.spi_device_bit_transfer.3871191513 Dec 31 01:10:00 PM PST 23 Dec 31 01:10:05 PM PST 23 201524739 ps
T927 /workspace/coverage/default/38.spi_device_abort.4040039419 Dec 31 01:11:16 PM PST 23 Dec 31 01:11:19 PM PST 23 14537943 ps
T928 /workspace/coverage/default/35.spi_device_rx_timeout.3372062034 Dec 31 01:11:15 PM PST 23 Dec 31 01:11:24 PM PST 23 1784133873 ps
T206 /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3344823694 Dec 31 01:08:58 PM PST 23 Dec 31 01:10:41 PM PST 23 9282731959 ps
T929 /workspace/coverage/default/26.spi_device_tx_async_fifo_reset.719738734 Dec 31 01:10:16 PM PST 23 Dec 31 01:10:20 PM PST 23 17714277 ps
T930 /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2534634759 Dec 31 01:10:13 PM PST 23 Dec 31 01:10:22 PM PST 23 2570729790 ps
T931 /workspace/coverage/default/19.spi_device_byte_transfer.553784924 Dec 31 01:09:44 PM PST 23 Dec 31 01:09:57 PM PST 23 2565035580 ps
T932 /workspace/coverage/default/35.spi_device_alert_test.1752635961 Dec 31 01:11:23 PM PST 23 Dec 31 01:11:28 PM PST 23 38916142 ps
T933 /workspace/coverage/default/49.spi_device_bit_transfer.2237293048 Dec 31 01:12:15 PM PST 23 Dec 31 01:12:21 PM PST 23 446120490 ps
T934 /workspace/coverage/default/0.spi_device_flash_mode.3017812111 Dec 31 01:07:33 PM PST 23 Dec 31 01:07:57 PM PST 23 447714879 ps
T935 /workspace/coverage/default/13.spi_device_intercept.113209062 Dec 31 01:08:53 PM PST 23 Dec 31 01:09:01 PM PST 23 1303660453 ps
T936 /workspace/coverage/default/0.spi_device_perf.3309796698 Dec 31 01:07:32 PM PST 23 Dec 31 01:13:41 PM PST 23 6133231536 ps
T937 /workspace/coverage/default/4.spi_device_fifo_underflow_overflow.2342592945 Dec 31 01:08:52 PM PST 23 Dec 31 01:14:06 PM PST 23 54560051581 ps
T938 /workspace/coverage/default/27.spi_device_rx_timeout.1186578059 Dec 31 01:10:34 PM PST 23 Dec 31 01:10:50 PM PST 23 903826155 ps
T939 /workspace/coverage/default/35.spi_device_read_buffer_direct.4285565162 Dec 31 01:11:38 PM PST 23 Dec 31 01:11:45 PM PST 23 4874593606 ps
T940 /workspace/coverage/default/30.spi_device_tx_async_fifo_reset.3534299406 Dec 31 01:10:36 PM PST 23 Dec 31 01:10:45 PM PST 23 34431566 ps
T941 /workspace/coverage/default/45.spi_device_flash_and_tpm.3329568676 Dec 31 01:12:05 PM PST 23 Dec 31 01:12:26 PM PST 23 2350974889 ps
T942 /workspace/coverage/default/8.spi_device_txrx.3286664304 Dec 31 01:08:50 PM PST 23 Dec 31 01:12:24 PM PST 23 30689614383 ps
T943 /workspace/coverage/default/18.spi_device_csb_read.914511147 Dec 31 01:09:37 PM PST 23 Dec 31 01:09:41 PM PST 23 20157143 ps
T944 /workspace/coverage/default/8.spi_device_pass_cmd_filtering.228351235 Dec 31 01:08:48 PM PST 23 Dec 31 01:08:59 PM PST 23 43363188263 ps
T945 /workspace/coverage/default/25.spi_device_tx_async_fifo_reset.1121061116 Dec 31 01:10:20 PM PST 23 Dec 31 01:10:30 PM PST 23 13040358 ps
T946 /workspace/coverage/default/42.spi_device_extreme_fifo_size.1428402595 Dec 31 01:11:41 PM PST 23 Dec 31 01:33:49 PM PST 23 76981055547 ps
T947 /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1615215771 Dec 31 01:11:57 PM PST 23 Dec 31 01:12:01 PM PST 23 399467919 ps
T948 /workspace/coverage/default/46.spi_device_bit_transfer.3559061798 Dec 31 01:12:20 PM PST 23 Dec 31 01:12:27 PM PST 23 190413166 ps
T949 /workspace/coverage/default/42.spi_device_csb_read.1887768451 Dec 31 01:11:41 PM PST 23 Dec 31 01:11:43 PM PST 23 24920589 ps
T950 /workspace/coverage/default/36.spi_device_rx_timeout.2434711612 Dec 31 01:12:06 PM PST 23 Dec 31 01:12:15 PM PST 23 3270719231 ps
T951 /workspace/coverage/default/37.spi_device_extreme_fifo_size.2892705775 Dec 31 01:11:17 PM PST 23 Dec 31 01:20:02 PM PST 23 77813156090 ps
T952 /workspace/coverage/default/21.spi_device_rx_async_fifo_reset.729070041 Dec 31 01:09:42 PM PST 23 Dec 31 01:09:53 PM PST 23 142433073 ps
T953 /workspace/coverage/default/49.spi_device_tpm_sts_read.1101744104 Dec 31 01:12:19 PM PST 23 Dec 31 01:12:25 PM PST 23 74731732 ps
T954 /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3787533749 Dec 31 01:08:52 PM PST 23 Dec 31 01:09:17 PM PST 23 12813732440 ps
T955 /workspace/coverage/default/8.spi_device_alert_test.1932255443 Dec 31 01:08:34 PM PST 23 Dec 31 01:08:36 PM PST 23 12561716 ps
T956 /workspace/coverage/default/19.spi_device_stress_all.1183664636 Dec 31 01:09:35 PM PST 23 Dec 31 01:21:05 PM PST 23 63885347206 ps
T957 /workspace/coverage/default/14.spi_device_fifo_underflow_overflow.1164707988 Dec 31 01:09:13 PM PST 23 Dec 31 01:17:09 PM PST 23 258326566559 ps
T958 /workspace/coverage/default/26.spi_device_mailbox.2339163984 Dec 31 01:10:18 PM PST 23 Dec 31 01:10:34 PM PST 23 2540674034 ps
T959 /workspace/coverage/default/17.spi_device_alert_test.4212497872 Dec 31 01:09:41 PM PST 23 Dec 31 01:09:51 PM PST 23 57516848 ps
T960 /workspace/coverage/default/43.spi_device_read_buffer_direct.215922691 Dec 31 01:12:15 PM PST 23 Dec 31 01:12:25 PM PST 23 1194357446 ps
T312 /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.67129726 Dec 31 01:10:16 PM PST 23 Dec 31 01:10:43 PM PST 23 5614071503 ps
T961 /workspace/coverage/default/48.spi_device_txrx.4263541402 Dec 31 01:12:14 PM PST 23 Dec 31 01:15:48 PM PST 23 54451819188 ps
T962 /workspace/coverage/default/7.spi_device_mem_parity.167859194 Dec 31 01:08:48 PM PST 23 Dec 31 01:08:51 PM PST 23 42313653 ps
T963 /workspace/coverage/default/39.spi_device_intr.4180360426 Dec 31 01:11:17 PM PST 23 Dec 31 01:11:58 PM PST 23 32253201329 ps
T964 /workspace/coverage/default/47.spi_device_abort.1909039337 Dec 31 01:12:19 PM PST 23 Dec 31 01:12:25 PM PST 23 26239927 ps
T965 /workspace/coverage/default/26.spi_device_abort.897149355 Dec 31 01:10:17 PM PST 23 Dec 31 01:10:24 PM PST 23 32368367 ps
T966 /workspace/coverage/default/5.spi_device_rx_timeout.3606951379 Dec 31 01:07:59 PM PST 23 Dec 31 01:08:05 PM PST 23 2062080802 ps
T967 /workspace/coverage/default/13.spi_device_read_buffer_direct.1440843751 Dec 31 01:08:52 PM PST 23 Dec 31 01:09:00 PM PST 23 384968718 ps
T968 /workspace/coverage/default/11.spi_device_fifo_underflow_overflow.1801375250 Dec 31 01:08:55 PM PST 23 Dec 31 01:11:03 PM PST 23 19263032355 ps
T969 /workspace/coverage/default/15.spi_device_bit_transfer.3735567647 Dec 31 01:09:11 PM PST 23 Dec 31 01:09:14 PM PST 23 1960981939 ps
T970 /workspace/coverage/default/14.spi_device_bit_transfer.3568860105 Dec 31 01:08:55 PM PST 23 Dec 31 01:09:03 PM PST 23 123052137 ps
T971 /workspace/coverage/default/47.spi_device_rx_timeout.4010502787 Dec 31 01:12:07 PM PST 23 Dec 31 01:12:14 PM PST 23 3305302222 ps
T972 /workspace/coverage/default/43.spi_device_smoke.480099092 Dec 31 01:12:15 PM PST 23 Dec 31 01:12:20 PM PST 23 79768074 ps
T973 /workspace/coverage/default/6.spi_device_mem_parity.2558391000 Dec 31 01:08:03 PM PST 23 Dec 31 01:08:06 PM PST 23 34521848 ps
T974 /workspace/coverage/default/44.spi_device_extreme_fifo_size.331001583 Dec 31 01:12:21 PM PST 23 Dec 31 01:36:35 PM PST 23 523484383226 ps
T975 /workspace/coverage/default/16.spi_device_tpm_sts_read.4290780390 Dec 31 01:09:29 PM PST 23 Dec 31 01:09:34 PM PST 23 27264875 ps
T976 /workspace/coverage/default/47.spi_device_extreme_fifo_size.1612324132 Dec 31 01:12:14 PM PST 23 Dec 31 01:13:21 PM PST 23 37745932224 ps
T977 /workspace/coverage/default/27.spi_device_perf.3816617075 Dec 31 01:10:30 PM PST 23 Dec 31 01:19:17 PM PST 23 8327404001 ps
T978 /workspace/coverage/default/12.spi_device_intercept.844957073 Dec 31 01:08:58 PM PST 23 Dec 31 01:09:18 PM PST 23 2868416159 ps
T979 /workspace/coverage/default/10.spi_device_smoke.307524150 Dec 31 01:08:52 PM PST 23 Dec 31 01:08:57 PM PST 23 99669086 ps
T220 /workspace/coverage/default/6.spi_device_intercept.2630723855 Dec 31 01:08:37 PM PST 23 Dec 31 01:08:47 PM PST 23 4140334502 ps
T980 /workspace/coverage/default/16.spi_device_intercept.1554358012 Dec 31 01:09:13 PM PST 23 Dec 31 01:09:20 PM PST 23 185103788 ps
T981 /workspace/coverage/default/38.spi_device_txrx.376013237 Dec 31 01:11:19 PM PST 23 Dec 31 01:14:33 PM PST 23 87985388161 ps
T982 /workspace/coverage/default/6.spi_device_tpm_rw.2424289405 Dec 31 01:08:10 PM PST 23 Dec 31 01:08:13 PM PST 23 73516812 ps
T983 /workspace/coverage/default/12.spi_device_perf.1531072775 Dec 31 01:08:51 PM PST 23 Dec 31 01:12:49 PM PST 23 37346813976 ps
T984 /workspace/coverage/default/10.spi_device_fifo_underflow_overflow.45654408 Dec 31 01:08:53 PM PST 23 Dec 31 01:11:52 PM PST 23 114059333763 ps
T985 /workspace/coverage/default/29.spi_device_flash_mode.1015026612 Dec 31 01:10:15 PM PST 23 Dec 31 01:10:25 PM PST 23 887162054 ps
T301 /workspace/coverage/default/34.spi_device_stress_all.1867163817 Dec 31 01:11:13 PM PST 23 Dec 31 01:37:12 PM PST 23 172147399471 ps
T986 /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1964491811 Dec 31 01:12:14 PM PST 23 Dec 31 01:12:25 PM PST 23 1371093959 ps
T77 /workspace/coverage/default/4.spi_device_sec_cm.1426858494 Dec 31 01:08:03 PM PST 23 Dec 31 01:08:06 PM PST 23 222239095 ps
T987 /workspace/coverage/default/43.spi_device_flash_mode.923178598 Dec 31 01:11:45 PM PST 23 Dec 31 01:12:11 PM PST 23 29255870786 ps
T988 /workspace/coverage/default/34.spi_device_fifo_underflow_overflow.2147594753 Dec 31 01:10:57 PM PST 23 Dec 31 01:16:20 PM PST 23 225604509585 ps
T989 /workspace/coverage/default/0.spi_device_rx_timeout.2942054346 Dec 31 01:07:31 PM PST 23 Dec 31 01:07:39 PM PST 23 2866878335 ps
T234 /workspace/coverage/default/6.spi_device_upload.4235685962 Dec 31 01:08:53 PM PST 23 Dec 31 01:09:10 PM PST 23 3563084415 ps
T990 /workspace/coverage/default/44.spi_device_tpm_all.619633653 Dec 31 01:11:44 PM PST 23 Dec 31 01:12:25 PM PST 23 3011849476 ps
T991 /workspace/coverage/default/0.spi_device_byte_transfer.3747027214 Dec 31 01:07:30 PM PST 23 Dec 31 01:07:34 PM PST 23 737331113 ps
T183 /workspace/coverage/default/46.spi_device_stress_all.1841341629 Dec 31 01:12:18 PM PST 23 Dec 31 02:58:22 PM PST 23 271117449096 ps
T992 /workspace/coverage/default/14.spi_device_perf.1939108835 Dec 31 01:09:18 PM PST 23 Dec 31 01:23:17 PM PST 23 353685174263 ps
T993 /workspace/coverage/default/7.spi_device_tpm_all.489598161 Dec 31 01:08:34 PM PST 23 Dec 31 01:09:00 PM PST 23 10878450479 ps
T994 /workspace/coverage/default/42.spi_device_flash_and_tpm.1512631344 Dec 31 01:11:40 PM PST 23 Dec 31 01:13:21 PM PST 23 6788859975 ps
T995 /workspace/coverage/default/10.spi_device_tpm_sts_read.934713538 Dec 31 01:09:01 PM PST 23 Dec 31 01:09:10 PM PST 23 102245941 ps
T996 /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1813322950 Dec 31 01:08:28 PM PST 23 Dec 31 01:08:46 PM PST 23 18377415602 ps
T997 /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2687240960 Dec 31 01:11:57 PM PST 23 Dec 31 01:12:07 PM PST 23 2737349199 ps
T998 /workspace/coverage/default/18.spi_device_perf.1923800991 Dec 31 01:09:39 PM PST 23 Dec 31 01:24:03 PM PST 23 23828099725 ps
T999 /workspace/coverage/default/8.spi_device_tx_async_fifo_reset.1014126094 Dec 31 01:08:34 PM PST 23 Dec 31 01:08:35 PM PST 23 44869298 ps
T1000 /workspace/coverage/default/48.spi_device_cfg_cmd.623059653 Dec 31 01:12:20 PM PST 23 Dec 31 01:12:29 PM PST 23 185523772 ps
T314 /workspace/coverage/default/43.spi_device_flash_all.191931531 Dec 31 01:12:15 PM PST 23 Dec 31 01:17:20 PM PST 23 234300205213 ps
T1001 /workspace/coverage/default/35.spi_device_flash_and_tpm.2393114765 Dec 31 01:11:23 PM PST 23 Dec 31 01:11:58 PM PST 23 1865461914 ps
T1002 /workspace/coverage/default/3.spi_device_read_buffer_direct.729198543 Dec 31 01:08:56 PM PST 23 Dec 31 01:09:10 PM PST 23 9168830693 ps
T1003 /workspace/coverage/default/12.spi_device_fifo_underflow_overflow.2814709679 Dec 31 01:08:56 PM PST 23 Dec 31 01:11:21 PM PST 23 109811973910 ps
T1004 /workspace/coverage/default/15.spi_device_mailbox.4193659378 Dec 31 01:09:17 PM PST 23 Dec 31 01:10:01 PM PST 23 25833340516 ps
T296 /workspace/coverage/default/48.spi_device_flash_all.108743007 Dec 31 01:12:14 PM PST 23 Dec 31 01:17:08 PM PST 23 64285555530 ps
T1005 /workspace/coverage/default/9.spi_device_bit_transfer.51262782 Dec 31 01:08:49 PM PST 23 Dec 31 01:08:54 PM PST 23 68691376 ps
T1006 /workspace/coverage/default/26.spi_device_extreme_fifo_size.1583574375 Dec 31 01:10:33 PM PST 23 Dec 31 01:57:21 PM PST 23 54596191204 ps
T1007 /workspace/coverage/default/8.spi_device_flash_all.687380793 Dec 31 01:08:48 PM PST 23 Dec 31 01:09:37 PM PST 23 36682941419 ps
T1008 /workspace/coverage/default/20.spi_device_smoke.1696427868 Dec 31 01:09:37 PM PST 23 Dec 31 01:09:41 PM PST 23 17940483 ps
T1009 /workspace/coverage/default/25.spi_device_upload.1257558555 Dec 31 01:10:17 PM PST 23 Dec 31 01:10:40 PM PST 23 1623116254 ps
T1010 /workspace/coverage/default/22.spi_device_csb_read.3784366059 Dec 31 01:10:02 PM PST 23 Dec 31 01:10:06 PM PST 23 15000819 ps
T1011 /workspace/coverage/default/41.spi_device_abort.2605194098 Dec 31 01:11:43 PM PST 23 Dec 31 01:11:45 PM PST 23 49865200 ps
T1012 /workspace/coverage/default/39.spi_device_tpm_sts_read.211665832 Dec 31 01:11:20 PM PST 23 Dec 31 01:11:25 PM PST 23 72517588 ps
T1013 /workspace/coverage/default/49.spi_device_tpm_rw.2840372646 Dec 31 01:12:17 PM PST 23 Dec 31 01:12:23 PM PST 23 18274443 ps
T1014 /workspace/coverage/default/17.spi_device_fifo_underflow_overflow.3177877412 Dec 31 01:09:21 PM PST 23 Dec 31 01:11:47 PM PST 23 16792260538 ps
T1015 /workspace/coverage/default/7.spi_device_ram_cfg.703553141 Dec 31 01:08:34 PM PST 23 Dec 31 01:08:36 PM PST 23 17676721 ps
T1016 /workspace/coverage/default/38.spi_device_rx_timeout.200614023 Dec 31 01:11:15 PM PST 23 Dec 31 01:11:21 PM PST 23 1231686073 ps
T1017 /workspace/coverage/default/0.spi_device_fifo_full.1961143507 Dec 31 01:07:29 PM PST 23 Dec 31 01:37:46 PM PST 23 130231139962 ps
T1018 /workspace/coverage/default/23.spi_device_cfg_cmd.1034324004 Dec 31 01:10:16 PM PST 23 Dec 31 01:10:24 PM PST 23 1274500310 ps
T1019 /workspace/coverage/default/43.spi_device_upload.1114648743 Dec 31 01:11:54 PM PST 23 Dec 31 01:12:05 PM PST 23 2313749951 ps
T1020 /workspace/coverage/default/8.spi_device_intr.1211084773 Dec 31 01:08:50 PM PST 23 Dec 31 01:09:32 PM PST 23 10135896052 ps
T1021 /workspace/coverage/default/11.spi_device_fifo_full.358867869 Dec 31 01:08:53 PM PST 23 Dec 31 01:22:10 PM PST 23 104212793575 ps
T1022 /workspace/coverage/default/24.spi_device_stress_all.938281915 Dec 31 01:10:13 PM PST 23 Dec 31 01:38:52 PM PST 23 167444946000 ps
T1023 /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4035034798 Dec 31 01:08:24 PM PST 23 Dec 31 01:08:34 PM PST 23 2186099239 ps
T1024 /workspace/coverage/default/26.spi_device_smoke.2169587860 Dec 31 01:10:17 PM PST 23 Dec 31 01:10:26 PM PST 23 26967038 ps
T1025 /workspace/coverage/default/15.spi_device_tx_async_fifo_reset.4069529977 Dec 31 01:09:16 PM PST 23 Dec 31 01:09:19 PM PST 23 18378589 ps
T184 /workspace/coverage/default/31.spi_device_fifo_underflow_overflow.4171148774 Dec 31 01:10:52 PM PST 23 Dec 31 01:20:50 PM PST 23 264073626175 ps
T1026 /workspace/coverage/default/15.spi_device_dummy_item_extra_dly.2745864145 Dec 31 01:08:58 PM PST 23 Dec 31 01:14:15 PM PST 23 102366190470 ps
T1027 /workspace/coverage/default/13.spi_device_flash_mode.1841908109 Dec 31 01:08:57 PM PST 23 Dec 31 01:09:41 PM PST 23 12457871198 ps
T1028 /workspace/coverage/default/1.spi_device_ram_cfg.2014783635 Dec 31 01:07:48 PM PST 23 Dec 31 01:07:50 PM PST 23 65734699 ps
T1029 /workspace/coverage/default/41.spi_device_intercept.1639256696 Dec 31 01:11:43 PM PST 23 Dec 31 01:11:53 PM PST 23 1900125721 ps
T1030 /workspace/coverage/default/15.spi_device_fifo_full.2704125955 Dec 31 01:09:12 PM PST 23 Dec 31 01:21:13 PM PST 23 138073170602 ps
T1031 /workspace/coverage/default/30.spi_device_tpm_all.2750374129 Dec 31 01:10:21 PM PST 23 Dec 31 01:10:43 PM PST 23 739756672 ps
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