Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.10 99.01 96.33 98.63 92.06 98.05 95.86 99.76


Total test records in report: 1786
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T1753 /workspace/coverage/default/33.spi_device_txrx.2174273224 Dec 31 01:10:51 PM PST 23 Dec 31 01:12:59 PM PST 23 85383281205 ps
T1754 /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3897615215 Dec 31 01:11:19 PM PST 23 Dec 31 01:11:36 PM PST 23 8100476022 ps
T1755 /workspace/coverage/default/27.spi_device_abort.947044031 Dec 31 01:10:19 PM PST 23 Dec 31 01:10:29 PM PST 23 49485543 ps
T1756 /workspace/coverage/default/33.spi_device_dummy_item_extra_dly.2562038663 Dec 31 01:10:50 PM PST 23 Dec 31 01:16:52 PM PST 23 144606038727 ps
T309 /workspace/coverage/default/45.spi_device_flash_all.1369173437 Dec 31 01:12:15 PM PST 23 Dec 31 01:15:37 PM PST 23 162833291960 ps
T1757 /workspace/coverage/default/34.spi_device_txrx.2633452733 Dec 31 01:10:55 PM PST 23 Dec 31 01:17:02 PM PST 23 234273038354 ps
T1758 /workspace/coverage/default/22.spi_device_txrx.2168405758 Dec 31 01:09:44 PM PST 23 Dec 31 01:15:52 PM PST 23 77789733255 ps
T1759 /workspace/coverage/default/11.spi_device_flash_mode.2977399825 Dec 31 01:08:57 PM PST 23 Dec 31 01:09:36 PM PST 23 64349631978 ps
T1760 /workspace/coverage/default/48.spi_device_read_buffer_direct.3874037109 Dec 31 01:12:19 PM PST 23 Dec 31 01:12:28 PM PST 23 1628488497 ps
T1761 /workspace/coverage/default/7.spi_device_alert_test.2798541183 Dec 31 01:08:46 PM PST 23 Dec 31 01:08:48 PM PST 23 14225785 ps
T1762 /workspace/coverage/default/36.spi_device_tx_async_fifo_reset.1045123098 Dec 31 01:10:55 PM PST 23 Dec 31 01:10:59 PM PST 23 18093293 ps
T1763 /workspace/coverage/default/4.spi_device_flash_all.1335961224 Dec 31 01:07:58 PM PST 23 Dec 31 01:08:38 PM PST 23 2272031417 ps
T1764 /workspace/coverage/default/40.spi_device_intr.2641904842 Dec 31 01:11:17 PM PST 23 Dec 31 01:12:08 PM PST 23 8420136486 ps
T1765 /workspace/coverage/default/48.spi_device_tpm_sts_read.3825456184 Dec 31 01:12:08 PM PST 23 Dec 31 01:12:10 PM PST 23 135522396 ps
T1766 /workspace/coverage/default/20.spi_device_byte_transfer.2044265350 Dec 31 01:09:38 PM PST 23 Dec 31 01:09:46 PM PST 23 228308014 ps
T1767 /workspace/coverage/default/29.spi_device_abort.2017568257 Dec 31 01:10:16 PM PST 23 Dec 31 01:10:23 PM PST 23 51108275 ps
T1768 /workspace/coverage/default/14.spi_device_tpm_rw.3832138655 Dec 31 01:09:16 PM PST 23 Dec 31 01:09:25 PM PST 23 275641739 ps
T1769 /workspace/coverage/default/14.spi_device_stress_all.4235522143 Dec 31 01:09:13 PM PST 23 Dec 31 01:10:12 PM PST 23 40945293962 ps
T1770 /workspace/coverage/default/21.spi_device_intr.577598475 Dec 31 01:09:39 PM PST 23 Dec 31 01:10:31 PM PST 23 42665490845 ps
T310 /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3420241680 Dec 31 01:10:55 PM PST 23 Dec 31 01:11:04 PM PST 23 806301306 ps
T1771 /workspace/coverage/default/28.spi_device_intr.3372271011 Dec 31 01:10:18 PM PST 23 Dec 31 01:11:34 PM PST 23 35613880031 ps
T1772 /workspace/coverage/default/12.spi_device_tx_async_fifo_reset.2577069423 Dec 31 01:08:52 PM PST 23 Dec 31 01:08:57 PM PST 23 16099008 ps
T1773 /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.13116100 Dec 31 01:12:22 PM PST 23 Dec 31 01:12:42 PM PST 23 46318663673 ps
T1774 /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1499532950 Dec 31 01:09:02 PM PST 23 Dec 31 01:09:44 PM PST 23 23149454731 ps
T1775 /workspace/coverage/default/10.spi_device_read_buffer_direct.2774414803 Dec 31 01:08:34 PM PST 23 Dec 31 01:08:42 PM PST 23 2881150233 ps
T1776 /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1750477783 Dec 31 01:09:16 PM PST 23 Dec 31 01:09:40 PM PST 23 5635470355 ps
T1777 /workspace/coverage/default/3.spi_device_byte_transfer.3809139586 Dec 31 01:07:58 PM PST 23 Dec 31 01:08:01 PM PST 23 579420107 ps
T1778 /workspace/coverage/default/32.spi_device_intr.2588501898 Dec 31 01:10:52 PM PST 23 Dec 31 01:11:28 PM PST 23 5486398455 ps
T1779 /workspace/coverage/default/17.spi_device_tx_async_fifo_reset.1112254287 Dec 31 01:09:38 PM PST 23 Dec 31 01:09:43 PM PST 23 21411011 ps
T1780 /workspace/coverage/default/6.spi_device_byte_transfer.3780318699 Dec 31 01:08:04 PM PST 23 Dec 31 01:08:09 PM PST 23 171112037 ps
T1781 /workspace/coverage/default/23.spi_device_rx_timeout.2548543717 Dec 31 01:10:15 PM PST 23 Dec 31 01:10:25 PM PST 23 2894961425 ps
T1782 /workspace/coverage/default/22.spi_device_perf.724875417 Dec 31 01:10:15 PM PST 23 Dec 31 01:18:57 PM PST 23 19889528094 ps
T1783 /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.821686084 Dec 31 01:07:31 PM PST 23 Dec 31 01:07:41 PM PST 23 4212699096 ps
T1784 /workspace/coverage/default/28.spi_device_upload.1040246421 Dec 31 01:10:16 PM PST 23 Dec 31 01:10:31 PM PST 23 2167577526 ps
T1785 /workspace/coverage/default/49.spi_device_tpm_all.2164474524 Dec 31 01:12:12 PM PST 23 Dec 31 01:12:19 PM PST 23 408133701 ps
T1786 /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2360053895 Dec 31 01:11:17 PM PST 23 Dec 31 01:12:01 PM PST 23 55629381186 ps

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1413006458
Short name T7
Test name
Test status
Simulation time 69695710692 ps
CPU time 405.27 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:16:31 PM PST 23
Peak memory 267904 kb
Host smart-41043d13-7ebc-46eb-899f-3e84bad446f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413006458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1413006458
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_extreme_fifo_size.1230083371
Short name T11
Test name
Test status
Simulation time 69539084161 ps
CPU time 2557.09 seconds
Started Dec 31 01:09:11 PM PST 23
Finished Dec 31 01:51:49 PM PST 23
Peak memory 221088 kb
Host smart-6f903f87-c527-4050-b728-d220b23d6ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230083371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_extreme_fifo_size.1230083371
Directory /workspace/15.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3066185574
Short name T23
Test name
Test status
Simulation time 373149167030 ps
CPU time 750.2 seconds
Started Dec 31 01:10:13 PM PST 23
Finished Dec 31 01:22:44 PM PST 23
Peak memory 320408 kb
Host smart-0dd583e1-7187-49d7-ab87-d6842e3d281a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066185574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3066185574
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.523111523
Short name T112
Test name
Test status
Simulation time 2062980532 ps
CPU time 20.51 seconds
Started Dec 31 12:49:15 PM PST 23
Finished Dec 31 12:49:37 PM PST 23
Peak memory 215776 kb
Host smart-f8745aa9-2c4e-43a6-b844-d03bd1c9ea98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523111523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.523111523
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2543176318
Short name T62
Test name
Test status
Simulation time 1172044916581 ps
CPU time 3745.64 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 02:13:43 PM PST 23
Peak memory 437796 kb
Host smart-b477f916-0469-4616-9464-8f99bfa50e11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543176318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2543176318
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.51060615
Short name T60
Test name
Test status
Simulation time 14645686 ps
CPU time 0.79 seconds
Started Dec 31 12:48:58 PM PST 23
Finished Dec 31 12:49:00 PM PST 23
Peak memory 204756 kb
Host smart-cd813b08-fdf3-47e6-95a1-0c478c8a1cd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51060615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.51060615
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3357478383
Short name T100
Test name
Test status
Simulation time 407753927789 ps
CPU time 711.45 seconds
Started Dec 31 01:09:27 PM PST 23
Finished Dec 31 01:21:24 PM PST 23
Peak memory 265152 kb
Host smart-e4fab92f-14f4-4ef7-8b21-052014ff99dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357478383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3357478383
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3395319302
Short name T74
Test name
Test status
Simulation time 20063115 ps
CPU time 0.75 seconds
Started Dec 31 01:07:31 PM PST 23
Finished Dec 31 01:07:33 PM PST 23
Peak memory 216724 kb
Host smart-bb96ff0d-8316-46cd-980d-b53965a161c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395319302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3395319302
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1054044056
Short name T213
Test name
Test status
Simulation time 37473571521 ps
CPU time 251.31 seconds
Started Dec 31 01:10:33 PM PST 23
Finished Dec 31 01:14:55 PM PST 23
Peak memory 284600 kb
Host smart-643a50f2-3e0f-4d7b-9cfc-2baf9563f0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054044056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1054044056
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1048755363
Short name T71
Test name
Test status
Simulation time 885780376 ps
CPU time 21.19 seconds
Started Dec 31 12:49:23 PM PST 23
Finished Dec 31 12:49:46 PM PST 23
Peak memory 215796 kb
Host smart-d54ffaca-50e6-4d9c-9d71-eaeb9a7ee028
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048755363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1048755363
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.713303925
Short name T235
Test name
Test status
Simulation time 484197600108 ps
CPU time 1730.38 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:40:08 PM PST 23
Peak memory 334024 kb
Host smart-d0d9c823-5e4f-42ee-9a33-84a04c109009
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713303925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.713303925
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3006297698
Short name T120
Test name
Test status
Simulation time 239203446377 ps
CPU time 1987.4 seconds
Started Dec 31 01:11:54 PM PST 23
Finished Dec 31 01:45:03 PM PST 23
Peak memory 389088 kb
Host smart-e6aba1b7-d787-4b3b-9928-feff20c8152b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006297698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3006297698
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.636488188
Short name T154
Test name
Test status
Simulation time 363579243 ps
CPU time 11.44 seconds
Started Dec 31 01:10:54 PM PST 23
Finished Dec 31 01:11:09 PM PST 23
Peak memory 238584 kb
Host smart-8e152467-cc9a-42da-9571-d6aef8f5a0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636488188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.636488188
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1944936966
Short name T19
Test name
Test status
Simulation time 110012498116 ps
CPU time 482.54 seconds
Started Dec 31 01:10:50 PM PST 23
Finished Dec 31 01:18:54 PM PST 23
Peak memory 274260 kb
Host smart-1bfccfcf-91c4-48fb-9a35-b1f66768970f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944936966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1944936966
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2757133143
Short name T114
Test name
Test status
Simulation time 96608308 ps
CPU time 3.72 seconds
Started Dec 31 12:49:19 PM PST 23
Finished Dec 31 12:49:24 PM PST 23
Peak memory 215948 kb
Host smart-5c092709-6396-4659-8f52-bf355e7e0898
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757133143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
757133143
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3717709475
Short name T239
Test name
Test status
Simulation time 11175352839 ps
CPU time 170.84 seconds
Started Dec 31 01:09:01 PM PST 23
Finished Dec 31 01:12:00 PM PST 23
Peak memory 284268 kb
Host smart-44a4c644-115f-4a8e-bae4-6b64ea3f48c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717709475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3717709475
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3419096418
Short name T270
Test name
Test status
Simulation time 31219579122 ps
CPU time 55.84 seconds
Started Dec 31 01:10:36 PM PST 23
Finished Dec 31 01:11:40 PM PST 23
Peak memory 252584 kb
Host smart-d9f69db9-1aeb-47d5-be1d-71a868401e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419096418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3419096418
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.519753307
Short name T140
Test name
Test status
Simulation time 175572224 ps
CPU time 2.59 seconds
Started Dec 31 12:49:08 PM PST 23
Finished Dec 31 12:49:12 PM PST 23
Peak memory 215804 kb
Host smart-ece16041-fb7c-4951-a436-0182ed6e84ed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519753307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.519753307
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2814073694
Short name T130
Test name
Test status
Simulation time 166340993 ps
CPU time 0.75 seconds
Started Dec 31 12:49:26 PM PST 23
Finished Dec 31 12:49:28 PM PST 23
Peak memory 204840 kb
Host smart-23637570-04ec-41a2-9c41-fdd06695c4c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814073694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2814073694
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.24068226
Short name T226
Test name
Test status
Simulation time 23475868470 ps
CPU time 188.42 seconds
Started Dec 31 01:11:12 PM PST 23
Finished Dec 31 01:14:22 PM PST 23
Peak memory 273752 kb
Host smart-7123c160-553b-4e7b-96a9-200369307350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24068226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.24068226
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1867163817
Short name T301
Test name
Test status
Simulation time 172147399471 ps
CPU time 1557.05 seconds
Started Dec 31 01:11:13 PM PST 23
Finished Dec 31 01:37:12 PM PST 23
Peak memory 317188 kb
Host smart-2dde29e8-79c3-4b8f-8878-009a2de59fd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867163817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1867163817
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3818417109
Short name T190
Test name
Test status
Simulation time 119447411697 ps
CPU time 265.87 seconds
Started Dec 31 01:08:00 PM PST 23
Finished Dec 31 01:12:27 PM PST 23
Peak memory 270176 kb
Host smart-7411a26a-7680-4ce0-8ed3-ed05ab175bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818417109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3818417109
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.288765350
Short name T215
Test name
Test status
Simulation time 88487990407 ps
CPU time 420.92 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:15:56 PM PST 23
Peak memory 278560 kb
Host smart-822f540a-90da-4563-8468-73d7eddda24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288765350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.288765350
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1233758142
Short name T80
Test name
Test status
Simulation time 36436678 ps
CPU time 0.98 seconds
Started Dec 31 01:07:33 PM PST 23
Finished Dec 31 01:07:36 PM PST 23
Peak memory 238164 kb
Host smart-7d38c8a9-0533-4f02-8347-c97cada474bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233758142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1233758142
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1597926451
Short name T8
Test name
Test status
Simulation time 470894747541 ps
CPU time 2235.77 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:48:35 PM PST 23
Peak memory 430324 kb
Host smart-8c14c488-b156-437d-a8cd-e7eeeb40ec23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597926451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1597926451
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.154840537
Short name T93
Test name
Test status
Simulation time 11242451575 ps
CPU time 45.65 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:10:32 PM PST 23
Peak memory 224308 kb
Host smart-6af2604e-9be0-4177-ae72-e40b50919e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154840537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.154840537
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1677183437
Short name T46
Test name
Test status
Simulation time 56080584892 ps
CPU time 1607.9 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:38:07 PM PST 23
Peak memory 394528 kb
Host smart-74db6a60-4f27-4f1f-b882-507637250051
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677183437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1677183437
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1849407036
Short name T295
Test name
Test status
Simulation time 109166461624 ps
CPU time 259.57 seconds
Started Dec 31 01:11:13 PM PST 23
Finished Dec 31 01:15:34 PM PST 23
Peak memory 264112 kb
Host smart-a1e0a5b1-3bd4-4b74-a70f-ca3a9793f3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849407036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1849407036
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.890558403
Short name T34
Test name
Test status
Simulation time 107373713 ps
CPU time 1.06 seconds
Started Dec 31 01:07:29 PM PST 23
Finished Dec 31 01:07:31 PM PST 23
Peak memory 218892 kb
Host smart-e2a4adab-7393-4a3e-9a94-588482fb0d1b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890558403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.890558403
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1089629423
Short name T69
Test name
Test status
Simulation time 14642434 ps
CPU time 0.71 seconds
Started Dec 31 01:09:00 PM PST 23
Finished Dec 31 01:09:09 PM PST 23
Peak memory 206476 kb
Host smart-f092bdea-392a-4941-86ec-8ca36da2b95a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089629423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1089629423
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2941509705
Short name T18
Test name
Test status
Simulation time 14529770562 ps
CPU time 165.41 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:14:07 PM PST 23
Peak memory 270736 kb
Host smart-64f4ef9a-1fd9-4c4d-b18d-02c8be88e9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941509705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2941509705
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_bit_transfer.1695334974
Short name T3
Test name
Test status
Simulation time 572769488 ps
CPU time 2.99 seconds
Started Dec 31 01:10:53 PM PST 23
Finished Dec 31 01:10:58 PM PST 23
Peak memory 216900 kb
Host smart-d04d1bbe-965f-49e9-8ea1-8329914a4560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695334974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_bit_transfer.1695334974
Directory /workspace/34.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1841908109
Short name T1027
Test name
Test status
Simulation time 12457871198 ps
CPU time 36.23 seconds
Started Dec 31 01:08:57 PM PST 23
Finished Dec 31 01:09:41 PM PST 23
Peak memory 249656 kb
Host smart-ce9e1784-cf20-4d48-87b7-b42e2cd06697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841908109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1841908109
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.559561860
Short name T97
Test name
Test status
Simulation time 2144314170 ps
CPU time 9.9 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:09:54 PM PST 23
Peak memory 216760 kb
Host smart-30313459-cc29-468b-ab80-2936ffc38fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559561860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.559561860
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3344823694
Short name T206
Test name
Test status
Simulation time 9282731959 ps
CPU time 95.07 seconds
Started Dec 31 01:08:58 PM PST 23
Finished Dec 31 01:10:41 PM PST 23
Peak memory 265188 kb
Host smart-87f6d735-41ae-4cd1-9bcc-5addda037878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344823694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3344823694
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2262412595
Short name T171
Test name
Test status
Simulation time 14677268 ps
CPU time 0.73 seconds
Started Dec 31 12:48:42 PM PST 23
Finished Dec 31 12:48:45 PM PST 23
Peak memory 204912 kb
Host smart-3c980f22-1d6c-46da-8753-42f0405c5b6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262412595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
262412595
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2897055245
Short name T199
Test name
Test status
Simulation time 1173947095 ps
CPU time 18.39 seconds
Started Dec 31 12:49:01 PM PST 23
Finished Dec 31 12:49:20 PM PST 23
Peak memory 216180 kb
Host smart-cf4d4a58-bbac-4577-80d5-5095ecac866e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897055245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2897055245
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.962139991
Short name T315
Test name
Test status
Simulation time 144034248460 ps
CPU time 258.97 seconds
Started Dec 31 01:08:27 PM PST 23
Finished Dec 31 01:12:47 PM PST 23
Peak memory 255444 kb
Host smart-7b019f0d-99fe-4b3d-914c-4113aa3421d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962139991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
962139991
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1288962571
Short name T221
Test name
Test status
Simulation time 224992793299 ps
CPU time 330.44 seconds
Started Dec 31 01:10:00 PM PST 23
Finished Dec 31 01:15:33 PM PST 23
Peak memory 266060 kb
Host smart-205215fd-12ed-48b5-a967-ff3f3e2588ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288962571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1288962571
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.47293567
Short name T1684
Test name
Test status
Simulation time 75243724636 ps
CPU time 156.15 seconds
Started Dec 31 01:10:01 PM PST 23
Finished Dec 31 01:12:39 PM PST 23
Peak memory 267296 kb
Host smart-38d70954-bb71-446d-ab7c-66673cb9e355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47293567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.47293567
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2699400736
Short name T214
Test name
Test status
Simulation time 17706840161 ps
CPU time 242.64 seconds
Started Dec 31 01:10:51 PM PST 23
Finished Dec 31 01:14:55 PM PST 23
Peak memory 276452 kb
Host smart-00281d60-4850-42e4-8aeb-59c820e34531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699400736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2699400736
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.4259668130
Short name T252
Test name
Test status
Simulation time 77311270802 ps
CPU time 175.49 seconds
Started Dec 31 01:10:52 PM PST 23
Finished Dec 31 01:13:49 PM PST 23
Peak memory 254532 kb
Host smart-10c47bd8-a505-490a-b804-9d17d6ac2c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259668130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.4259668130
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1844635277
Short name T306
Test name
Test status
Simulation time 355433830936 ps
CPU time 568.75 seconds
Started Dec 31 01:08:28 PM PST 23
Finished Dec 31 01:17:58 PM PST 23
Peak memory 262808 kb
Host smart-9ff6c0b1-6fcd-436d-a4f7-12ae7ae82e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844635277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1844635277
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_fifo_underflow_overflow.1263579956
Short name T44
Test name
Test status
Simulation time 129297126262 ps
CPU time 245 seconds
Started Dec 31 01:09:41 PM PST 23
Finished Dec 31 01:13:56 PM PST 23
Peak memory 409648 kb
Host smart-aa5be7fd-383e-435a-817f-0b30a3456fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263579956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_fifo_underflow_overf
low.1263579956
Directory /workspace/21.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.836570122
Short name T165
Test name
Test status
Simulation time 53420873 ps
CPU time 2.47 seconds
Started Dec 31 12:49:20 PM PST 23
Finished Dec 31 12:49:24 PM PST 23
Peak memory 218736 kb
Host smart-31b490cc-3097-451c-adac-81cb2dc53963
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836570122 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.836570122
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2516926122
Short name T196
Test name
Test status
Simulation time 201994721 ps
CPU time 6.49 seconds
Started Dec 31 12:49:12 PM PST 23
Finished Dec 31 12:49:20 PM PST 23
Peak memory 215792 kb
Host smart-3215ac2b-3555-49a3-9bf4-d99adfce6d7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516926122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2516926122
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_fifo_underflow_overflow.45654408
Short name T984
Test name
Test status
Simulation time 114059333763 ps
CPU time 174.11 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:11:52 PM PST 23
Peak memory 310728 kb
Host smart-c9f7bccb-be8c-4863-aac3-824d4590fd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45654408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_fifo_underflow_overflo
w.45654408
Directory /workspace/10.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.4097876591
Short name T212
Test name
Test status
Simulation time 88214914218 ps
CPU time 218.9 seconds
Started Dec 31 01:08:48 PM PST 23
Finished Dec 31 01:12:29 PM PST 23
Peak memory 272368 kb
Host smart-7dd407f4-6ede-44e4-b3a6-49da7cb7baf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097876591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.4097876591
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_intr.3692414877
Short name T185
Test name
Test status
Simulation time 11792817044 ps
CPU time 76.75 seconds
Started Dec 31 01:09:27 PM PST 23
Finished Dec 31 01:10:50 PM PST 23
Peak memory 248712 kb
Host smart-627dbccf-6bdd-480b-82ff-991b855734af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692414877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intr.3692414877
Directory /workspace/17.spi_device_intr/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3420241680
Short name T310
Test name
Test status
Simulation time 806301306 ps
CPU time 5.81 seconds
Started Dec 31 01:10:55 PM PST 23
Finished Dec 31 01:11:04 PM PST 23
Peak memory 233272 kb
Host smart-19e4a1b9-5950-4e91-af81-e891b0e1152c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420241680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3420241680
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1721280745
Short name T225
Test name
Test status
Simulation time 6511438087 ps
CPU time 72.82 seconds
Started Dec 31 01:11:22 PM PST 23
Finished Dec 31 01:12:39 PM PST 23
Peak memory 251764 kb
Host smart-ddcb272b-84ce-4094-9304-39537f803e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721280745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1721280745
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1265909563
Short name T4
Test name
Test status
Simulation time 9311396157 ps
CPU time 29.95 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:09:26 PM PST 23
Peak memory 233384 kb
Host smart-3281574f-5891-497c-b1f8-35a2339272ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265909563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1265909563
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_abort.588053541
Short name T65
Test name
Test status
Simulation time 26851901 ps
CPU time 0.77 seconds
Started Dec 31 01:08:49 PM PST 23
Finished Dec 31 01:08:53 PM PST 23
Peak memory 206572 kb
Host smart-849e3ca9-6c8f-45aa-863b-d6a5e7f04922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588053541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_abort.588053541
Directory /workspace/3.spi_device_abort/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2767762995
Short name T125
Test name
Test status
Simulation time 388770850 ps
CPU time 3.49 seconds
Started Dec 31 12:49:31 PM PST 23
Finished Dec 31 12:49:38 PM PST 23
Peak memory 215936 kb
Host smart-46890b95-ce5a-4ce9-901e-9c2290fe4506
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767762995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
767762995
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/13.spi_device_rx_async_fifo_reset.1867883466
Short name T540
Test name
Test status
Simulation time 44106480 ps
CPU time 0.91 seconds
Started Dec 31 01:08:58 PM PST 23
Finished Dec 31 01:09:07 PM PST 23
Peak memory 208216 kb
Host smart-0fde0e01-052d-4fab-a254-7f9671181855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867883466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_rx_async_fifo_reset.1867883466
Directory /workspace/13.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/16.spi_device_tx_async_fifo_reset.1676329511
Short name T123
Test name
Test status
Simulation time 55221847 ps
CPU time 0.77 seconds
Started Dec 31 01:09:14 PM PST 23
Finished Dec 31 01:09:18 PM PST 23
Peak memory 208448 kb
Host smart-a7e0cb8e-07e7-4463-ad56-47f1c7400c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676329511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tx_async_fifo_reset.1676329511
Directory /workspace/16.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2716790834
Short name T174
Test name
Test status
Simulation time 21054634273 ps
CPU time 93.47 seconds
Started Dec 31 01:09:40 PM PST 23
Finished Dec 31 01:11:23 PM PST 23
Peak memory 262252 kb
Host smart-38c39a36-bc88-42ab-a4de-7c7f566ab685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716790834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2716790834
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1402742148
Short name T341
Test name
Test status
Simulation time 1493179122 ps
CPU time 9.52 seconds
Started Dec 31 12:48:47 PM PST 23
Finished Dec 31 12:48:57 PM PST 23
Peak memory 215944 kb
Host smart-e36b902d-0814-4bd1-8b81-a9c33f54f4b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402742148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1402742148
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3371081391
Short name T421
Test name
Test status
Simulation time 1000668846 ps
CPU time 15.1 seconds
Started Dec 31 12:49:02 PM PST 23
Finished Dec 31 12:49:19 PM PST 23
Peak memory 207592 kb
Host smart-eca5828f-0d8b-4a5c-bd5d-f7bd3d2407b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371081391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3371081391
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3352885678
Short name T441
Test name
Test status
Simulation time 102687666 ps
CPU time 1.42 seconds
Started Dec 31 12:48:55 PM PST 23
Finished Dec 31 12:48:57 PM PST 23
Peak memory 207540 kb
Host smart-3758c6fe-0e25-4dab-8700-648def960e6a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352885678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3352885678
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3749668432
Short name T407
Test name
Test status
Simulation time 99308224 ps
CPU time 2.54 seconds
Started Dec 31 12:49:22 PM PST 23
Finished Dec 31 12:49:26 PM PST 23
Peak memory 219788 kb
Host smart-babec4d0-4126-4eda-970a-4e01be4e068e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749668432 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3749668432
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3797739973
Short name T138
Test name
Test status
Simulation time 201047232 ps
CPU time 2.52 seconds
Started Dec 31 12:49:05 PM PST 23
Finished Dec 31 12:49:09 PM PST 23
Peak memory 215684 kb
Host smart-0bc3d3ba-7c25-44f5-a988-2fdd42244335
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797739973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
797739973
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3710452745
Short name T369
Test name
Test status
Simulation time 764982011 ps
CPU time 13.19 seconds
Started Dec 31 12:49:12 PM PST 23
Finished Dec 31 12:49:27 PM PST 23
Peak memory 215780 kb
Host smart-fd20f6ee-6ebf-4ffc-9e23-af89c3477191
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710452745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3710452745
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.414139656
Short name T423
Test name
Test status
Simulation time 157333484 ps
CPU time 3.16 seconds
Started Dec 31 12:49:03 PM PST 23
Finished Dec 31 12:49:07 PM PST 23
Peak memory 215708 kb
Host smart-c007eb7e-f23b-4061-a950-74571a42c053
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414139656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.414139656
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3728776524
Short name T438
Test name
Test status
Simulation time 641918109 ps
CPU time 4.52 seconds
Started Dec 31 12:49:17 PM PST 23
Finished Dec 31 12:49:23 PM PST 23
Peak memory 216056 kb
Host smart-c5c61d58-d59e-43bd-8e34-f99f57797e0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728776524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
728776524
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.981683214
Short name T435
Test name
Test status
Simulation time 4537597923 ps
CPU time 8.17 seconds
Started Dec 31 12:48:41 PM PST 23
Finished Dec 31 12:48:51 PM PST 23
Peak memory 215964 kb
Host smart-7f55551f-8239-4d6f-a98a-d15bfe25e93e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981683214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.981683214
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.375316379
Short name T440
Test name
Test status
Simulation time 2115121711 ps
CPU time 16.23 seconds
Started Dec 31 12:48:53 PM PST 23
Finished Dec 31 12:49:10 PM PST 23
Peak memory 217040 kb
Host smart-3ae0f18f-a491-4f0e-b903-90d316bc3790
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375316379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.375316379
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.917494483
Short name T349
Test name
Test status
Simulation time 2791709268 ps
CPU time 14.62 seconds
Started Dec 31 12:49:17 PM PST 23
Finished Dec 31 12:49:33 PM PST 23
Peak memory 215888 kb
Host smart-c4052b89-4b8d-4560-830e-169c4dbf3494
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917494483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.917494483
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1307782600
Short name T147
Test name
Test status
Simulation time 22370591 ps
CPU time 0.97 seconds
Started Dec 31 12:49:03 PM PST 23
Finished Dec 31 12:49:05 PM PST 23
Peak memory 207432 kb
Host smart-c8e34d9d-961b-48a8-9142-1154d61bb487
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307782600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1307782600
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2408918364
Short name T137
Test name
Test status
Simulation time 40856732 ps
CPU time 2.47 seconds
Started Dec 31 12:49:54 PM PST 23
Finished Dec 31 12:49:59 PM PST 23
Peak memory 215764 kb
Host smart-d96911af-ddfb-4ca4-b882-a5df78c9880b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408918364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
408918364
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.719638226
Short name T417
Test name
Test status
Simulation time 34458199 ps
CPU time 0.7 seconds
Started Dec 31 12:48:38 PM PST 23
Finished Dec 31 12:48:39 PM PST 23
Peak memory 204864 kb
Host smart-08103088-9d9c-43bc-b04c-bd8bd6462736
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719638226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.719638226
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2183786873
Short name T422
Test name
Test status
Simulation time 209585604 ps
CPU time 6.59 seconds
Started Dec 31 12:48:55 PM PST 23
Finished Dec 31 12:49:02 PM PST 23
Peak memory 215764 kb
Host smart-abfc4ec0-c605-4c8b-9401-f26c12171d86
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183786873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2183786873
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3568792795
Short name T335
Test name
Test status
Simulation time 4091532686 ps
CPU time 5.13 seconds
Started Dec 31 12:49:03 PM PST 23
Finished Dec 31 12:49:09 PM PST 23
Peak memory 215796 kb
Host smart-b859a417-f279-4c0b-b23a-34f98a631510
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568792795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3568792795
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3309144469
Short name T392
Test name
Test status
Simulation time 213762679 ps
CPU time 4.25 seconds
Started Dec 31 12:49:16 PM PST 23
Finished Dec 31 12:49:21 PM PST 23
Peak memory 215720 kb
Host smart-7ef19f0b-61be-48de-8f4c-1e4e98eae131
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309144469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3309144469
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2786719384
Short name T200
Test name
Test status
Simulation time 278413509 ps
CPU time 7.6 seconds
Started Dec 31 12:49:11 PM PST 23
Finished Dec 31 12:49:20 PM PST 23
Peak memory 215832 kb
Host smart-1e81d20e-524a-4c1d-80ac-9aef9feec28d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786719384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2786719384
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4250025232
Short name T405
Test name
Test status
Simulation time 45985347 ps
CPU time 1.46 seconds
Started Dec 31 12:49:16 PM PST 23
Finished Dec 31 12:49:19 PM PST 23
Peak memory 217356 kb
Host smart-0910c4f2-5685-4b46-b3a3-70f979e097ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250025232 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.4250025232
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3446934011
Short name T136
Test name
Test status
Simulation time 263559252 ps
CPU time 2.45 seconds
Started Dec 31 12:49:05 PM PST 23
Finished Dec 31 12:49:09 PM PST 23
Peak memory 215852 kb
Host smart-9bac4b77-bc0f-4f92-b189-0fb31ba66e90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446934011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3446934011
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1774482943
Short name T430
Test name
Test status
Simulation time 15862528 ps
CPU time 0.75 seconds
Started Dec 31 12:49:08 PM PST 23
Finished Dec 31 12:49:11 PM PST 23
Peak memory 204892 kb
Host smart-9e1f38d6-a1a9-49a1-a02c-ae4115e0b731
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774482943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1774482943
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.912949301
Short name T370
Test name
Test status
Simulation time 164097432 ps
CPU time 3.25 seconds
Started Dec 31 12:49:26 PM PST 23
Finished Dec 31 12:49:31 PM PST 23
Peak memory 215736 kb
Host smart-c0125a46-f655-41cc-a385-5a444ecf52b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912949301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.912949301
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1325279719
Short name T393
Test name
Test status
Simulation time 1693867126 ps
CPU time 5.68 seconds
Started Dec 31 12:49:02 PM PST 23
Finished Dec 31 12:49:09 PM PST 23
Peak memory 217640 kb
Host smart-1282d459-4a73-4fd1-aa34-8463e0942753
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325279719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1325279719
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1843198387
Short name T348
Test name
Test status
Simulation time 96249338 ps
CPU time 2.15 seconds
Started Dec 31 12:49:23 PM PST 23
Finished Dec 31 12:49:27 PM PST 23
Peak memory 218044 kb
Host smart-3d8a810c-7027-46d0-84c2-c56d360e9dd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843198387 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1843198387
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3052213110
Short name T133
Test name
Test status
Simulation time 38424918 ps
CPU time 2.22 seconds
Started Dec 31 12:49:16 PM PST 23
Finished Dec 31 12:49:20 PM PST 23
Peak memory 215740 kb
Host smart-610765cd-af54-404e-b8bd-fd1c0cab3ea0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052213110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3052213110
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.677947774
Short name T386
Test name
Test status
Simulation time 12135447 ps
CPU time 0.68 seconds
Started Dec 31 12:49:43 PM PST 23
Finished Dec 31 12:49:45 PM PST 23
Peak memory 204872 kb
Host smart-b364e4e8-c2e6-46a0-bb05-099d3433014b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677947774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.677947774
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4040394235
Short name T134
Test name
Test status
Simulation time 3510395309 ps
CPU time 4.32 seconds
Started Dec 31 12:49:26 PM PST 23
Finished Dec 31 12:49:32 PM PST 23
Peak memory 216088 kb
Host smart-669719b8-b8e1-442e-bb55-6134abb50939
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040394235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.4040394235
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3548981429
Short name T379
Test name
Test status
Simulation time 82779434 ps
CPU time 2.65 seconds
Started Dec 31 12:49:16 PM PST 23
Finished Dec 31 12:49:20 PM PST 23
Peak memory 216004 kb
Host smart-db89f036-30de-46d6-9a10-b93e8c48e166
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548981429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3548981429
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1198953062
Short name T163
Test name
Test status
Simulation time 2594943032 ps
CPU time 7.59 seconds
Started Dec 31 12:49:15 PM PST 23
Finished Dec 31 12:49:24 PM PST 23
Peak memory 215968 kb
Host smart-30c0f9c3-7c95-4f4c-97b0-b200bed6fd8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198953062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1198953062
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3307517334
Short name T129
Test name
Test status
Simulation time 135688488 ps
CPU time 2.62 seconds
Started Dec 31 12:49:05 PM PST 23
Finished Dec 31 12:49:09 PM PST 23
Peak memory 218340 kb
Host smart-166c444e-58f9-412d-a178-5e656cd9a1f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307517334 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3307517334
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2873595661
Short name T366
Test name
Test status
Simulation time 124013084 ps
CPU time 2.61 seconds
Started Dec 31 12:49:05 PM PST 23
Finished Dec 31 12:49:08 PM PST 23
Peak memory 215724 kb
Host smart-997d03c2-74f7-40dc-9237-16892c0b8c25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873595661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2873595661
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3681954945
Short name T355
Test name
Test status
Simulation time 17796798 ps
CPU time 0.7 seconds
Started Dec 31 12:49:18 PM PST 23
Finished Dec 31 12:49:20 PM PST 23
Peak memory 204908 kb
Host smart-3dff96b4-d141-48bf-acba-a96ffc84c62d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681954945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3681954945
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3621031096
Short name T410
Test name
Test status
Simulation time 67651874 ps
CPU time 3.83 seconds
Started Dec 31 12:49:20 PM PST 23
Finished Dec 31 12:49:25 PM PST 23
Peak memory 215808 kb
Host smart-9333a3ea-bacf-4fa9-9dc6-56351b7b2b05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621031096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3621031096
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3559626663
Short name T344
Test name
Test status
Simulation time 88935079 ps
CPU time 1.6 seconds
Started Dec 31 12:49:14 PM PST 23
Finished Dec 31 12:49:17 PM PST 23
Peak memory 215964 kb
Host smart-4fd8443b-a5d9-4f23-9b80-4ae9aba23541
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559626663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3559626663
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.992995605
Short name T408
Test name
Test status
Simulation time 568874095 ps
CPU time 6.46 seconds
Started Dec 31 12:49:07 PM PST 23
Finished Dec 31 12:49:15 PM PST 23
Peak memory 223176 kb
Host smart-dc460fe9-2e88-4053-a964-e05e332baf37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992995605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.992995605
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1142249924
Short name T372
Test name
Test status
Simulation time 84248690 ps
CPU time 2.25 seconds
Started Dec 31 12:48:55 PM PST 23
Finished Dec 31 12:48:58 PM PST 23
Peak memory 218252 kb
Host smart-d0ac85fb-63d5-47f8-ad45-cb2d94f9cf96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142249924 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1142249924
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1460139496
Short name T420
Test name
Test status
Simulation time 74666939 ps
CPU time 2.45 seconds
Started Dec 31 12:49:23 PM PST 23
Finished Dec 31 12:49:26 PM PST 23
Peak memory 215808 kb
Host smart-0accfe95-1fee-4e93-ae7e-94b53b732453
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460139496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1460139496
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1281489727
Short name T403
Test name
Test status
Simulation time 35802861 ps
CPU time 0.69 seconds
Started Dec 31 12:49:01 PM PST 23
Finished Dec 31 12:49:02 PM PST 23
Peak memory 204924 kb
Host smart-d25c4cba-cd60-4271-87a8-c5644298fa6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281489727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1281489727
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3288825874
Short name T432
Test name
Test status
Simulation time 70837879 ps
CPU time 1.93 seconds
Started Dec 31 12:49:20 PM PST 23
Finished Dec 31 12:49:23 PM PST 23
Peak memory 215676 kb
Host smart-f6f56f9f-e13e-4d82-b059-1f93e941af39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288825874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3288825874
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2568121808
Short name T346
Test name
Test status
Simulation time 84929067 ps
CPU time 2.11 seconds
Started Dec 31 12:49:18 PM PST 23
Finished Dec 31 12:49:22 PM PST 23
Peak memory 215856 kb
Host smart-9a57ca0c-f7db-4cfd-ba16-7b88015e5ff6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568121808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2568121808
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3861009420
Short name T404
Test name
Test status
Simulation time 101099943 ps
CPU time 6.13 seconds
Started Dec 31 12:49:12 PM PST 23
Finished Dec 31 12:49:19 PM PST 23
Peak memory 215824 kb
Host smart-42cc6ad9-b82b-4835-962a-fccea45a181a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861009420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3861009420
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1026173171
Short name T364
Test name
Test status
Simulation time 33391195 ps
CPU time 1.23 seconds
Started Dec 31 12:49:11 PM PST 23
Finished Dec 31 12:49:13 PM PST 23
Peak memory 216244 kb
Host smart-8ac0c68e-4997-4753-882e-53ce14b9f890
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026173171 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1026173171
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3298036816
Short name T135
Test name
Test status
Simulation time 33021086 ps
CPU time 1.95 seconds
Started Dec 31 12:49:02 PM PST 23
Finished Dec 31 12:49:05 PM PST 23
Peak memory 215820 kb
Host smart-3eb14700-d620-4fae-b600-49a02146a2f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298036816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3298036816
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3310957750
Short name T388
Test name
Test status
Simulation time 57983581 ps
CPU time 0.79 seconds
Started Dec 31 12:48:57 PM PST 23
Finished Dec 31 12:48:59 PM PST 23
Peak memory 204856 kb
Host smart-661102a2-d2c6-4c7c-86b8-a248eac3665d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310957750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3310957750
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2717805602
Short name T385
Test name
Test status
Simulation time 1395756597 ps
CPU time 4.16 seconds
Started Dec 31 12:49:28 PM PST 23
Finished Dec 31 12:49:38 PM PST 23
Peak memory 215800 kb
Host smart-3de93f70-a911-445a-97f9-0df897006d46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717805602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2717805602
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1867587003
Short name T115
Test name
Test status
Simulation time 33156093 ps
CPU time 2.16 seconds
Started Dec 31 12:49:18 PM PST 23
Finished Dec 31 12:49:22 PM PST 23
Peak memory 215960 kb
Host smart-26de3163-2af4-42e3-8c84-124fb64d9769
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867587003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1867587003
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.478345202
Short name T336
Test name
Test status
Simulation time 32216627 ps
CPU time 1.74 seconds
Started Dec 31 12:49:23 PM PST 23
Finished Dec 31 12:49:26 PM PST 23
Peak memory 218080 kb
Host smart-f73aa829-dfb3-4c8a-a33b-09c412c8f253
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478345202 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.478345202
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.410524607
Short name T143
Test name
Test status
Simulation time 70390962 ps
CPU time 1.8 seconds
Started Dec 31 12:49:10 PM PST 23
Finished Dec 31 12:49:13 PM PST 23
Peak memory 207576 kb
Host smart-45b9d41b-1343-46b5-8a3a-7062dc1ca7d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410524607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.410524607
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3520472976
Short name T59
Test name
Test status
Simulation time 10904699 ps
CPU time 0.7 seconds
Started Dec 31 12:49:27 PM PST 23
Finished Dec 31 12:49:29 PM PST 23
Peak memory 204848 kb
Host smart-a7ba5ac0-7e54-4424-827e-4ecd206f5616
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520472976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3520472976
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3417621884
Short name T168
Test name
Test status
Simulation time 132142351 ps
CPU time 4.23 seconds
Started Dec 31 12:49:29 PM PST 23
Finished Dec 31 12:49:34 PM PST 23
Peak memory 215724 kb
Host smart-ca50a1c5-a18a-43b5-827b-2cf6d94ab86c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417621884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3417621884
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2128406323
Short name T437
Test name
Test status
Simulation time 55026326 ps
CPU time 3.87 seconds
Started Dec 31 12:49:31 PM PST 23
Finished Dec 31 12:49:36 PM PST 23
Peak memory 216008 kb
Host smart-18c9c44b-5426-4a05-8723-2c7ba8667249
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128406323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2128406323
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3225229471
Short name T436
Test name
Test status
Simulation time 413860777 ps
CPU time 12.82 seconds
Started Dec 31 12:49:27 PM PST 23
Finished Dec 31 12:49:41 PM PST 23
Peak memory 215792 kb
Host smart-9d666e9e-8b1f-4f3a-9096-8ace50c692a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225229471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3225229471
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3654491636
Short name T362
Test name
Test status
Simulation time 39513011 ps
CPU time 1.56 seconds
Started Dec 31 12:49:08 PM PST 23
Finished Dec 31 12:49:10 PM PST 23
Peak memory 217408 kb
Host smart-e75d4814-3cc5-42ca-b8f0-c4fa22b0d6f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654491636 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3654491636
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1508570168
Short name T141
Test name
Test status
Simulation time 124233242 ps
CPU time 2.45 seconds
Started Dec 31 12:49:26 PM PST 23
Finished Dec 31 12:49:29 PM PST 23
Peak memory 215788 kb
Host smart-7afa34b0-686a-424d-9bfd-9e51ac3c3ebb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508570168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1508570168
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3419647183
Short name T416
Test name
Test status
Simulation time 16277227 ps
CPU time 0.77 seconds
Started Dec 31 12:49:29 PM PST 23
Finished Dec 31 12:49:31 PM PST 23
Peak memory 204876 kb
Host smart-d1708008-7f04-4f2c-aedb-21d21219edf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419647183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3419647183
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2815027737
Short name T412
Test name
Test status
Simulation time 311985359 ps
CPU time 4.32 seconds
Started Dec 31 12:48:46 PM PST 23
Finished Dec 31 12:48:51 PM PST 23
Peak memory 215644 kb
Host smart-09b07f3f-176b-47ec-9c86-f1f06cf02622
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815027737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2815027737
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3203708582
Short name T110
Test name
Test status
Simulation time 254654934 ps
CPU time 2.06 seconds
Started Dec 31 12:49:21 PM PST 23
Finished Dec 31 12:49:24 PM PST 23
Peak memory 215884 kb
Host smart-8dfc1aba-0369-47fa-94bc-589f5e66130b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203708582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3203708582
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1408331828
Short name T201
Test name
Test status
Simulation time 857229255 ps
CPU time 13.1 seconds
Started Dec 31 12:49:40 PM PST 23
Finished Dec 31 12:49:54 PM PST 23
Peak memory 215704 kb
Host smart-b0cc8c0c-0b2f-4e07-b59f-8d60fe4c5e39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408331828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1408331828
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2845970148
Short name T354
Test name
Test status
Simulation time 89568527 ps
CPU time 1.98 seconds
Started Dec 31 12:49:21 PM PST 23
Finished Dec 31 12:49:24 PM PST 23
Peak memory 218200 kb
Host smart-3924fcbd-c21f-4071-93fb-de5f622548af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845970148 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2845970148
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.408538576
Short name T367
Test name
Test status
Simulation time 464029100 ps
CPU time 2.72 seconds
Started Dec 31 12:49:24 PM PST 23
Finished Dec 31 12:49:28 PM PST 23
Peak memory 207532 kb
Host smart-a5fee462-2d4c-4d2b-b2ae-5f7e426c77bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408538576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.408538576
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3874371859
Short name T442
Test name
Test status
Simulation time 11489698 ps
CPU time 0.7 seconds
Started Dec 31 12:49:36 PM PST 23
Finished Dec 31 12:49:38 PM PST 23
Peak memory 204920 kb
Host smart-05b096a1-b9a3-4046-b584-cc7442ecccb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874371859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3874371859
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.174565651
Short name T169
Test name
Test status
Simulation time 54574427 ps
CPU time 1.76 seconds
Started Dec 31 12:49:28 PM PST 23
Finished Dec 31 12:49:32 PM PST 23
Peak memory 215720 kb
Host smart-313b6c0b-3e22-4c7e-be1e-62b98ffd7f45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174565651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.174565651
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3379462878
Short name T109
Test name
Test status
Simulation time 85509831 ps
CPU time 2.52 seconds
Started Dec 31 12:49:15 PM PST 23
Finished Dec 31 12:49:19 PM PST 23
Peak memory 215904 kb
Host smart-2dbeb4f9-c3e1-42aa-9864-40820c96873d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379462878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3379462878
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1679497781
Short name T197
Test name
Test status
Simulation time 1965259656 ps
CPU time 20.66 seconds
Started Dec 31 12:49:23 PM PST 23
Finished Dec 31 12:49:45 PM PST 23
Peak memory 215656 kb
Host smart-0debdbe8-74da-4a1f-8eea-bff8895b1638
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679497781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1679497781
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2812086636
Short name T444
Test name
Test status
Simulation time 23338180 ps
CPU time 2.14 seconds
Started Dec 31 12:49:36 PM PST 23
Finished Dec 31 12:49:44 PM PST 23
Peak memory 218372 kb
Host smart-ebbfecb7-7488-4b7d-892d-d97c7d165892
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812086636 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2812086636
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3766482769
Short name T126
Test name
Test status
Simulation time 92041906 ps
CPU time 1.78 seconds
Started Dec 31 12:49:15 PM PST 23
Finished Dec 31 12:49:18 PM PST 23
Peak memory 215788 kb
Host smart-f93ccbd4-05e1-4502-9bb0-7cc893dc8505
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766482769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3766482769
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1267508888
Short name T434
Test name
Test status
Simulation time 20424818 ps
CPU time 0.7 seconds
Started Dec 31 12:49:08 PM PST 23
Finished Dec 31 12:49:10 PM PST 23
Peak memory 204848 kb
Host smart-6f415264-1556-41e6-86fd-ea25e6f99eb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267508888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1267508888
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2487807757
Short name T400
Test name
Test status
Simulation time 382024352 ps
CPU time 3.92 seconds
Started Dec 31 12:49:33 PM PST 23
Finished Dec 31 12:49:37 PM PST 23
Peak memory 215632 kb
Host smart-3e529070-9bd9-41b9-9458-bba3e43697c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487807757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2487807757
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1327169233
Short name T418
Test name
Test status
Simulation time 165540189 ps
CPU time 4 seconds
Started Dec 31 12:49:20 PM PST 23
Finished Dec 31 12:49:26 PM PST 23
Peak memory 215908 kb
Host smart-8dc8a4f9-fff0-4fa0-ad5b-a663075dbb41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327169233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1327169233
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2133390489
Short name T160
Test name
Test status
Simulation time 750521162 ps
CPU time 15.76 seconds
Started Dec 31 12:49:01 PM PST 23
Finished Dec 31 12:49:18 PM PST 23
Peak memory 215708 kb
Host smart-9c1a8a95-945b-411a-a772-38e76998c81c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133390489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2133390489
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.588040379
Short name T159
Test name
Test status
Simulation time 46050274 ps
CPU time 2.28 seconds
Started Dec 31 12:49:14 PM PST 23
Finished Dec 31 12:49:17 PM PST 23
Peak memory 219556 kb
Host smart-838c52d7-7a44-41a5-8509-2f5d8790a44d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588040379 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.588040379
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2298901439
Short name T415
Test name
Test status
Simulation time 134667526 ps
CPU time 2.35 seconds
Started Dec 31 12:48:59 PM PST 23
Finished Dec 31 12:49:02 PM PST 23
Peak memory 215796 kb
Host smart-34e3ee58-1146-4901-a777-dfd68e755b5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298901439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2298901439
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.89390614
Short name T443
Test name
Test status
Simulation time 75581289 ps
CPU time 0.73 seconds
Started Dec 31 12:49:15 PM PST 23
Finished Dec 31 12:49:17 PM PST 23
Peak memory 204856 kb
Host smart-3d003e3f-f75e-4ecd-b560-67a184f532bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89390614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.89390614
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.510194544
Short name T371
Test name
Test status
Simulation time 930892234 ps
CPU time 3.3 seconds
Started Dec 31 12:49:02 PM PST 23
Finished Dec 31 12:49:07 PM PST 23
Peak memory 215736 kb
Host smart-53792e93-0e2b-46f3-828c-ff70a13f8d99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510194544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.510194544
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3555110484
Short name T131
Test name
Test status
Simulation time 66247464 ps
CPU time 2.26 seconds
Started Dec 31 12:49:21 PM PST 23
Finished Dec 31 12:49:30 PM PST 23
Peak memory 215900 kb
Host smart-aa111471-abd4-44a4-bf1f-20b42dd2b4b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555110484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3555110484
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.929065390
Short name T409
Test name
Test status
Simulation time 321992266 ps
CPU time 19.39 seconds
Started Dec 31 12:49:27 PM PST 23
Finished Dec 31 12:49:48 PM PST 23
Peak memory 215796 kb
Host smart-eb20443b-930b-47b3-a57a-86d940826319
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929065390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.929065390
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2083993557
Short name T377
Test name
Test status
Simulation time 13559245447 ps
CPU time 28.22 seconds
Started Dec 31 12:48:53 PM PST 23
Finished Dec 31 12:49:23 PM PST 23
Peak memory 215832 kb
Host smart-da2af036-72d2-4484-9e84-04fb61beb4ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083993557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2083993557
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1267137676
Short name T127
Test name
Test status
Simulation time 2311137969 ps
CPU time 35.09 seconds
Started Dec 31 12:49:27 PM PST 23
Finished Dec 31 12:50:04 PM PST 23
Peak memory 207580 kb
Host smart-6bd9ded4-44ff-496c-9b6b-f0564d80852b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267137676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1267137676
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2753441695
Short name T431
Test name
Test status
Simulation time 23879795 ps
CPU time 0.99 seconds
Started Dec 31 12:49:04 PM PST 23
Finished Dec 31 12:49:06 PM PST 23
Peak memory 207468 kb
Host smart-9bdbf335-918e-417e-92e9-0e5749f3b33a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753441695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2753441695
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1210614485
Short name T161
Test name
Test status
Simulation time 87389538 ps
CPU time 1.39 seconds
Started Dec 31 12:48:55 PM PST 23
Finished Dec 31 12:48:58 PM PST 23
Peak memory 217244 kb
Host smart-12c33ca9-7823-400b-b797-dff2da44c1cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210614485 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1210614485
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.855020486
Short name T380
Test name
Test status
Simulation time 33883153 ps
CPU time 1.24 seconds
Started Dec 31 12:49:03 PM PST 23
Finished Dec 31 12:49:05 PM PST 23
Peak memory 215780 kb
Host smart-908aa658-09c6-4539-a70e-b2e9ff19963a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855020486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.855020486
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.973774540
Short name T357
Test name
Test status
Simulation time 10762225 ps
CPU time 0.72 seconds
Started Dec 31 12:49:01 PM PST 23
Finished Dec 31 12:49:02 PM PST 23
Peak memory 204868 kb
Host smart-cdd1f79d-d61b-4d9e-89e8-64f18a2453ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973774540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.973774540
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.208530473
Short name T139
Test name
Test status
Simulation time 139280379 ps
CPU time 4.81 seconds
Started Dec 31 12:49:17 PM PST 23
Finished Dec 31 12:49:23 PM PST 23
Peak memory 215800 kb
Host smart-d1fd6e60-e68d-4735-a3a8-c4b9502a85a8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208530473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.208530473
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1505288858
Short name T339
Test name
Test status
Simulation time 685923946 ps
CPU time 11.01 seconds
Started Dec 31 12:49:13 PM PST 23
Finished Dec 31 12:49:25 PM PST 23
Peak memory 215716 kb
Host smart-caf01086-3cfb-408c-b60a-212e8ab0c78f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505288858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1505288858
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2402336298
Short name T61
Test name
Test status
Simulation time 292790723 ps
CPU time 3.34 seconds
Started Dec 31 12:48:58 PM PST 23
Finished Dec 31 12:49:02 PM PST 23
Peak memory 215780 kb
Host smart-df0665b3-544a-4cf6-a757-8942f88aae44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402336298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2402336298
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3791219802
Short name T361
Test name
Test status
Simulation time 104882369 ps
CPU time 3.81 seconds
Started Dec 31 12:49:01 PM PST 23
Finished Dec 31 12:49:06 PM PST 23
Peak memory 215888 kb
Host smart-fa84cc2d-b873-418a-9870-da3dedaa8341
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791219802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
791219802
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2210089200
Short name T391
Test name
Test status
Simulation time 18125082 ps
CPU time 0.78 seconds
Started Dec 31 12:49:20 PM PST 23
Finished Dec 31 12:49:22 PM PST 23
Peak memory 204932 kb
Host smart-aba7ac8a-18ce-43d2-90e0-c030401e7107
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210089200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2210089200
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.773149894
Short name T170
Test name
Test status
Simulation time 16316130 ps
CPU time 0.7 seconds
Started Dec 31 12:49:14 PM PST 23
Finished Dec 31 12:49:16 PM PST 23
Peak memory 204900 kb
Host smart-7d095721-64d1-4d1a-b2c0-4c8a93a1946d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773149894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.773149894
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.423669673
Short name T439
Test name
Test status
Simulation time 15938851 ps
CPU time 0.73 seconds
Started Dec 31 12:49:48 PM PST 23
Finished Dec 31 12:49:50 PM PST 23
Peak memory 204904 kb
Host smart-1f21ef3e-6755-4e73-9343-2c9c38d5a0aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423669673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.423669673
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.59276291
Short name T338
Test name
Test status
Simulation time 17542807 ps
CPU time 0.76 seconds
Started Dec 31 12:49:21 PM PST 23
Finished Dec 31 12:49:24 PM PST 23
Peak memory 204888 kb
Host smart-c1a6b183-10b3-408f-b09f-95eefa9f52b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59276291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.59276291
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2417734105
Short name T399
Test name
Test status
Simulation time 26869501 ps
CPU time 0.74 seconds
Started Dec 31 12:49:38 PM PST 23
Finished Dec 31 12:49:40 PM PST 23
Peak memory 204904 kb
Host smart-7fa5b6b3-448d-46af-bcdd-880dadd33a31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417734105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2417734105
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1714336444
Short name T353
Test name
Test status
Simulation time 28856992 ps
CPU time 0.72 seconds
Started Dec 31 12:49:33 PM PST 23
Finished Dec 31 12:49:36 PM PST 23
Peak memory 204932 kb
Host smart-ffbeb8f5-f75f-4517-a27c-0fa73cbfbb80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714336444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1714336444
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4086034643
Short name T347
Test name
Test status
Simulation time 25353831 ps
CPU time 0.72 seconds
Started Dec 31 12:49:25 PM PST 23
Finished Dec 31 12:49:27 PM PST 23
Peak memory 204888 kb
Host smart-f829fa30-c6fb-4758-9ea2-d7151d0e24d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086034643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
4086034643
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1107869983
Short name T425
Test name
Test status
Simulation time 34337966 ps
CPU time 0.68 seconds
Started Dec 31 12:49:17 PM PST 23
Finished Dec 31 12:49:19 PM PST 23
Peak memory 204900 kb
Host smart-5a52d39a-7ba4-4e17-af08-2ec3eb99eb49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107869983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1107869983
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2445728480
Short name T368
Test name
Test status
Simulation time 16447278 ps
CPU time 0.75 seconds
Started Dec 31 12:49:18 PM PST 23
Finished Dec 31 12:49:20 PM PST 23
Peak memory 204932 kb
Host smart-a089e873-309d-4c64-83f8-a7d0093a7bdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445728480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2445728480
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.440052235
Short name T166
Test name
Test status
Simulation time 29099425 ps
CPU time 0.75 seconds
Started Dec 31 12:49:09 PM PST 23
Finished Dec 31 12:49:11 PM PST 23
Peak memory 204816 kb
Host smart-197fdc4d-b901-477e-9c59-2a14ecb81b88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440052235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.440052235
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3466765533
Short name T146
Test name
Test status
Simulation time 518175637 ps
CPU time 16.73 seconds
Started Dec 31 12:48:53 PM PST 23
Finished Dec 31 12:49:10 PM PST 23
Peak memory 207560 kb
Host smart-99dc31e2-696f-44d8-8ce2-7b0f69a96eae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466765533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3466765533
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3343742125
Short name T406
Test name
Test status
Simulation time 870888604 ps
CPU time 13.12 seconds
Started Dec 31 12:48:43 PM PST 23
Finished Dec 31 12:48:58 PM PST 23
Peak memory 215652 kb
Host smart-dfd79db3-dda5-44c4-9322-3d9ebfec5901
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343742125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3343742125
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2706433073
Short name T117
Test name
Test status
Simulation time 14781136 ps
CPU time 0.97 seconds
Started Dec 31 12:48:49 PM PST 23
Finished Dec 31 12:48:51 PM PST 23
Peak memory 207356 kb
Host smart-d3ab3e5c-50f7-4b40-8c0d-93bf38a216c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706433073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2706433073
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3218246788
Short name T337
Test name
Test status
Simulation time 39971162 ps
CPU time 2.39 seconds
Started Dec 31 12:49:24 PM PST 23
Finished Dec 31 12:49:28 PM PST 23
Peak memory 218272 kb
Host smart-70f29dd6-d4e0-4412-bcb0-134e76585dfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218246788 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3218246788
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.960984307
Short name T426
Test name
Test status
Simulation time 27834912 ps
CPU time 1.77 seconds
Started Dec 31 12:48:56 PM PST 23
Finished Dec 31 12:48:58 PM PST 23
Peak memory 207592 kb
Host smart-49a4e00c-2e04-44e6-955b-9b4c4fd4981a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960984307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.960984307
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3393358925
Short name T414
Test name
Test status
Simulation time 19175212 ps
CPU time 0.76 seconds
Started Dec 31 12:48:57 PM PST 23
Finished Dec 31 12:48:59 PM PST 23
Peak memory 204820 kb
Host smart-60827aba-8c25-43d3-8a93-d5b58c141e49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393358925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
393358925
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.149691756
Short name T365
Test name
Test status
Simulation time 102502144 ps
CPU time 3.79 seconds
Started Dec 31 12:49:12 PM PST 23
Finished Dec 31 12:49:16 PM PST 23
Peak memory 215776 kb
Host smart-959e464d-ebb9-44b0-9860-a1914a0f3258
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149691756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.149691756
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3347993391
Short name T342
Test name
Test status
Simulation time 856566936 ps
CPU time 9.42 seconds
Started Dec 31 12:49:02 PM PST 23
Finished Dec 31 12:49:12 PM PST 23
Peak memory 215952 kb
Host smart-e59ebb21-697c-4327-8490-0c9fc0ffd33f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347993391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3347993391
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.369305383
Short name T383
Test name
Test status
Simulation time 994341536 ps
CPU time 4.39 seconds
Started Dec 31 12:48:57 PM PST 23
Finished Dec 31 12:49:07 PM PST 23
Peak memory 215812 kb
Host smart-daf6f5c8-4a22-473e-8bf5-fcfc49695d9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369305383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.369305383
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.232592557
Short name T356
Test name
Test status
Simulation time 145715825 ps
CPU time 5.11 seconds
Started Dec 31 12:49:10 PM PST 23
Finished Dec 31 12:49:16 PM PST 23
Peak memory 216008 kb
Host smart-4fb7083e-39ec-4dcc-9c4c-b245fd21e882
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232592557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.232592557
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1189101970
Short name T72
Test name
Test status
Simulation time 1153703668 ps
CPU time 12.53 seconds
Started Dec 31 12:48:52 PM PST 23
Finished Dec 31 12:49:10 PM PST 23
Peak memory 215860 kb
Host smart-146aca40-7826-4e19-b668-b9ca345d1c83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189101970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1189101970
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3184094398
Short name T395
Test name
Test status
Simulation time 27140864 ps
CPU time 0.72 seconds
Started Dec 31 12:49:44 PM PST 23
Finished Dec 31 12:49:45 PM PST 23
Peak memory 204892 kb
Host smart-402ec78c-3452-4618-b6db-9c9420ceefa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184094398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3184094398
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.549746739
Short name T428
Test name
Test status
Simulation time 21322929 ps
CPU time 0.69 seconds
Started Dec 31 12:49:19 PM PST 23
Finished Dec 31 12:49:22 PM PST 23
Peak memory 204908 kb
Host smart-bbc3d3f8-afc7-4320-9653-db7d6f94e1b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549746739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.549746739
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.180505277
Short name T57
Test name
Test status
Simulation time 43866414 ps
CPU time 0.72 seconds
Started Dec 31 12:49:15 PM PST 23
Finished Dec 31 12:49:18 PM PST 23
Peak memory 204876 kb
Host smart-f556f66f-9957-4936-9593-d2cb7e962a09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180505277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.180505277
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1552214530
Short name T382
Test name
Test status
Simulation time 56263507 ps
CPU time 0.73 seconds
Started Dec 31 12:49:16 PM PST 23
Finished Dec 31 12:49:18 PM PST 23
Peak memory 204848 kb
Host smart-7c6a3186-8094-43a8-9b26-b98dada270cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552214530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1552214530
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1014114642
Short name T433
Test name
Test status
Simulation time 22095516 ps
CPU time 0.7 seconds
Started Dec 31 12:49:07 PM PST 23
Finished Dec 31 12:49:09 PM PST 23
Peak memory 204844 kb
Host smart-464e741c-6721-4429-a379-afb7ff169a32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014114642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1014114642
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2279510928
Short name T396
Test name
Test status
Simulation time 12793996 ps
CPU time 0.71 seconds
Started Dec 31 12:49:02 PM PST 23
Finished Dec 31 12:49:03 PM PST 23
Peak memory 204840 kb
Host smart-adab3f75-51ca-443c-9783-e1e1533756b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279510928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2279510928
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1016897984
Short name T188
Test name
Test status
Simulation time 50210653 ps
CPU time 0.7 seconds
Started Dec 31 12:49:17 PM PST 23
Finished Dec 31 12:49:19 PM PST 23
Peak memory 204888 kb
Host smart-c4664fe7-fee7-4d67-ae82-31f9c4b502b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016897984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1016897984
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.387510196
Short name T376
Test name
Test status
Simulation time 10984838 ps
CPU time 0.69 seconds
Started Dec 31 12:48:51 PM PST 23
Finished Dec 31 12:48:52 PM PST 23
Peak memory 204840 kb
Host smart-a6ebaa78-3295-4d09-832a-c40808b120d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387510196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.387510196
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3299031234
Short name T144
Test name
Test status
Simulation time 433973285 ps
CPU time 8.84 seconds
Started Dec 31 12:49:30 PM PST 23
Finished Dec 31 12:49:40 PM PST 23
Peak memory 216764 kb
Host smart-7cf35c7c-d0d1-44b9-8475-59d12d5ccd35
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299031234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3299031234
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1478954015
Short name T427
Test name
Test status
Simulation time 8313927277 ps
CPU time 38.96 seconds
Started Dec 31 12:49:06 PM PST 23
Finished Dec 31 12:49:46 PM PST 23
Peak memory 217128 kb
Host smart-ccc5ef53-ab20-4ff5-822c-a5863593cf4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478954015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1478954015
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3512467649
Short name T373
Test name
Test status
Simulation time 188732782 ps
CPU time 1.45 seconds
Started Dec 31 12:49:22 PM PST 23
Finished Dec 31 12:49:26 PM PST 23
Peak memory 215716 kb
Host smart-53d674de-8a6b-4b59-a028-56227d2d1da8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512467649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3512467649
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1973909833
Short name T378
Test name
Test status
Simulation time 189358009 ps
CPU time 1.4 seconds
Started Dec 31 12:49:31 PM PST 23
Finished Dec 31 12:49:33 PM PST 23
Peak memory 215732 kb
Host smart-66ba85d4-d7a7-424d-8479-2361d60d3e89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973909833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
973909833
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.735003621
Short name T381
Test name
Test status
Simulation time 74470244 ps
CPU time 0.68 seconds
Started Dec 31 12:49:24 PM PST 23
Finished Dec 31 12:49:26 PM PST 23
Peak memory 204816 kb
Host smart-fddbf553-19c1-4407-910a-ddad5edf8ec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735003621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.735003621
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1029320141
Short name T374
Test name
Test status
Simulation time 334656629 ps
CPU time 4.73 seconds
Started Dec 31 12:49:39 PM PST 23
Finished Dec 31 12:49:45 PM PST 23
Peak memory 215828 kb
Host smart-e9b2a64c-2394-4b53-8832-d3e20dba26a3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029320141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1029320141
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3648256891
Short name T389
Test name
Test status
Simulation time 542585079 ps
CPU time 9.1 seconds
Started Dec 31 12:48:58 PM PST 23
Finished Dec 31 12:49:08 PM PST 23
Peak memory 215780 kb
Host smart-23154334-824f-4ce3-9865-28599e820397
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648256891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3648256891
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1844831589
Short name T360
Test name
Test status
Simulation time 105022949 ps
CPU time 2.02 seconds
Started Dec 31 12:49:08 PM PST 23
Finished Dec 31 12:49:11 PM PST 23
Peak memory 215740 kb
Host smart-367087db-49e4-44fd-9fca-873310fca433
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844831589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1844831589
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.27270974
Short name T419
Test name
Test status
Simulation time 16442351 ps
CPU time 0.73 seconds
Started Dec 31 12:49:19 PM PST 23
Finished Dec 31 12:49:22 PM PST 23
Peak memory 204852 kb
Host smart-d2b5d961-a5e4-405e-8703-ba0998ca30e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27270974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.27270974
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1912972522
Short name T387
Test name
Test status
Simulation time 51311837 ps
CPU time 0.68 seconds
Started Dec 31 12:49:04 PM PST 23
Finished Dec 31 12:49:05 PM PST 23
Peak memory 204936 kb
Host smart-ece49d87-b181-4952-b863-fd087d7bffc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912972522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1912972522
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1348440464
Short name T345
Test name
Test status
Simulation time 16228348 ps
CPU time 0.78 seconds
Started Dec 31 12:49:07 PM PST 23
Finished Dec 31 12:49:09 PM PST 23
Peak memory 204856 kb
Host smart-f5c750f6-feba-450f-a084-728019b4a1e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348440464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1348440464
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2568377520
Short name T397
Test name
Test status
Simulation time 74018762 ps
CPU time 0.74 seconds
Started Dec 31 12:49:16 PM PST 23
Finished Dec 31 12:49:18 PM PST 23
Peak memory 204836 kb
Host smart-2767f378-3b65-4664-9c37-1c143f809897
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568377520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2568377520
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2176867611
Short name T58
Test name
Test status
Simulation time 16420780 ps
CPU time 0.68 seconds
Started Dec 31 12:49:48 PM PST 23
Finished Dec 31 12:49:49 PM PST 23
Peak memory 204808 kb
Host smart-60ffa7c8-f600-43f3-9766-d0f7fb376c16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176867611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2176867611
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2211333226
Short name T172
Test name
Test status
Simulation time 45798249 ps
CPU time 0.73 seconds
Started Dec 31 12:49:13 PM PST 23
Finished Dec 31 12:49:15 PM PST 23
Peak memory 204848 kb
Host smart-6f7abb58-7e0d-467b-9060-46cf0e05be6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211333226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2211333226
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2832378736
Short name T340
Test name
Test status
Simulation time 84172616 ps
CPU time 0.73 seconds
Started Dec 31 12:48:58 PM PST 23
Finished Dec 31 12:49:00 PM PST 23
Peak memory 204860 kb
Host smart-3add035a-c20e-4f09-8057-302d4697e3d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832378736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2832378736
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2801802467
Short name T187
Test name
Test status
Simulation time 13637404 ps
CPU time 0.69 seconds
Started Dec 31 12:49:20 PM PST 23
Finished Dec 31 12:49:22 PM PST 23
Peak memory 204840 kb
Host smart-d99bf7a4-6e54-45bc-8af2-12fcd927d61c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801802467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2801802467
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2283568299
Short name T394
Test name
Test status
Simulation time 14784757 ps
CPU time 0.68 seconds
Started Dec 31 12:49:21 PM PST 23
Finished Dec 31 12:49:23 PM PST 23
Peak memory 204892 kb
Host smart-b9aeee91-790e-4beb-95f0-da3bd0cd77f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283568299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2283568299
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3324104200
Short name T411
Test name
Test status
Simulation time 27595361 ps
CPU time 0.69 seconds
Started Dec 31 12:49:24 PM PST 23
Finished Dec 31 12:49:26 PM PST 23
Peak memory 204864 kb
Host smart-dad9f647-1141-450a-907f-8c6ed59e6241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324104200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3324104200
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1516288827
Short name T167
Test name
Test status
Simulation time 110752168 ps
CPU time 2.24 seconds
Started Dec 31 12:49:00 PM PST 23
Finished Dec 31 12:49:03 PM PST 23
Peak memory 218308 kb
Host smart-f3ddc33e-a502-414f-88f6-6e0ff1eb75f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516288827 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1516288827
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3363982033
Short name T164
Test name
Test status
Simulation time 830364135 ps
CPU time 1.77 seconds
Started Dec 31 12:49:04 PM PST 23
Finished Dec 31 12:49:07 PM PST 23
Peak memory 215660 kb
Host smart-1d893e82-7780-412d-9b65-05c3f6e3c6de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363982033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
363982033
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.888167030
Short name T352
Test name
Test status
Simulation time 14634973 ps
CPU time 0.71 seconds
Started Dec 31 12:49:25 PM PST 23
Finished Dec 31 12:49:27 PM PST 23
Peak memory 204804 kb
Host smart-4a9a9a86-e544-4257-9805-2574c9fe3141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888167030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.888167030
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1336871637
Short name T384
Test name
Test status
Simulation time 63304844 ps
CPU time 1.74 seconds
Started Dec 31 12:49:29 PM PST 23
Finished Dec 31 12:49:32 PM PST 23
Peak memory 215712 kb
Host smart-52c61e1e-1d38-4e21-b004-619e8fa03510
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336871637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1336871637
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.268520456
Short name T113
Test name
Test status
Simulation time 134117871 ps
CPU time 3.89 seconds
Started Dec 31 12:49:21 PM PST 23
Finished Dec 31 12:49:27 PM PST 23
Peak memory 215940 kb
Host smart-1e1586c1-bc4f-4486-934d-a1f2b17c755d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268520456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.268520456
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1784453770
Short name T413
Test name
Test status
Simulation time 1087438009 ps
CPU time 7.67 seconds
Started Dec 31 12:49:25 PM PST 23
Finished Dec 31 12:49:38 PM PST 23
Peak memory 215796 kb
Host smart-0bd7369e-cc07-443b-b9b6-1da9c8c42c83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784453770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1784453770
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2266602986
Short name T108
Test name
Test status
Simulation time 195431550 ps
CPU time 2.57 seconds
Started Dec 31 12:49:01 PM PST 23
Finished Dec 31 12:49:04 PM PST 23
Peak memory 217652 kb
Host smart-36b33231-0f6b-4879-aba0-f9184bb14f71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266602986 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2266602986
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.446936160
Short name T142
Test name
Test status
Simulation time 499429174 ps
CPU time 2.94 seconds
Started Dec 31 12:49:41 PM PST 23
Finished Dec 31 12:49:45 PM PST 23
Peak memory 215752 kb
Host smart-244922d7-aed3-4d91-aaa2-5a968d38d949
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446936160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.446936160
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2254996637
Short name T350
Test name
Test status
Simulation time 43272080 ps
CPU time 0.75 seconds
Started Dec 31 12:49:46 PM PST 23
Finished Dec 31 12:49:48 PM PST 23
Peak memory 204908 kb
Host smart-a7995e3d-c5a6-460c-937d-b518410e1549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254996637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
254996637
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1982926651
Short name T128
Test name
Test status
Simulation time 67809370 ps
CPU time 2.08 seconds
Started Dec 31 12:48:49 PM PST 23
Finished Dec 31 12:48:52 PM PST 23
Peak memory 215804 kb
Host smart-f16d2037-48a7-42d8-b4f3-35635ea7f7e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982926651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1982926651
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.344321761
Short name T401
Test name
Test status
Simulation time 276506832 ps
CPU time 5.81 seconds
Started Dec 31 12:49:38 PM PST 23
Finished Dec 31 12:49:45 PM PST 23
Peak memory 215896 kb
Host smart-0e02bd94-6b6d-431f-8042-b9a8f1c3c3cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344321761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.344321761
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1358129087
Short name T132
Test name
Test status
Simulation time 502654804 ps
CPU time 7.13 seconds
Started Dec 31 12:49:26 PM PST 23
Finished Dec 31 12:49:34 PM PST 23
Peak memory 215608 kb
Host smart-7c8d638b-17a9-42b9-b2a4-ede1ec400838
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358129087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1358129087
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1458871861
Short name T351
Test name
Test status
Simulation time 41042766 ps
CPU time 2.59 seconds
Started Dec 31 12:48:45 PM PST 23
Finished Dec 31 12:48:49 PM PST 23
Peak memory 218412 kb
Host smart-4bf48129-db37-4731-a884-91ae82440374
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458871861 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1458871861
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1464235707
Short name T343
Test name
Test status
Simulation time 43124699 ps
CPU time 2.45 seconds
Started Dec 31 12:48:51 PM PST 23
Finished Dec 31 12:48:54 PM PST 23
Peak memory 215796 kb
Host smart-e23550c8-e981-4f69-ae23-182061560a68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464235707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
464235707
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2438026596
Short name T363
Test name
Test status
Simulation time 19517490 ps
CPU time 0.71 seconds
Started Dec 31 12:49:21 PM PST 23
Finished Dec 31 12:49:22 PM PST 23
Peak memory 204896 kb
Host smart-e8a7736d-ff7e-4198-badc-b8a546f27a0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438026596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
438026596
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2626513893
Short name T162
Test name
Test status
Simulation time 174934312 ps
CPU time 3.4 seconds
Started Dec 31 12:48:47 PM PST 23
Finished Dec 31 12:48:52 PM PST 23
Peak memory 215752 kb
Host smart-55cf74a2-320c-447e-9f41-eea65b45cda8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626513893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2626513893
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3999119948
Short name T429
Test name
Test status
Simulation time 241857978 ps
CPU time 1.76 seconds
Started Dec 31 12:48:56 PM PST 23
Finished Dec 31 12:48:59 PM PST 23
Peak memory 215944 kb
Host smart-0951fe10-46a7-4934-9382-a58d470a5bf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999119948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
999119948
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3402620
Short name T402
Test name
Test status
Simulation time 213069944 ps
CPU time 6.47 seconds
Started Dec 31 12:49:08 PM PST 23
Finished Dec 31 12:49:16 PM PST 23
Peak memory 215832 kb
Host smart-1303ed95-bb24-4b6d-9876-b3ed29f08f2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl
_intg_err.3402620
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1916099983
Short name T56
Test name
Test status
Simulation time 223398453 ps
CPU time 2.34 seconds
Started Dec 31 12:49:12 PM PST 23
Finished Dec 31 12:49:16 PM PST 23
Peak memory 219656 kb
Host smart-e5d2458a-a9df-480c-997d-3fdf9cba081b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916099983 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1916099983
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3237921824
Short name T424
Test name
Test status
Simulation time 82570670 ps
CPU time 2.1 seconds
Started Dec 31 12:49:13 PM PST 23
Finished Dec 31 12:49:16 PM PST 23
Peak memory 215768 kb
Host smart-e75923bf-7739-4ed8-a99c-38f03446bf3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237921824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
237921824
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1870248359
Short name T375
Test name
Test status
Simulation time 15859657 ps
CPU time 0.7 seconds
Started Dec 31 12:48:52 PM PST 23
Finished Dec 31 12:48:54 PM PST 23
Peak memory 204872 kb
Host smart-b7309373-ead7-47bc-82c4-a6fb059487c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870248359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
870248359
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2412223194
Short name T390
Test name
Test status
Simulation time 464446427 ps
CPU time 1.88 seconds
Started Dec 31 12:48:55 PM PST 23
Finished Dec 31 12:48:58 PM PST 23
Peak memory 215692 kb
Host smart-2bc71eaf-2c84-4a92-a33c-738596a41408
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412223194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2412223194
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1157623294
Short name T359
Test name
Test status
Simulation time 138684742 ps
CPU time 3.9 seconds
Started Dec 31 12:49:33 PM PST 23
Finished Dec 31 12:49:40 PM PST 23
Peak memory 215888 kb
Host smart-3617145d-45ea-44fb-9c70-292e2f364802
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157623294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
157623294
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1723833242
Short name T358
Test name
Test status
Simulation time 122708729 ps
CPU time 7.31 seconds
Started Dec 31 12:48:57 PM PST 23
Finished Dec 31 12:49:05 PM PST 23
Peak memory 217620 kb
Host smart-a9fadc0b-1ab0-45e7-a5ce-62f68652d965
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723833242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1723833242
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3510659489
Short name T158
Test name
Test status
Simulation time 165242485 ps
CPU time 2.19 seconds
Started Dec 31 12:49:28 PM PST 23
Finished Dec 31 12:49:31 PM PST 23
Peak memory 217072 kb
Host smart-6eb1e6b5-e2f0-4512-ac93-f336dc609f15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510659489 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3510659489
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1558328940
Short name T145
Test name
Test status
Simulation time 101200238 ps
CPU time 2.73 seconds
Started Dec 31 12:49:15 PM PST 23
Finished Dec 31 12:49:20 PM PST 23
Peak memory 215696 kb
Host smart-1f6414a1-d2dc-4f7f-9b46-4956259b24de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558328940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
558328940
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2246005756
Short name T186
Test name
Test status
Simulation time 122361972 ps
CPU time 0.8 seconds
Started Dec 31 12:49:17 PM PST 23
Finished Dec 31 12:49:19 PM PST 23
Peak memory 204780 kb
Host smart-0c423c3c-e434-461f-a28b-3368b67e19f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246005756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
246005756
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.633679520
Short name T398
Test name
Test status
Simulation time 947719917 ps
CPU time 4.36 seconds
Started Dec 31 12:48:51 PM PST 23
Finished Dec 31 12:48:57 PM PST 23
Peak memory 215804 kb
Host smart-a87a98ea-465a-4a0b-9f09-2b60cfe49927
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633679520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.633679520
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2250390387
Short name T116
Test name
Test status
Simulation time 762004941 ps
CPU time 3.35 seconds
Started Dec 31 12:49:25 PM PST 23
Finished Dec 31 12:49:29 PM PST 23
Peak memory 215944 kb
Host smart-a3d95852-1d48-4f76-9179-fdf19c9dcca6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250390387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
250390387
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.330339649
Short name T198
Test name
Test status
Simulation time 359993134 ps
CPU time 20.34 seconds
Started Dec 31 12:49:19 PM PST 23
Finished Dec 31 12:49:41 PM PST 23
Peak memory 215704 kb
Host smart-97d14de1-ddae-42d6-a53d-7c18cfd0393f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330339649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.330339649
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_abort.1562039373
Short name T685
Test name
Test status
Simulation time 17514893 ps
CPU time 0.76 seconds
Started Dec 31 01:07:30 PM PST 23
Finished Dec 31 01:07:31 PM PST 23
Peak memory 206552 kb
Host smart-910e5e2b-7d7a-422c-8830-4cc141e53a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562039373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_abort.1562039373
Directory /workspace/0.spi_device_abort/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1389905829
Short name T88
Test name
Test status
Simulation time 24286963 ps
CPU time 0.75 seconds
Started Dec 31 01:08:24 PM PST 23
Finished Dec 31 01:08:26 PM PST 23
Peak memory 206524 kb
Host smart-37d607b7-28b9-4c54-8808-bfe109b0e07d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389905829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
389905829
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_bit_transfer.2889466390
Short name T1355
Test name
Test status
Simulation time 793834550 ps
CPU time 2.55 seconds
Started Dec 31 01:07:33 PM PST 23
Finished Dec 31 01:07:38 PM PST 23
Peak memory 216748 kb
Host smart-f293ac22-7e46-4d67-b0a7-8967687e1a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889466390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_bit_transfer.2889466390
Directory /workspace/0.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/0.spi_device_byte_transfer.3747027214
Short name T991
Test name
Test status
Simulation time 737331113 ps
CPU time 2.83 seconds
Started Dec 31 01:07:30 PM PST 23
Finished Dec 31 01:07:34 PM PST 23
Peak memory 216860 kb
Host smart-16ed68b0-1712-4f5f-ab11-5aba7380be43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747027214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_byte_transfer.3747027214
Directory /workspace/0.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.731467536
Short name T1730
Test name
Test status
Simulation time 570340130 ps
CPU time 4.12 seconds
Started Dec 31 01:07:32 PM PST 23
Finished Dec 31 01:07:39 PM PST 23
Peak memory 219304 kb
Host smart-50d1bed7-2174-4602-b209-8957f862b7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731467536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.731467536
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.966573437
Short name T701
Test name
Test status
Simulation time 23158644 ps
CPU time 0.82 seconds
Started Dec 31 01:07:30 PM PST 23
Finished Dec 31 01:07:33 PM PST 23
Peak memory 207556 kb
Host smart-a5013f82-b29a-42d1-93b4-daf2a6b94556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966573437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.966573437
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_dummy_item_extra_dly.2053910582
Short name T814
Test name
Test status
Simulation time 82090063982 ps
CPU time 530.02 seconds
Started Dec 31 01:07:31 PM PST 23
Finished Dec 31 01:16:24 PM PST 23
Peak memory 319392 kb
Host smart-6ac7edec-e4ea-4e73-b0eb-0f1454a48f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053910582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_dummy_item_extra_dly.2053910582
Directory /workspace/0.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/0.spi_device_extreme_fifo_size.104711827
Short name T1172
Test name
Test status
Simulation time 76335714622 ps
CPU time 452.61 seconds
Started Dec 31 01:07:32 PM PST 23
Finished Dec 31 01:15:08 PM PST 23
Peak memory 217908 kb
Host smart-cd8854d3-1d1c-4cbc-a24b-043b572e99a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104711827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_extreme_fifo_size.104711827
Directory /workspace/0.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/0.spi_device_fifo_full.1961143507
Short name T1017
Test name
Test status
Simulation time 130231139962 ps
CPU time 1816.1 seconds
Started Dec 31 01:07:29 PM PST 23
Finished Dec 31 01:37:46 PM PST 23
Peak memory 282552 kb
Host smart-211ef0ed-96dc-43e9-93d3-44023d541e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961143507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_fifo_full.1961143507
Directory /workspace/0.spi_device_fifo_full/latest

Test location /workspace/coverage/default/0.spi_device_fifo_underflow_overflow.1329600121
Short name T39
Test name
Test status
Simulation time 24364963263 ps
CPU time 188.87 seconds
Started Dec 31 01:07:29 PM PST 23
Finished Dec 31 01:10:39 PM PST 23
Peak memory 312808 kb
Host smart-8b7ea1ea-328c-46c8-ac19-35f3e4cae0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329600121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_fifo_underflow_overfl
ow.1329600121
Directory /workspace/0.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2802603181
Short name T20
Test name
Test status
Simulation time 21062498445 ps
CPU time 39.55 seconds
Started Dec 31 01:08:04 PM PST 23
Finished Dec 31 01:08:45 PM PST 23
Peak memory 256624 kb
Host smart-ed7f6702-bd97-44f5-b8c0-7eb3c9864728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802603181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2802603181
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1393215097
Short name T1328
Test name
Test status
Simulation time 19813970440 ps
CPU time 175.67 seconds
Started Dec 31 01:08:05 PM PST 23
Finished Dec 31 01:11:03 PM PST 23
Peak memory 264800 kb
Host smart-92ef0894-2757-46e2-9c54-4368b1f82f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393215097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1393215097
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3295231576
Short name T1330
Test name
Test status
Simulation time 117837476484 ps
CPU time 165.83 seconds
Started Dec 31 01:07:49 PM PST 23
Finished Dec 31 01:10:36 PM PST 23
Peak memory 255968 kb
Host smart-eaaf6e3a-2b84-40cb-b25d-5633eddb50b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295231576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3295231576
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3017812111
Short name T934
Test name
Test status
Simulation time 447714879 ps
CPU time 21.8 seconds
Started Dec 31 01:07:33 PM PST 23
Finished Dec 31 01:07:57 PM PST 23
Peak memory 249156 kb
Host smart-0851b450-2dec-4e01-b326-2de5741a4a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017812111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3017812111
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3474724461
Short name T1049
Test name
Test status
Simulation time 227449034 ps
CPU time 3.23 seconds
Started Dec 31 01:07:31 PM PST 23
Finished Dec 31 01:07:35 PM PST 23
Peak memory 238496 kb
Host smart-632bc8e0-f964-4d26-9ba5-78030244f179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474724461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3474724461
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_intr.1954541859
Short name T861
Test name
Test status
Simulation time 125549859630 ps
CPU time 114.03 seconds
Started Dec 31 01:07:31 PM PST 23
Finished Dec 31 01:09:27 PM PST 23
Peak memory 254116 kb
Host smart-2b846918-63e8-42bf-8d32-cf2283174d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954541859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intr.1954541859
Directory /workspace/0.spi_device_intr/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3185077258
Short name T1600
Test name
Test status
Simulation time 170816016 ps
CPU time 3.53 seconds
Started Dec 31 01:07:31 PM PST 23
Finished Dec 31 01:07:35 PM PST 23
Peak memory 218924 kb
Host smart-4feea03d-ace4-4622-a3b3-dfb41d9f81f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185077258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3185077258
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3689906446
Short name T914
Test name
Test status
Simulation time 61407109 ps
CPU time 2.67 seconds
Started Dec 31 01:07:32 PM PST 23
Finished Dec 31 01:07:36 PM PST 23
Peak memory 218528 kb
Host smart-956e0c36-e501-4f5e-80e4-f7c6cd0a0bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689906446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3689906446
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.756075122
Short name T639
Test name
Test status
Simulation time 9781431870 ps
CPU time 12.31 seconds
Started Dec 31 01:07:30 PM PST 23
Finished Dec 31 01:07:44 PM PST 23
Peak memory 238392 kb
Host smart-42315604-3357-4557-abae-0ec730a34c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756075122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.756075122
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_perf.3309796698
Short name T936
Test name
Test status
Simulation time 6133231536 ps
CPU time 367.07 seconds
Started Dec 31 01:07:32 PM PST 23
Finished Dec 31 01:13:41 PM PST 23
Peak memory 248624 kb
Host smart-0dd9642b-fd1d-4dd5-8cd4-730bd81b167d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309796698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_perf.3309796698
Directory /workspace/0.spi_device_perf/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3150954386
Short name T1404
Test name
Test status
Simulation time 1852275594 ps
CPU time 8.59 seconds
Started Dec 31 01:07:30 PM PST 23
Finished Dec 31 01:07:40 PM PST 23
Peak memory 234148 kb
Host smart-c9a39404-663d-47b3-998f-73642e009ccb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3150954386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3150954386
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_rx_async_fifo_reset.1989632421
Short name T696
Test name
Test status
Simulation time 25173491 ps
CPU time 0.88 seconds
Started Dec 31 01:07:31 PM PST 23
Finished Dec 31 01:07:33 PM PST 23
Peak memory 208424 kb
Host smart-9dd36d86-2113-4c5d-bf88-d3864890e088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989632421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_rx_async_fifo_reset.1989632421
Directory /workspace/0.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/0.spi_device_rx_timeout.2942054346
Short name T989
Test name
Test status
Simulation time 2866878335 ps
CPU time 6.43 seconds
Started Dec 31 01:07:31 PM PST 23
Finished Dec 31 01:07:39 PM PST 23
Peak memory 216892 kb
Host smart-1c058cc1-d9be-436c-9865-4cfee7155c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942054346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_rx_timeout.2942054346
Directory /workspace/0.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/0.spi_device_smoke.1913930917
Short name T471
Test name
Test status
Simulation time 378214572 ps
CPU time 0.97 seconds
Started Dec 31 01:07:32 PM PST 23
Finished Dec 31 01:07:34 PM PST 23
Peak memory 207892 kb
Host smart-ff92f913-932b-4f63-86f6-d969df4bd259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913930917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_smoke.1913930917
Directory /workspace/0.spi_device_smoke/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3764149507
Short name T1255
Test name
Test status
Simulation time 6538366091 ps
CPU time 25.79 seconds
Started Dec 31 01:07:30 PM PST 23
Finished Dec 31 01:07:58 PM PST 23
Peak memory 217204 kb
Host smart-60359bf8-3a14-4b70-8316-451a52c8f166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764149507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3764149507
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.821686084
Short name T1783
Test name
Test status
Simulation time 4212699096 ps
CPU time 7.64 seconds
Started Dec 31 01:07:31 PM PST 23
Finished Dec 31 01:07:41 PM PST 23
Peak memory 216864 kb
Host smart-1cc27232-b93b-4eef-8109-697ac55442e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821686084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.821686084
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3244950062
Short name T871
Test name
Test status
Simulation time 36220985 ps
CPU time 1.23 seconds
Started Dec 31 01:07:31 PM PST 23
Finished Dec 31 01:07:34 PM PST 23
Peak memory 208404 kb
Host smart-8bee8e35-c184-4dfc-9ece-f758d64ac1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244950062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3244950062
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2495427803
Short name T1440
Test name
Test status
Simulation time 32526020 ps
CPU time 0.71 seconds
Started Dec 31 01:07:30 PM PST 23
Finished Dec 31 01:07:32 PM PST 23
Peak memory 206860 kb
Host smart-dc08cafe-1f47-4ecb-be14-7b616b58c86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495427803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2495427803
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_tx_async_fifo_reset.1851254957
Short name T1485
Test name
Test status
Simulation time 15220470 ps
CPU time 0.76 seconds
Started Dec 31 01:07:32 PM PST 23
Finished Dec 31 01:07:35 PM PST 23
Peak memory 208440 kb
Host smart-9fc27be2-f825-4607-8140-9a36d43d8a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851254957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tx_async_fifo_reset.1851254957
Directory /workspace/0.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/0.spi_device_txrx.4192388685
Short name T1750
Test name
Test status
Simulation time 51252827142 ps
CPU time 241.52 seconds
Started Dec 31 01:07:30 PM PST 23
Finished Dec 31 01:11:32 PM PST 23
Peak memory 315808 kb
Host smart-8dd7fc6a-edac-4c6e-93df-a52dcd94e5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192388685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_txrx.4192388685
Directory /workspace/0.spi_device_txrx/latest

Test location /workspace/coverage/default/0.spi_device_upload.3817252902
Short name T797
Test name
Test status
Simulation time 24789525816 ps
CPU time 27.79 seconds
Started Dec 31 01:07:32 PM PST 23
Finished Dec 31 01:08:01 PM PST 23
Peak memory 255052 kb
Host smart-fbb5b4ca-317f-4a64-9ec2-3f3308ccfbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817252902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3817252902
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_abort.3130136004
Short name T1677
Test name
Test status
Simulation time 16138824 ps
CPU time 0.77 seconds
Started Dec 31 01:07:48 PM PST 23
Finished Dec 31 01:07:50 PM PST 23
Peak memory 206540 kb
Host smart-7d77808f-c1a1-4620-b097-7cc50adae2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130136004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_abort.3130136004
Directory /workspace/1.spi_device_abort/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.307891676
Short name T864
Test name
Test status
Simulation time 24425966 ps
CPU time 0.72 seconds
Started Dec 31 01:08:31 PM PST 23
Finished Dec 31 01:08:32 PM PST 23
Peak memory 206480 kb
Host smart-fc751d10-e16a-4227-a85d-6ee1c06d0765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307891676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.307891676
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_bit_transfer.2302609526
Short name T202
Test name
Test status
Simulation time 510356244 ps
CPU time 3.03 seconds
Started Dec 31 01:07:35 PM PST 23
Finished Dec 31 01:07:39 PM PST 23
Peak memory 216812 kb
Host smart-cf294a9e-3a6e-45f5-8ab4-14bef0c5b275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302609526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_bit_transfer.2302609526
Directory /workspace/1.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/1.spi_device_byte_transfer.2485079715
Short name T470
Test name
Test status
Simulation time 733165415 ps
CPU time 3.38 seconds
Started Dec 31 01:08:25 PM PST 23
Finished Dec 31 01:08:29 PM PST 23
Peak memory 216724 kb
Host smart-b2fb2f53-3bbe-480c-bc3a-2c78d847a319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485079715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_byte_transfer.2485079715
Directory /workspace/1.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1808526515
Short name T279
Test name
Test status
Simulation time 3096423120 ps
CPU time 7.58 seconds
Started Dec 31 01:08:02 PM PST 23
Finished Dec 31 01:08:11 PM PST 23
Peak memory 222328 kb
Host smart-7b2dc146-78f5-4925-9c83-a31444b802d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808526515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1808526515
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1055065598
Short name T517
Test name
Test status
Simulation time 74639543 ps
CPU time 0.8 seconds
Started Dec 31 01:07:32 PM PST 23
Finished Dec 31 01:07:34 PM PST 23
Peak memory 207544 kb
Host smart-894fbb2c-7016-4375-8cd3-fa9601c8820a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055065598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1055065598
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_dummy_item_extra_dly.252879942
Short name T593
Test name
Test status
Simulation time 38961236728 ps
CPU time 951.27 seconds
Started Dec 31 01:08:03 PM PST 23
Finished Dec 31 01:23:56 PM PST 23
Peak memory 238440 kb
Host smart-3e28ebef-8158-4f10-a044-f19f127d33d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252879942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_dummy_item_extra_dly.252879942
Directory /workspace/1.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/1.spi_device_extreme_fifo_size.3614823860
Short name T1336
Test name
Test status
Simulation time 127410896138 ps
CPU time 2291.78 seconds
Started Dec 31 01:07:48 PM PST 23
Finished Dec 31 01:46:01 PM PST 23
Peak memory 220084 kb
Host smart-a84b3c31-0bbf-45cb-8c5b-62ae040470b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614823860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_extreme_fifo_size.3614823860
Directory /workspace/1.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/1.spi_device_fifo_full.4112234720
Short name T1695
Test name
Test status
Simulation time 126701489045 ps
CPU time 1414.94 seconds
Started Dec 31 01:07:35 PM PST 23
Finished Dec 31 01:31:11 PM PST 23
Peak memory 249308 kb
Host smart-204d3b73-5145-4485-bf5a-34b2f7c787df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112234720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_fifo_full.4112234720
Directory /workspace/1.spi_device_fifo_full/latest

Test location /workspace/coverage/default/1.spi_device_fifo_underflow_overflow.4232734123
Short name T558
Test name
Test status
Simulation time 144919788310 ps
CPU time 509.96 seconds
Started Dec 31 01:08:03 PM PST 23
Finished Dec 31 01:16:35 PM PST 23
Peak memory 443780 kb
Host smart-a451951d-be8b-4bba-8a05-7cbcc31bae4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232734123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_fifo_underflow_overfl
ow.4232734123
Directory /workspace/1.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2523403990
Short name T249
Test name
Test status
Simulation time 1771261241 ps
CPU time 19.53 seconds
Started Dec 31 01:08:46 PM PST 23
Finished Dec 31 01:09:07 PM PST 23
Peak memory 249640 kb
Host smart-9d9e5a1b-0dca-464f-988f-f7d1f1fba8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523403990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2523403990
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1445305756
Short name T627
Test name
Test status
Simulation time 918976074 ps
CPU time 17.67 seconds
Started Dec 31 01:08:00 PM PST 23
Finished Dec 31 01:08:19 PM PST 23
Peak memory 257668 kb
Host smart-660046ea-ce3b-45e4-83bb-91a3aac4c7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445305756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1445305756
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1096306032
Short name T1705
Test name
Test status
Simulation time 1062628669 ps
CPU time 5.33 seconds
Started Dec 31 01:08:48 PM PST 23
Finished Dec 31 01:08:55 PM PST 23
Peak memory 218568 kb
Host smart-35953104-756d-4733-806f-ea6c93cc27fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096306032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1096306032
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_intr.4000439780
Short name T1064
Test name
Test status
Simulation time 52199289424 ps
CPU time 65.49 seconds
Started Dec 31 01:07:32 PM PST 23
Finished Dec 31 01:08:40 PM PST 23
Peak memory 232816 kb
Host smart-574e84a3-8c07-47a3-bf6f-580f3357c8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000439780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intr.4000439780
Directory /workspace/1.spi_device_intr/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.330344686
Short name T224
Test name
Test status
Simulation time 3179691353 ps
CPU time 12.28 seconds
Started Dec 31 01:08:24 PM PST 23
Finished Dec 31 01:08:37 PM PST 23
Peak memory 232600 kb
Host smart-8896d30e-2e8a-442b-aa63-64a4a36725ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330344686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.330344686
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.458842856
Short name T1037
Test name
Test status
Simulation time 28497714 ps
CPU time 1.07 seconds
Started Dec 31 01:07:47 PM PST 23
Finished Dec 31 01:07:49 PM PST 23
Peak memory 218744 kb
Host smart-66177194-581f-4048-bb2e-4b26eb32c88c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458842856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.458842856
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.4103589975
Short name T231
Test name
Test status
Simulation time 5067172708 ps
CPU time 17.57 seconds
Started Dec 31 01:08:04 PM PST 23
Finished Dec 31 01:08:23 PM PST 23
Peak memory 240380 kb
Host smart-140102f0-a8cc-4f0d-b345-855dbd5a4237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103589975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.4103589975
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1299500789
Short name T276
Test name
Test status
Simulation time 9664221227 ps
CPU time 17.43 seconds
Started Dec 31 01:08:03 PM PST 23
Finished Dec 31 01:08:22 PM PST 23
Peak memory 249240 kb
Host smart-c1e5f39a-0dd6-48d0-ae18-b6cf1bdeec58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299500789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1299500789
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_perf.1672711517
Short name T1536
Test name
Test status
Simulation time 104056026926 ps
CPU time 680.83 seconds
Started Dec 31 01:07:49 PM PST 23
Finished Dec 31 01:19:11 PM PST 23
Peak memory 275148 kb
Host smart-6d0d2fd3-5f65-4044-84c1-d6bde9f34c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672711517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_perf.1672711517
Directory /workspace/1.spi_device_perf/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.2014783635
Short name T1028
Test name
Test status
Simulation time 65734699 ps
CPU time 0.73 seconds
Started Dec 31 01:07:48 PM PST 23
Finished Dec 31 01:07:50 PM PST 23
Peak memory 216556 kb
Host smart-6e85a401-309e-4de2-aaed-40b3588fdbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014783635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.2014783635
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1737064217
Short name T1297
Test name
Test status
Simulation time 441058525 ps
CPU time 4.21 seconds
Started Dec 31 01:08:05 PM PST 23
Finished Dec 31 01:08:12 PM PST 23
Peak memory 236712 kb
Host smart-b3c48d19-8c2c-41d1-bb9e-b5e3d4babb06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1737064217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1737064217
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_rx_async_fifo_reset.946232083
Short name T565
Test name
Test status
Simulation time 209973875 ps
CPU time 1 seconds
Started Dec 31 01:08:05 PM PST 23
Finished Dec 31 01:08:08 PM PST 23
Peak memory 208468 kb
Host smart-6a07ffdc-d09c-4c77-878a-06bd0b867522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946232083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_rx_async_fifo_reset.946232083
Directory /workspace/1.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/1.spi_device_rx_timeout.3477447460
Short name T1282
Test name
Test status
Simulation time 1288623160 ps
CPU time 6.2 seconds
Started Dec 31 01:08:28 PM PST 23
Finished Dec 31 01:08:35 PM PST 23
Peak memory 216760 kb
Host smart-45f2cdc1-4205-4994-ba3e-710507e8ce63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477447460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_rx_timeout.3477447460
Directory /workspace/1.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.389789432
Short name T76
Test name
Test status
Simulation time 48873890 ps
CPU time 1 seconds
Started Dec 31 01:08:30 PM PST 23
Finished Dec 31 01:08:32 PM PST 23
Peak memory 237160 kb
Host smart-27d1ef5c-0c41-4c29-8439-2a6e9dd6262e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389789432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.389789432
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_smoke.973265710
Short name T1303
Test name
Test status
Simulation time 152984811 ps
CPU time 1.05 seconds
Started Dec 31 01:08:03 PM PST 23
Finished Dec 31 01:08:06 PM PST 23
Peak memory 208036 kb
Host smart-36d00c31-926b-4b5b-81cb-7e66dee3203a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973265710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_smoke.973265710
Directory /workspace/1.spi_device_smoke/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3609317919
Short name T1540
Test name
Test status
Simulation time 16559573534 ps
CPU time 65.21 seconds
Started Dec 31 01:07:32 PM PST 23
Finished Dec 31 01:08:40 PM PST 23
Peak memory 216780 kb
Host smart-584c272d-c98d-4da4-b4fd-77253492e8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609317919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3609317919
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1750404099
Short name T1055
Test name
Test status
Simulation time 18338753731 ps
CPU time 27.36 seconds
Started Dec 31 01:07:47 PM PST 23
Finished Dec 31 01:08:16 PM PST 23
Peak memory 216784 kb
Host smart-d83522ad-0cb4-4f30-82e4-d32c82e769b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750404099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1750404099
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1260769316
Short name T529
Test name
Test status
Simulation time 108282288 ps
CPU time 1.84 seconds
Started Dec 31 01:07:59 PM PST 23
Finished Dec 31 01:08:02 PM PST 23
Peak memory 216796 kb
Host smart-6e87e1dc-ab75-402f-b2d5-7c83fdba5b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260769316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1260769316
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1173471121
Short name T883
Test name
Test status
Simulation time 42476617 ps
CPU time 0.9 seconds
Started Dec 31 01:08:23 PM PST 23
Finished Dec 31 01:08:25 PM PST 23
Peak memory 206880 kb
Host smart-e5498be7-b138-4300-ad5b-1e789a61ae1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173471121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1173471121
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_tx_async_fifo_reset.3344529467
Short name T1493
Test name
Test status
Simulation time 28396822 ps
CPU time 0.77 seconds
Started Dec 31 01:07:48 PM PST 23
Finished Dec 31 01:07:50 PM PST 23
Peak memory 208440 kb
Host smart-52962dec-714b-46a6-92f3-a8cba0cc7f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344529467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tx_async_fifo_reset.3344529467
Directory /workspace/1.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/1.spi_device_txrx.3065639920
Short name T1162
Test name
Test status
Simulation time 58980457567 ps
CPU time 256.52 seconds
Started Dec 31 01:08:00 PM PST 23
Finished Dec 31 01:12:18 PM PST 23
Peak memory 246444 kb
Host smart-486b2916-ad93-4483-bee9-c675b3622e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065639920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_txrx.3065639920
Directory /workspace/1.spi_device_txrx/latest

Test location /workspace/coverage/default/1.spi_device_upload.471497962
Short name T583
Test name
Test status
Simulation time 2035558684 ps
CPU time 2.6 seconds
Started Dec 31 01:08:08 PM PST 23
Finished Dec 31 01:08:13 PM PST 23
Peak memory 218428 kb
Host smart-62f8f4a8-965d-492d-a434-f387fcb2f571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471497962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.471497962
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_abort.1911265126
Short name T1449
Test name
Test status
Simulation time 49112871 ps
CPU time 0.74 seconds
Started Dec 31 01:08:59 PM PST 23
Finished Dec 31 01:09:09 PM PST 23
Peak memory 206556 kb
Host smart-06fb14ee-e4c0-4ea3-a054-b27b36487fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911265126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_abort.1911265126
Directory /workspace/10.spi_device_abort/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3574338168
Short name T555
Test name
Test status
Simulation time 23490304 ps
CPU time 0.72 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:08:58 PM PST 23
Peak memory 206536 kb
Host smart-c5c465fc-acfd-48ef-8136-afa8ed5826be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574338168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3574338168
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_bit_transfer.3915819223
Short name T1190
Test name
Test status
Simulation time 326603771 ps
CPU time 2.21 seconds
Started Dec 31 01:08:56 PM PST 23
Finished Dec 31 01:09:06 PM PST 23
Peak memory 216728 kb
Host smart-285fca8b-365f-42e1-a1f9-b84c29fb2990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915819223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_bit_transfer.3915819223
Directory /workspace/10.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/10.spi_device_byte_transfer.2668452748
Short name T570
Test name
Test status
Simulation time 284917451 ps
CPU time 2.65 seconds
Started Dec 31 01:08:54 PM PST 23
Finished Dec 31 01:09:02 PM PST 23
Peak memory 216872 kb
Host smart-ee4e92df-23b2-426c-8302-d05ec035f55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668452748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_byte_transfer.2668452748
Directory /workspace/10.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.4053324633
Short name T776
Test name
Test status
Simulation time 202151256 ps
CPU time 3.49 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:08:59 PM PST 23
Peak memory 240992 kb
Host smart-1cbbf6ba-88f3-4e55-8d11-ca24197e4b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053324633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.4053324633
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1079578093
Short name T562
Test name
Test status
Simulation time 16590125 ps
CPU time 0.77 seconds
Started Dec 31 01:09:01 PM PST 23
Finished Dec 31 01:09:09 PM PST 23
Peak memory 207612 kb
Host smart-5f63d1c0-b0fd-43b3-a488-05876a9d3f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079578093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1079578093
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_dummy_item_extra_dly.4212542370
Short name T708
Test name
Test status
Simulation time 35785054958 ps
CPU time 253.37 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:13:08 PM PST 23
Peak memory 287288 kb
Host smart-e7f736eb-cef9-44cb-b031-6e811694fd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212542370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_dummy_item_extra_dly.4212542370
Directory /workspace/10.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/10.spi_device_extreme_fifo_size.4232847114
Short name T612
Test name
Test status
Simulation time 70569708343 ps
CPU time 933.13 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:24:31 PM PST 23
Peak memory 219048 kb
Host smart-d1801d42-39f9-43da-959a-6542166aa7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232847114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_extreme_fifo_size.4232847114
Directory /workspace/10.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/10.spi_device_fifo_full.4020744063
Short name T463
Test name
Test status
Simulation time 172178670667 ps
CPU time 824.85 seconds
Started Dec 31 01:08:51 PM PST 23
Finished Dec 31 01:22:39 PM PST 23
Peak memory 255264 kb
Host smart-9765ce1a-7d50-4c6f-8773-b4c8f89a3155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020744063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_fifo_full.4020744063
Directory /workspace/10.spi_device_fifo_full/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3531474896
Short name T189
Test name
Test status
Simulation time 12717506345 ps
CPU time 60.33 seconds
Started Dec 31 01:08:36 PM PST 23
Finished Dec 31 01:09:39 PM PST 23
Peak memory 251472 kb
Host smart-c4cfec00-da72-4306-9ab9-338ec908c3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531474896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3531474896
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3265069609
Short name T1077
Test name
Test status
Simulation time 31025163504 ps
CPU time 231.03 seconds
Started Dec 31 01:08:50 PM PST 23
Finished Dec 31 01:12:44 PM PST 23
Peak memory 249128 kb
Host smart-82045cdf-b37d-4d96-8083-a49edc8a3b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265069609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3265069609
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2650918238
Short name T1721
Test name
Test status
Simulation time 943138258 ps
CPU time 16.94 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:09:15 PM PST 23
Peak memory 235448 kb
Host smart-1e6c7a4a-0942-4e10-8b73-0dc526d1b3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650918238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2650918238
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3342780860
Short name T244
Test name
Test status
Simulation time 898640043 ps
CPU time 6.76 seconds
Started Dec 31 01:08:48 PM PST 23
Finished Dec 31 01:08:56 PM PST 23
Peak memory 241160 kb
Host smart-eed55653-02bf-4d12-a2f4-a7c3a5e87bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342780860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3342780860
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_intr.198270860
Short name T662
Test name
Test status
Simulation time 33281138453 ps
CPU time 75.52 seconds
Started Dec 31 01:08:35 PM PST 23
Finished Dec 31 01:09:53 PM PST 23
Peak memory 238660 kb
Host smart-056192a6-a958-43e3-9231-67fc540f482b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198270860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intr.198270860
Directory /workspace/10.spi_device_intr/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1931053152
Short name T35
Test name
Test status
Simulation time 15236245 ps
CPU time 1.04 seconds
Started Dec 31 01:09:01 PM PST 23
Finished Dec 31 01:09:10 PM PST 23
Peak memory 218660 kb
Host smart-176d5fca-3ea2-4866-8bc0-cff4fdf3d67f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931053152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1931053152
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3216056131
Short name T281
Test name
Test status
Simulation time 1607832040 ps
CPU time 8.4 seconds
Started Dec 31 01:09:11 PM PST 23
Finished Dec 31 01:09:21 PM PST 23
Peak memory 240544 kb
Host smart-036d3bf1-a57b-496a-90d8-099352185817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216056131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3216056131
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2969036068
Short name T247
Test name
Test status
Simulation time 5838182453 ps
CPU time 14.94 seconds
Started Dec 31 01:09:11 PM PST 23
Finished Dec 31 01:09:27 PM PST 23
Peak memory 219168 kb
Host smart-fb4380bc-1af0-45c3-8b97-f05ad29ffc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969036068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2969036068
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_perf.116026433
Short name T1583
Test name
Test status
Simulation time 125302554309 ps
CPU time 445.3 seconds
Started Dec 31 01:08:50 PM PST 23
Finished Dec 31 01:16:18 PM PST 23
Peak memory 282488 kb
Host smart-f2d75dd7-d893-46af-ae7b-4a759e4d93e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116026433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_perf.116026433
Directory /workspace/10.spi_device_perf/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.818796314
Short name T1707
Test name
Test status
Simulation time 40945385 ps
CPU time 0.72 seconds
Started Dec 31 01:09:00 PM PST 23
Finished Dec 31 01:09:09 PM PST 23
Peak memory 216712 kb
Host smart-1a7a3601-0869-46e6-9880-5ee57514b540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818796314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.818796314
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2774414803
Short name T1775
Test name
Test status
Simulation time 2881150233 ps
CPU time 5.85 seconds
Started Dec 31 01:08:34 PM PST 23
Finished Dec 31 01:08:42 PM PST 23
Peak memory 234560 kb
Host smart-810d6895-c2e0-415d-ad86-714725122ddb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2774414803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2774414803
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_rx_async_fifo_reset.1458661951
Short name T1709
Test name
Test status
Simulation time 20341856 ps
CPU time 0.91 seconds
Started Dec 31 01:08:58 PM PST 23
Finished Dec 31 01:09:07 PM PST 23
Peak memory 208456 kb
Host smart-c15cb31d-b1a6-4838-b7e8-6273e58fa37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458661951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_rx_async_fifo_reset.1458661951
Directory /workspace/10.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/10.spi_device_rx_timeout.1087028306
Short name T1227
Test name
Test status
Simulation time 2644311997 ps
CPU time 5.97 seconds
Started Dec 31 01:08:59 PM PST 23
Finished Dec 31 01:09:13 PM PST 23
Peak memory 216864 kb
Host smart-96925d3c-7095-4f6a-b283-0bbff0e1120f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087028306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_rx_timeout.1087028306
Directory /workspace/10.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/10.spi_device_smoke.307524150
Short name T979
Test name
Test status
Simulation time 99669086 ps
CPU time 1.06 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:08:57 PM PST 23
Peak memory 216572 kb
Host smart-2b46c932-d570-4e51-9e4f-257cb7953e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307524150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_smoke.307524150
Directory /workspace/10.spi_device_smoke/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.194824827
Short name T1568
Test name
Test status
Simulation time 220259368656 ps
CPU time 4955.26 seconds
Started Dec 31 01:08:48 PM PST 23
Finished Dec 31 02:31:26 PM PST 23
Peak memory 387920 kb
Host smart-761176ba-3ae8-4f3e-9d85-f4b2b7eee2ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194824827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.194824827
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2663851954
Short name T1199
Test name
Test status
Simulation time 5708876741 ps
CPU time 31.92 seconds
Started Dec 31 01:09:14 PM PST 23
Finished Dec 31 01:09:49 PM PST 23
Peak memory 220676 kb
Host smart-a5034e93-a3b8-4402-8a5f-72e1a4d4e1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663851954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2663851954
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1642049289
Short name T1292
Test name
Test status
Simulation time 10436215447 ps
CPU time 11.68 seconds
Started Dec 31 01:08:59 PM PST 23
Finished Dec 31 01:09:19 PM PST 23
Peak memory 216864 kb
Host smart-44f66ea1-9850-4af8-bfd4-98c4ac5083f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642049289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1642049289
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2162308696
Short name T830
Test name
Test status
Simulation time 50503378 ps
CPU time 0.74 seconds
Started Dec 31 01:09:02 PM PST 23
Finished Dec 31 01:09:10 PM PST 23
Peak memory 206900 kb
Host smart-a66d96df-f2f6-4f7a-afd0-925ed505bdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162308696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2162308696
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.934713538
Short name T995
Test name
Test status
Simulation time 102245941 ps
CPU time 0.8 seconds
Started Dec 31 01:09:01 PM PST 23
Finished Dec 31 01:09:10 PM PST 23
Peak memory 206912 kb
Host smart-7223d485-ce76-4562-9230-fcef6d32bf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934713538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.934713538
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_tx_async_fifo_reset.1781160236
Short name T1668
Test name
Test status
Simulation time 17633195 ps
CPU time 0.84 seconds
Started Dec 31 01:08:59 PM PST 23
Finished Dec 31 01:09:08 PM PST 23
Peak memory 208460 kb
Host smart-c8ffba79-45b0-453d-a339-3f0cf3b53d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781160236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tx_async_fifo_reset.1781160236
Directory /workspace/10.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/10.spi_device_txrx.2294156233
Short name T1118
Test name
Test status
Simulation time 15668673906 ps
CPU time 164.46 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:11:42 PM PST 23
Peak memory 269704 kb
Host smart-601c5e3e-28dd-4faf-b200-13108d355a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294156233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_txrx.2294156233
Directory /workspace/10.spi_device_txrx/latest

Test location /workspace/coverage/default/10.spi_device_upload.2799350440
Short name T232
Test name
Test status
Simulation time 5688029130 ps
CPU time 10.13 seconds
Started Dec 31 01:08:55 PM PST 23
Finished Dec 31 01:09:12 PM PST 23
Peak memory 233188 kb
Host smart-330d1d1b-0b9d-414b-8db2-e921ab1d5144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799350440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2799350440
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_abort.4252696814
Short name T1342
Test name
Test status
Simulation time 49752679 ps
CPU time 0.76 seconds
Started Dec 31 01:08:54 PM PST 23
Finished Dec 31 01:09:01 PM PST 23
Peak memory 206568 kb
Host smart-068bc63f-0820-4773-8c7d-7ec607ac52ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252696814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_abort.4252696814
Directory /workspace/11.spi_device_abort/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3425889516
Short name T590
Test name
Test status
Simulation time 12968078 ps
CPU time 0.74 seconds
Started Dec 31 01:08:54 PM PST 23
Finished Dec 31 01:08:59 PM PST 23
Peak memory 206504 kb
Host smart-90686efa-82d8-477a-bd8a-1b227c26c8af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425889516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3425889516
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_bit_transfer.194646682
Short name T739
Test name
Test status
Simulation time 446723664 ps
CPU time 2.72 seconds
Started Dec 31 01:08:55 PM PST 23
Finished Dec 31 01:09:04 PM PST 23
Peak memory 216820 kb
Host smart-eb02ec12-116d-4f98-ac1c-d2006ecabf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194646682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_bit_transfer.194646682
Directory /workspace/11.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/11.spi_device_byte_transfer.110489759
Short name T663
Test name
Test status
Simulation time 199704982 ps
CPU time 2.53 seconds
Started Dec 31 01:08:56 PM PST 23
Finished Dec 31 01:09:06 PM PST 23
Peak memory 216848 kb
Host smart-a3d1cdf0-65fc-4fee-9889-395c83045dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110489759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_byte_transfer.110489759
Directory /workspace/11.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.417376712
Short name T1464
Test name
Test status
Simulation time 864409421 ps
CPU time 3.45 seconds
Started Dec 31 01:08:54 PM PST 23
Finished Dec 31 01:09:04 PM PST 23
Peak memory 220324 kb
Host smart-ab6d6441-f292-4eb0-aa96-602b6540a331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417376712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.417376712
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.400486696
Short name T456
Test name
Test status
Simulation time 12612087 ps
CPU time 0.75 seconds
Started Dec 31 01:08:51 PM PST 23
Finished Dec 31 01:08:54 PM PST 23
Peak memory 206544 kb
Host smart-9c89c99f-9c80-42f3-8eb5-c6b373e574c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400486696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.400486696
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_dummy_item_extra_dly.2038450765
Short name T656
Test name
Test status
Simulation time 51708623366 ps
CPU time 114.36 seconds
Started Dec 31 01:08:51 PM PST 23
Finished Dec 31 01:10:49 PM PST 23
Peak memory 256208 kb
Host smart-789f9f9d-9590-41cb-9c43-6b10e201aa0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038450765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_dummy_item_extra_dly.2038450765
Directory /workspace/11.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/11.spi_device_extreme_fifo_size.4041588697
Short name T1703
Test name
Test status
Simulation time 156396085653 ps
CPU time 70.71 seconds
Started Dec 31 01:08:57 PM PST 23
Finished Dec 31 01:10:15 PM PST 23
Peak memory 220072 kb
Host smart-b11e5d50-3dfe-46ee-b5f2-4307b55eeaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041588697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_extreme_fifo_size.4041588697
Directory /workspace/11.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/11.spi_device_fifo_full.358867869
Short name T1021
Test name
Test status
Simulation time 104212793575 ps
CPU time 792.46 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:22:10 PM PST 23
Peak memory 267644 kb
Host smart-830885c2-a49b-450e-b64c-110edb33c3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358867869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_fifo_full.358867869
Directory /workspace/11.spi_device_fifo_full/latest

Test location /workspace/coverage/default/11.spi_device_fifo_underflow_overflow.1801375250
Short name T968
Test name
Test status
Simulation time 19263032355 ps
CPU time 121.73 seconds
Started Dec 31 01:08:55 PM PST 23
Finished Dec 31 01:11:03 PM PST 23
Peak memory 282356 kb
Host smart-44b550c5-23c6-49b1-b366-08c0c5e53308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801375250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_fifo_underflow_overf
low.1801375250
Directory /workspace/11.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2689216640
Short name T1517
Test name
Test status
Simulation time 259388642305 ps
CPU time 138.68 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:11:16 PM PST 23
Peak memory 249788 kb
Host smart-fd389629-627a-4389-ab98-f855c17732ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689216640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2689216640
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2631044223
Short name T305
Test name
Test status
Simulation time 205903500750 ps
CPU time 548.09 seconds
Started Dec 31 01:08:58 PM PST 23
Finished Dec 31 01:18:14 PM PST 23
Peak memory 273876 kb
Host smart-f4bf081f-d3af-4437-a3b1-28291510f353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631044223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2631044223
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1203138315
Short name T1509
Test name
Test status
Simulation time 12908618614 ps
CPU time 63.54 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:10:00 PM PST 23
Peak memory 249856 kb
Host smart-6a61ee1f-3464-4383-86e7-865b8623d881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203138315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1203138315
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2977399825
Short name T1759
Test name
Test status
Simulation time 64349631978 ps
CPU time 31.02 seconds
Started Dec 31 01:08:57 PM PST 23
Finished Dec 31 01:09:36 PM PST 23
Peak memory 233340 kb
Host smart-31fb7fd0-33f9-498e-8dcc-efe265f1fe59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977399825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2977399825
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.177876221
Short name T887
Test name
Test status
Simulation time 304665876 ps
CPU time 4.66 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:09:00 PM PST 23
Peak memory 220512 kb
Host smart-3099058b-9296-41ab-a96d-2b2880427990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177876221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.177876221
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_intr.3628451275
Short name T1135
Test name
Test status
Simulation time 1847140193 ps
CPU time 9.77 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:09:06 PM PST 23
Peak memory 218128 kb
Host smart-5e2821d8-5d59-4e96-92ea-bd468e7990cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628451275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intr.3628451275
Directory /workspace/11.spi_device_intr/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3930673051
Short name T1725
Test name
Test status
Simulation time 17095851068 ps
CPU time 15.79 seconds
Started Dec 31 01:08:54 PM PST 23
Finished Dec 31 01:09:14 PM PST 23
Peak memory 225016 kb
Host smart-da4dbe3a-c1ec-44c0-a0a4-34f71bd1debd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930673051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3930673051
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1802001251
Short name T692
Test name
Test status
Simulation time 51762261 ps
CPU time 1.03 seconds
Started Dec 31 01:08:33 PM PST 23
Finished Dec 31 01:08:36 PM PST 23
Peak memory 218984 kb
Host smart-19f468f2-ffc0-4742-9e50-3454fe45af81
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802001251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1802001251
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1779630891
Short name T240
Test name
Test status
Simulation time 288494509 ps
CPU time 6.05 seconds
Started Dec 31 01:08:56 PM PST 23
Finished Dec 31 01:09:08 PM PST 23
Peak memory 237776 kb
Host smart-53756c2a-7a07-4f50-8c69-092b87c67730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779630891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1779630891
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.59599039
Short name T1477
Test name
Test status
Simulation time 15626151251 ps
CPU time 12.76 seconds
Started Dec 31 01:08:56 PM PST 23
Finished Dec 31 01:09:15 PM PST 23
Peak memory 236344 kb
Host smart-1964b1e0-ca8e-4f88-b005-13f381a33342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59599039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.59599039
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_perf.3298533354
Short name T1348
Test name
Test status
Simulation time 97823016898 ps
CPU time 400.96 seconds
Started Dec 31 01:08:34 PM PST 23
Finished Dec 31 01:15:17 PM PST 23
Peak memory 244800 kb
Host smart-e3c8babc-54c0-4d6e-9e9f-c1cd1459492b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298533354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_perf.3298533354
Directory /workspace/11.spi_device_perf/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.3851551714
Short name T588
Test name
Test status
Simulation time 15984028 ps
CPU time 0.74 seconds
Started Dec 31 01:08:54 PM PST 23
Finished Dec 31 01:08:59 PM PST 23
Peak memory 216636 kb
Host smart-2bdc8a74-60cf-4ccc-9248-ebc681e22c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851551714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.3851551714
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1037183167
Short name T1351
Test name
Test status
Simulation time 1417584624 ps
CPU time 5.26 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:09:03 PM PST 23
Peak memory 218944 kb
Host smart-1248a2e3-714f-484e-8d2e-6fbf9314c78f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1037183167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1037183167
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_rx_async_fifo_reset.3235142895
Short name T720
Test name
Test status
Simulation time 24725766 ps
CPU time 0.84 seconds
Started Dec 31 01:08:50 PM PST 23
Finished Dec 31 01:08:54 PM PST 23
Peak memory 208460 kb
Host smart-46a065f4-79c8-472e-bec7-6bd491ff5f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235142895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_rx_async_fifo_reset.3235142895
Directory /workspace/11.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/11.spi_device_rx_timeout.321325882
Short name T1181
Test name
Test status
Simulation time 8021196951 ps
CPU time 6.68 seconds
Started Dec 31 01:08:56 PM PST 23
Finished Dec 31 01:09:10 PM PST 23
Peak memory 216844 kb
Host smart-16d00d8b-111e-460e-bfc8-1fb1b408604d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321325882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_rx_timeout.321325882
Directory /workspace/11.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/11.spi_device_smoke.596875379
Short name T713
Test name
Test status
Simulation time 208839753 ps
CPU time 1.15 seconds
Started Dec 31 01:08:54 PM PST 23
Finished Dec 31 01:09:02 PM PST 23
Peak memory 208044 kb
Host smart-8f101e0c-1588-4553-9fa7-563853cfe20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596875379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_smoke.596875379
Directory /workspace/11.spi_device_smoke/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3415456138
Short name T1452
Test name
Test status
Simulation time 42224818123 ps
CPU time 144.58 seconds
Started Dec 31 01:08:56 PM PST 23
Finished Dec 31 01:11:28 PM PST 23
Peak memory 216828 kb
Host smart-1e7da53f-4200-409a-9af1-7e8af466e339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415456138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3415456138
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2990260135
Short name T1150
Test name
Test status
Simulation time 2483910847 ps
CPU time 11.23 seconds
Started Dec 31 01:08:35 PM PST 23
Finished Dec 31 01:08:49 PM PST 23
Peak memory 216896 kb
Host smart-e1653422-82fb-4656-82f2-0a8c6c6ebafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990260135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2990260135
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.412734394
Short name T1557
Test name
Test status
Simulation time 303698501 ps
CPU time 2.42 seconds
Started Dec 31 01:08:57 PM PST 23
Finished Dec 31 01:09:06 PM PST 23
Peak memory 216800 kb
Host smart-6318d90f-b76c-48f4-86eb-a0fa44f10ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412734394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.412734394
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2610842708
Short name T918
Test name
Test status
Simulation time 388611775 ps
CPU time 1.05 seconds
Started Dec 31 01:08:50 PM PST 23
Finished Dec 31 01:08:54 PM PST 23
Peak memory 206968 kb
Host smart-2cebbde7-5cb6-4cc0-970e-d56e7a2688b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610842708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2610842708
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_tx_async_fifo_reset.3929835322
Short name T1680
Test name
Test status
Simulation time 51745587 ps
CPU time 0.78 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:08:56 PM PST 23
Peak memory 208484 kb
Host smart-10d41f77-d2b3-4d57-b9ce-4138dcf5057d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929835322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tx_async_fifo_reset.3929835322
Directory /workspace/11.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/11.spi_device_txrx.3146705506
Short name T812
Test name
Test status
Simulation time 34514753818 ps
CPU time 241.58 seconds
Started Dec 31 01:08:50 PM PST 23
Finished Dec 31 01:12:55 PM PST 23
Peak memory 239776 kb
Host smart-865edd63-ff36-4d6f-97c0-0209df2a408d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146705506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_txrx.3146705506
Directory /workspace/11.spi_device_txrx/latest

Test location /workspace/coverage/default/11.spi_device_upload.3267322676
Short name T1660
Test name
Test status
Simulation time 6492141531 ps
CPU time 8.05 seconds
Started Dec 31 01:08:59 PM PST 23
Finished Dec 31 01:09:15 PM PST 23
Peak memory 219500 kb
Host smart-9e49b6d9-4335-4dc4-b76c-9323ffc06748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267322676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3267322676
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_abort.1691281794
Short name T726
Test name
Test status
Simulation time 46774738 ps
CPU time 0.8 seconds
Started Dec 31 01:08:54 PM PST 23
Finished Dec 31 01:09:00 PM PST 23
Peak memory 206556 kb
Host smart-791a2ca1-1c95-416a-ac9a-43fb0a882dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691281794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_abort.1691281794
Directory /workspace/12.spi_device_abort/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1757272893
Short name T1345
Test name
Test status
Simulation time 15449708 ps
CPU time 0.76 seconds
Started Dec 31 01:08:55 PM PST 23
Finished Dec 31 01:09:02 PM PST 23
Peak memory 206472 kb
Host smart-9adee21e-b77b-4093-b360-11e3c1441d79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757272893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1757272893
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_bit_transfer.135927574
Short name T502
Test name
Test status
Simulation time 126566827 ps
CPU time 2.47 seconds
Started Dec 31 01:09:01 PM PST 23
Finished Dec 31 01:09:12 PM PST 23
Peak memory 216480 kb
Host smart-28448519-6214-486f-8605-dcf43fd1bf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135927574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_bit_transfer.135927574
Directory /workspace/12.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/12.spi_device_byte_transfer.354780108
Short name T1446
Test name
Test status
Simulation time 161503530 ps
CPU time 3.01 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:08:59 PM PST 23
Peak memory 216804 kb
Host smart-b264c9a2-e965-42bf-849f-55b664b6b4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354780108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_byte_transfer.354780108
Directory /workspace/12.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2046134720
Short name T829
Test name
Test status
Simulation time 481238943 ps
CPU time 3.76 seconds
Started Dec 31 01:08:55 PM PST 23
Finished Dec 31 01:09:05 PM PST 23
Peak memory 218288 kb
Host smart-32a75024-052c-4bb5-b465-be900f695407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046134720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2046134720
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.106681906
Short name T636
Test name
Test status
Simulation time 32070752 ps
CPU time 0.75 seconds
Started Dec 31 01:09:02 PM PST 23
Finished Dec 31 01:09:10 PM PST 23
Peak memory 206584 kb
Host smart-88be09e4-dade-44e6-9f06-c857b3fa9b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106681906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.106681906
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_dummy_item_extra_dly.3483756823
Short name T1070
Test name
Test status
Simulation time 119130443194 ps
CPU time 252.24 seconds
Started Dec 31 01:08:55 PM PST 23
Finished Dec 31 01:13:14 PM PST 23
Peak memory 273708 kb
Host smart-487b2338-c3fb-4ad9-b814-262c69cb2bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483756823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_dummy_item_extra_dly.3483756823
Directory /workspace/12.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/12.spi_device_extreme_fifo_size.1433689175
Short name T1447
Test name
Test status
Simulation time 47896798744 ps
CPU time 2256.75 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:46:34 PM PST 23
Peak memory 224980 kb
Host smart-bf84bc68-9e68-4165-a8aa-d97ca61329a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433689175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_extreme_fifo_size.1433689175
Directory /workspace/12.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/12.spi_device_fifo_full.4275052105
Short name T1237
Test name
Test status
Simulation time 45068449031 ps
CPU time 255.04 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:13:11 PM PST 23
Peak memory 273448 kb
Host smart-fd4d9ba3-1bc5-4cc3-9e54-425d6ef1620c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275052105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_fifo_full.4275052105
Directory /workspace/12.spi_device_fifo_full/latest

Test location /workspace/coverage/default/12.spi_device_fifo_underflow_overflow.2814709679
Short name T1003
Test name
Test status
Simulation time 109811973910 ps
CPU time 136.84 seconds
Started Dec 31 01:08:56 PM PST 23
Finished Dec 31 01:11:21 PM PST 23
Peak memory 290252 kb
Host smart-dfff1125-0e00-401a-bc9f-00d885ff8e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814709679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_fifo_underflow_overf
low.2814709679
Directory /workspace/12.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3937580095
Short name T919
Test name
Test status
Simulation time 1339288818 ps
CPU time 21.37 seconds
Started Dec 31 01:08:54 PM PST 23
Finished Dec 31 01:09:20 PM PST 23
Peak memory 239964 kb
Host smart-bb724bcc-7ea2-4905-8569-0f77fe77b515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937580095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3937580095
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1057598757
Short name T205
Test name
Test status
Simulation time 38463875592 ps
CPU time 345.76 seconds
Started Dec 31 01:08:57 PM PST 23
Finished Dec 31 01:14:50 PM PST 23
Peak memory 266352 kb
Host smart-134cbad6-6da3-435c-9d3b-1267febdbdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057598757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1057598757
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.245988807
Short name T101
Test name
Test status
Simulation time 145059002294 ps
CPU time 271.03 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:13:28 PM PST 23
Peak memory 256624 kb
Host smart-6d403e59-64b9-46bb-8b4a-d17e014f29f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245988807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.245988807
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.451902718
Short name T761
Test name
Test status
Simulation time 6799465515 ps
CPU time 23.22 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:09:18 PM PST 23
Peak memory 240296 kb
Host smart-77245c00-8ca6-45f6-8fe0-4092e65c50cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451902718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.451902718
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.844957073
Short name T978
Test name
Test status
Simulation time 2868416159 ps
CPU time 10.99 seconds
Started Dec 31 01:08:58 PM PST 23
Finished Dec 31 01:09:18 PM PST 23
Peak memory 225148 kb
Host smart-f85c469c-b99f-4379-be87-da312635bfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844957073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.844957073
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_intr.3484503562
Short name T695
Test name
Test status
Simulation time 40146893208 ps
CPU time 74.96 seconds
Started Dec 31 01:08:57 PM PST 23
Finished Dec 31 01:10:19 PM PST 23
Peak memory 239704 kb
Host smart-567646e9-7f20-4628-90c1-35922ab0f33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484503562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intr.3484503562
Directory /workspace/12.spi_device_intr/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1115971414
Short name T289
Test name
Test status
Simulation time 457599733 ps
CPU time 5.57 seconds
Started Dec 31 01:08:55 PM PST 23
Finished Dec 31 01:09:07 PM PST 23
Peak memory 239984 kb
Host smart-cb81452b-223e-4b5b-8e37-f3cbb2161068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115971414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1115971414
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2636849334
Short name T1635
Test name
Test status
Simulation time 134817076 ps
CPU time 1.02 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:08:58 PM PST 23
Peak memory 218904 kb
Host smart-0066647e-ca6d-4c19-bfaa-7445de17e6f1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636849334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2636849334
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3557432946
Short name T299
Test name
Test status
Simulation time 8949709509 ps
CPU time 7.96 seconds
Started Dec 31 01:08:56 PM PST 23
Finished Dec 31 01:09:11 PM PST 23
Peak memory 222172 kb
Host smart-92094627-af95-4358-8e11-eff586b07c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557432946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3557432946
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1624052732
Short name T1419
Test name
Test status
Simulation time 9236138659 ps
CPU time 17.11 seconds
Started Dec 31 01:08:54 PM PST 23
Finished Dec 31 01:09:16 PM PST 23
Peak memory 219304 kb
Host smart-95d44098-6d8d-4245-9886-71d44a442f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624052732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1624052732
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_perf.1531072775
Short name T983
Test name
Test status
Simulation time 37346813976 ps
CPU time 234.35 seconds
Started Dec 31 01:08:51 PM PST 23
Finished Dec 31 01:12:49 PM PST 23
Peak memory 265672 kb
Host smart-90489166-dfb5-4309-bef3-73a3bdc18af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531072775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_perf.1531072775
Directory /workspace/12.spi_device_perf/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.779440155
Short name T667
Test name
Test status
Simulation time 17474864 ps
CPU time 0.73 seconds
Started Dec 31 01:08:50 PM PST 23
Finished Dec 31 01:08:54 PM PST 23
Peak memory 216176 kb
Host smart-bae9c286-3cff-4b62-8db2-f8dc9b7e419b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779440155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.779440155
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1344902373
Short name T853
Test name
Test status
Simulation time 612503931 ps
CPU time 4.83 seconds
Started Dec 31 01:08:56 PM PST 23
Finished Dec 31 01:09:08 PM PST 23
Peak memory 237080 kb
Host smart-572749b8-5306-4e8f-86db-77119b8054a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1344902373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1344902373
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_rx_async_fifo_reset.1448168600
Short name T671
Test name
Test status
Simulation time 37577155 ps
CPU time 0.9 seconds
Started Dec 31 01:08:55 PM PST 23
Finished Dec 31 01:09:03 PM PST 23
Peak memory 208448 kb
Host smart-ff0d442f-58db-4ee8-96d1-2b5699374b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448168600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_rx_async_fifo_reset.1448168600
Directory /workspace/12.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/12.spi_device_rx_timeout.1297974951
Short name T1113
Test name
Test status
Simulation time 507059806 ps
CPU time 4.75 seconds
Started Dec 31 01:08:55 PM PST 23
Finished Dec 31 01:09:06 PM PST 23
Peak memory 216864 kb
Host smart-c4b14ec9-9ab3-4e04-8099-016374ed46cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297974951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_rx_timeout.1297974951
Directory /workspace/12.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/12.spi_device_smoke.3750894274
Short name T688
Test name
Test status
Simulation time 73858681 ps
CPU time 1.13 seconds
Started Dec 31 01:08:56 PM PST 23
Finished Dec 31 01:09:05 PM PST 23
Peak memory 216760 kb
Host smart-44bb34dc-cde0-44f5-9fbe-a74a1ddfbd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750894274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_smoke.3750894274
Directory /workspace/12.spi_device_smoke/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3061751649
Short name T1744
Test name
Test status
Simulation time 1890258727404 ps
CPU time 1571.37 seconds
Started Dec 31 01:08:54 PM PST 23
Finished Dec 31 01:35:12 PM PST 23
Peak memory 438136 kb
Host smart-20d91a54-b151-496c-97da-5eeedefa4262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061751649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3061751649
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.443077563
Short name T1205
Test name
Test status
Simulation time 5453089630 ps
CPU time 49.3 seconds
Started Dec 31 01:08:56 PM PST 23
Finished Dec 31 01:09:52 PM PST 23
Peak memory 217180 kb
Host smart-9cce8fd5-baa8-44e9-b58d-216caebbe30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443077563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.443077563
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2361230759
Short name T604
Test name
Test status
Simulation time 4040575590 ps
CPU time 7.19 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:09:04 PM PST 23
Peak memory 216904 kb
Host smart-49926b75-e34b-4401-9e45-738e81f7c240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361230759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2361230759
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2960205509
Short name T1380
Test name
Test status
Simulation time 81104032 ps
CPU time 0.97 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:08:58 PM PST 23
Peak memory 208120 kb
Host smart-69544bac-1958-4e33-825c-c858ba13fc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960205509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2960205509
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3044448522
Short name T1441
Test name
Test status
Simulation time 137171783 ps
CPU time 0.83 seconds
Started Dec 31 01:08:54 PM PST 23
Finished Dec 31 01:09:00 PM PST 23
Peak memory 206840 kb
Host smart-d52a787a-0094-4c83-a1f3-69df4df98246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044448522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3044448522
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_tx_async_fifo_reset.2577069423
Short name T1772
Test name
Test status
Simulation time 16099008 ps
CPU time 0.8 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:08:57 PM PST 23
Peak memory 208440 kb
Host smart-b5d058f8-3c2a-4835-84f1-4fefb0c4a706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577069423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tx_async_fifo_reset.2577069423
Directory /workspace/12.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/12.spi_device_txrx.763466356
Short name T767
Test name
Test status
Simulation time 19774904117 ps
CPU time 229.37 seconds
Started Dec 31 01:08:57 PM PST 23
Finished Dec 31 01:12:54 PM PST 23
Peak memory 273680 kb
Host smart-7ca52653-f9a0-4076-a47d-6bfe0401ea67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763466356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_txrx.763466356
Directory /workspace/12.spi_device_txrx/latest

Test location /workspace/coverage/default/12.spi_device_upload.732888584
Short name T1108
Test name
Test status
Simulation time 17255115253 ps
CPU time 20.83 seconds
Started Dec 31 01:08:55 PM PST 23
Finished Dec 31 01:09:23 PM PST 23
Peak memory 233264 kb
Host smart-2ba25231-4b1c-455b-bdf7-6d0f20a36674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732888584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.732888584
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_abort.2238307331
Short name T66
Test name
Test status
Simulation time 34626075 ps
CPU time 0.74 seconds
Started Dec 31 01:08:57 PM PST 23
Finished Dec 31 01:09:05 PM PST 23
Peak memory 206600 kb
Host smart-fd589c90-3072-4c44-a033-4f82ba4940d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238307331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_abort.2238307331
Directory /workspace/13.spi_device_abort/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.4258856256
Short name T1454
Test name
Test status
Simulation time 13436334 ps
CPU time 0.72 seconds
Started Dec 31 01:08:57 PM PST 23
Finished Dec 31 01:09:05 PM PST 23
Peak memory 206368 kb
Host smart-7427bbab-292d-4be9-8a0a-1deae13abd7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258856256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
4258856256
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_bit_transfer.731271803
Short name T83
Test name
Test status
Simulation time 292228325 ps
CPU time 2.66 seconds
Started Dec 31 01:08:57 PM PST 23
Finished Dec 31 01:09:07 PM PST 23
Peak memory 216780 kb
Host smart-59699d7c-9b3c-4c98-b3ab-286f7fd0bd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731271803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_bit_transfer.731271803
Directory /workspace/13.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/13.spi_device_byte_transfer.1844878494
Short name T1535
Test name
Test status
Simulation time 177720377 ps
CPU time 2.44 seconds
Started Dec 31 01:09:17 PM PST 23
Finished Dec 31 01:09:22 PM PST 23
Peak memory 216804 kb
Host smart-342b3f05-1b70-4c30-bc47-cbd0a957e0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844878494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_byte_transfer.1844878494
Directory /workspace/13.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2196998414
Short name T263
Test name
Test status
Simulation time 79775106 ps
CPU time 3.25 seconds
Started Dec 31 01:08:51 PM PST 23
Finished Dec 31 01:08:57 PM PST 23
Peak memory 238468 kb
Host smart-9803aece-8fe2-427b-92c3-c66385bc0cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196998414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2196998414
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.397552101
Short name T1044
Test name
Test status
Simulation time 59591895 ps
CPU time 0.77 seconds
Started Dec 31 01:09:16 PM PST 23
Finished Dec 31 01:09:19 PM PST 23
Peak memory 207508 kb
Host smart-f2559ba3-e496-48e2-a915-37f813a62ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397552101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.397552101
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_dummy_item_extra_dly.2402742355
Short name T1378
Test name
Test status
Simulation time 205803355813 ps
CPU time 468.58 seconds
Started Dec 31 01:09:13 PM PST 23
Finished Dec 31 01:17:04 PM PST 23
Peak memory 255300 kb
Host smart-b5f84e02-f92f-4683-9430-8c1e36f08c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402742355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_dummy_item_extra_dly.2402742355
Directory /workspace/13.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/13.spi_device_extreme_fifo_size.2010385562
Short name T863
Test name
Test status
Simulation time 74623943736 ps
CPU time 69.34 seconds
Started Dec 31 01:09:13 PM PST 23
Finished Dec 31 01:10:25 PM PST 23
Peak memory 220484 kb
Host smart-cec6b7f4-e1b6-475b-adff-121a9fdba50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010385562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_extreme_fifo_size.2010385562
Directory /workspace/13.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/13.spi_device_fifo_full.2244063766
Short name T1445
Test name
Test status
Simulation time 40459224261 ps
CPU time 248.06 seconds
Started Dec 31 01:08:58 PM PST 23
Finished Dec 31 01:13:15 PM PST 23
Peak memory 273108 kb
Host smart-bb595dad-a125-4b98-b40b-d84beb03caa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244063766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_fifo_full.2244063766
Directory /workspace/13.spi_device_fifo_full/latest

Test location /workspace/coverage/default/13.spi_device_fifo_underflow_overflow.955979676
Short name T1700
Test name
Test status
Simulation time 383891704029 ps
CPU time 1107.84 seconds
Started Dec 31 01:09:12 PM PST 23
Finished Dec 31 01:27:43 PM PST 23
Peak memory 824284 kb
Host smart-bf3e61e0-371a-41fc-92f8-91fb99fb44ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955979676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_fifo_underflow_overfl
ow.955979676
Directory /workspace/13.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.733584927
Short name T1606
Test name
Test status
Simulation time 20194681392 ps
CPU time 110.49 seconds
Started Dec 31 01:08:58 PM PST 23
Finished Dec 31 01:10:55 PM PST 23
Peak memory 257152 kb
Host smart-25764dc0-52eb-4685-89c9-832c9ee8612e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733584927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.733584927
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3287358263
Short name T192
Test name
Test status
Simulation time 14711494175 ps
CPU time 105.1 seconds
Started Dec 31 01:08:51 PM PST 23
Finished Dec 31 01:10:39 PM PST 23
Peak memory 250380 kb
Host smart-41ea78ee-af65-48fc-9314-69aaedf62077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287358263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3287358263
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_intercept.113209062
Short name T935
Test name
Test status
Simulation time 1303660453 ps
CPU time 3.62 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:09:01 PM PST 23
Peak memory 218544 kb
Host smart-2aa33154-650e-4ad5-8cb1-2e204ec9a624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113209062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.113209062
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_intr.2788981498
Short name T1216
Test name
Test status
Simulation time 9537794343 ps
CPU time 17.71 seconds
Started Dec 31 01:08:57 PM PST 23
Finished Dec 31 01:09:22 PM PST 23
Peak memory 218044 kb
Host smart-1112bac7-b096-4fdc-b62d-c9d55954ecde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788981498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intr.2788981498
Directory /workspace/13.spi_device_intr/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.6313923
Short name T209
Test name
Test status
Simulation time 540933659 ps
CPU time 7.67 seconds
Started Dec 31 01:08:58 PM PST 23
Finished Dec 31 01:09:13 PM PST 23
Peak memory 219740 kb
Host smart-801bcb99-e4fe-4f4e-b9ea-4f40990b8019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6313923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.6313923
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2047280743
Short name T1434
Test name
Test status
Simulation time 17856653 ps
CPU time 1.05 seconds
Started Dec 31 01:09:16 PM PST 23
Finished Dec 31 01:09:20 PM PST 23
Peak memory 218776 kb
Host smart-268b9847-4431-4065-8c72-6a94c5b8d8af
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047280743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2047280743
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.4019109372
Short name T1402
Test name
Test status
Simulation time 675875669 ps
CPU time 5.04 seconds
Started Dec 31 01:08:57 PM PST 23
Finished Dec 31 01:09:09 PM PST 23
Peak memory 239492 kb
Host smart-977f421b-6f8e-4e7a-9c0a-fd19e9907b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019109372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.4019109372
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1693214972
Short name T710
Test name
Test status
Simulation time 30571370725 ps
CPU time 11.87 seconds
Started Dec 31 01:08:57 PM PST 23
Finished Dec 31 01:09:17 PM PST 23
Peak memory 238024 kb
Host smart-28e715c4-9444-4917-b426-e8bf5ee40aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693214972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1693214972
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_perf.2675167820
Short name T492
Test name
Test status
Simulation time 147619045453 ps
CPU time 1673.84 seconds
Started Dec 31 01:09:01 PM PST 23
Finished Dec 31 01:37:03 PM PST 23
Peak memory 249752 kb
Host smart-3546555a-171f-4d46-bbd4-7bf7185cbb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675167820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_perf.2675167820
Directory /workspace/13.spi_device_perf/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.1737349249
Short name T568
Test name
Test status
Simulation time 24217432 ps
CPU time 0.73 seconds
Started Dec 31 01:08:56 PM PST 23
Finished Dec 31 01:09:04 PM PST 23
Peak memory 216680 kb
Host smart-af52d8d3-a004-4276-90aa-1f37ab77187b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737349249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.1737349249
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1440843751
Short name T967
Test name
Test status
Simulation time 384968718 ps
CPU time 4.32 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:09:00 PM PST 23
Peak memory 220964 kb
Host smart-84fdbc19-dde8-4597-9c4b-92b9373a3ee2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1440843751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1440843751
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_rx_timeout.3176301092
Short name T741
Test name
Test status
Simulation time 527723582 ps
CPU time 5.32 seconds
Started Dec 31 01:09:01 PM PST 23
Finished Dec 31 01:09:14 PM PST 23
Peak memory 216584 kb
Host smart-158029fb-a265-4ab9-b53f-8502a272bdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176301092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_rx_timeout.3176301092
Directory /workspace/13.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/13.spi_device_smoke.1044063802
Short name T1079
Test name
Test status
Simulation time 26863082 ps
CPU time 0.89 seconds
Started Dec 31 01:08:56 PM PST 23
Finished Dec 31 01:09:04 PM PST 23
Peak memory 207840 kb
Host smart-f36ca171-dca8-45d1-be8f-80e9ac496fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044063802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_smoke.1044063802
Directory /workspace/13.spi_device_smoke/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.228445518
Short name T1632
Test name
Test status
Simulation time 217735171412 ps
CPU time 1169.58 seconds
Started Dec 31 01:08:58 PM PST 23
Finished Dec 31 01:28:35 PM PST 23
Peak memory 504188 kb
Host smart-529ac53a-abad-4749-bb13-977e28c789af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228445518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.228445518
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2347936375
Short name T1365
Test name
Test status
Simulation time 25990931530 ps
CPU time 69.27 seconds
Started Dec 31 01:09:14 PM PST 23
Finished Dec 31 01:10:26 PM PST 23
Peak memory 217868 kb
Host smart-2d53f08a-4d3c-4f76-a866-d673d2d38d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347936375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2347936375
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1458363140
Short name T516
Test name
Test status
Simulation time 2865469547 ps
CPU time 11.36 seconds
Started Dec 31 01:08:58 PM PST 23
Finished Dec 31 01:09:17 PM PST 23
Peak memory 216872 kb
Host smart-ccb6d0cd-5a33-4111-b5d9-41e66ad14978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458363140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1458363140
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.258359919
Short name T874
Test name
Test status
Simulation time 33601518 ps
CPU time 0.98 seconds
Started Dec 31 01:08:51 PM PST 23
Finished Dec 31 01:08:55 PM PST 23
Peak memory 207984 kb
Host smart-26775ef1-91e5-40da-8bad-30df8a28c7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258359919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.258359919
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2225904538
Short name T899
Test name
Test status
Simulation time 39902725 ps
CPU time 0.81 seconds
Started Dec 31 01:08:55 PM PST 23
Finished Dec 31 01:09:02 PM PST 23
Peak memory 206812 kb
Host smart-e9aec697-46b5-47e5-890f-a7d27dbded9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225904538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2225904538
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_tx_async_fifo_reset.436512925
Short name T1561
Test name
Test status
Simulation time 27245241 ps
CPU time 0.79 seconds
Started Dec 31 01:08:56 PM PST 23
Finished Dec 31 01:09:03 PM PST 23
Peak memory 208424 kb
Host smart-87b6f8d8-8177-44f7-890d-16a6fb71213e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436512925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tx_async_fifo_reset.436512925
Directory /workspace/13.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/13.spi_device_txrx.3064805578
Short name T697
Test name
Test status
Simulation time 73758837693 ps
CPU time 379.46 seconds
Started Dec 31 01:08:58 PM PST 23
Finished Dec 31 01:15:25 PM PST 23
Peak memory 298292 kb
Host smart-0e2bde63-4a1f-466f-a03f-d2d743703ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064805578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_txrx.3064805578
Directory /workspace/13.spi_device_txrx/latest

Test location /workspace/coverage/default/13.spi_device_upload.2144889516
Short name T520
Test name
Test status
Simulation time 436987329 ps
CPU time 3.28 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:09:01 PM PST 23
Peak memory 233232 kb
Host smart-0b2ba9c5-dab2-49da-96d7-8181e6d66e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144889516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2144889516
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_abort.3716972749
Short name T1101
Test name
Test status
Simulation time 38433813 ps
CPU time 0.74 seconds
Started Dec 31 01:09:11 PM PST 23
Finished Dec 31 01:09:13 PM PST 23
Peak memory 206584 kb
Host smart-c9b26fc4-4c8b-4096-a826-4dff93af7b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716972749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_abort.3716972749
Directory /workspace/14.spi_device_abort/latest

Test location /workspace/coverage/default/14.spi_device_bit_transfer.3568860105
Short name T970
Test name
Test status
Simulation time 123052137 ps
CPU time 2.25 seconds
Started Dec 31 01:08:55 PM PST 23
Finished Dec 31 01:09:03 PM PST 23
Peak memory 216820 kb
Host smart-ab6b7d6f-6fb9-45f7-b4e6-1d1f6988385c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568860105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_bit_transfer.3568860105
Directory /workspace/14.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/14.spi_device_byte_transfer.1794625025
Short name T1183
Test name
Test status
Simulation time 147934740 ps
CPU time 2.61 seconds
Started Dec 31 01:09:12 PM PST 23
Finished Dec 31 01:09:17 PM PST 23
Peak memory 216780 kb
Host smart-b9a7de60-c4de-4598-8d82-4a682bc467ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794625025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_byte_transfer.1794625025
Directory /workspace/14.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.922033669
Short name T1326
Test name
Test status
Simulation time 2217371006 ps
CPU time 5.07 seconds
Started Dec 31 01:08:59 PM PST 23
Finished Dec 31 01:09:12 PM PST 23
Peak memory 236548 kb
Host smart-1c50baa9-94fb-4a11-b3f9-96bdd07722f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922033669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.922033669
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3668488904
Short name T1458
Test name
Test status
Simulation time 17243620 ps
CPU time 0.78 seconds
Started Dec 31 01:09:18 PM PST 23
Finished Dec 31 01:09:20 PM PST 23
Peak memory 206528 kb
Host smart-addc3440-0334-4f65-88bd-3f94d771822f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668488904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3668488904
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_dummy_item_extra_dly.354151372
Short name T634
Test name
Test status
Simulation time 44300712257 ps
CPU time 338.39 seconds
Started Dec 31 01:09:00 PM PST 23
Finished Dec 31 01:14:47 PM PST 23
Peak memory 296824 kb
Host smart-1c6d3f5f-75e4-401f-b6d9-0efc9a3cbfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354151372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_dummy_item_extra_dly.354151372
Directory /workspace/14.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/14.spi_device_extreme_fifo_size.859921480
Short name T1601
Test name
Test status
Simulation time 29126110201 ps
CPU time 163.77 seconds
Started Dec 31 01:09:22 PM PST 23
Finished Dec 31 01:12:08 PM PST 23
Peak memory 230580 kb
Host smart-95a36516-eadb-4ccb-a4a5-d931d2e11ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859921480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_extreme_fifo_size.859921480
Directory /workspace/14.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/14.spi_device_fifo_full.869676986
Short name T1462
Test name
Test status
Simulation time 266166999970 ps
CPU time 616 seconds
Started Dec 31 01:09:11 PM PST 23
Finished Dec 31 01:19:29 PM PST 23
Peak memory 255636 kb
Host smart-2486b9b7-a7d7-40ae-8609-88cb5a9a202a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869676986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_fifo_full.869676986
Directory /workspace/14.spi_device_fifo_full/latest

Test location /workspace/coverage/default/14.spi_device_fifo_underflow_overflow.1164707988
Short name T957
Test name
Test status
Simulation time 258326566559 ps
CPU time 474.15 seconds
Started Dec 31 01:09:13 PM PST 23
Finished Dec 31 01:17:09 PM PST 23
Peak memory 408628 kb
Host smart-b9a01b17-a361-4686-8fc2-49c784df014b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164707988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_fifo_underflow_overf
low.1164707988
Directory /workspace/14.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1348683180
Short name T811
Test name
Test status
Simulation time 16677216894 ps
CPU time 62.47 seconds
Started Dec 31 01:09:10 PM PST 23
Finished Dec 31 01:10:14 PM PST 23
Peak memory 252272 kb
Host smart-1e6fcc66-1730-45ce-94ad-ab688c205443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348683180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1348683180
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1816981102
Short name T300
Test name
Test status
Simulation time 68565403319 ps
CPU time 241.88 seconds
Started Dec 31 01:09:22 PM PST 23
Finished Dec 31 01:13:26 PM PST 23
Peak memory 277868 kb
Host smart-fa8fc64c-b9bf-4131-a848-c4637b69df11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816981102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1816981102
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1715046906
Short name T322
Test name
Test status
Simulation time 69736019217 ps
CPU time 389.06 seconds
Started Dec 31 01:09:09 PM PST 23
Finished Dec 31 01:15:40 PM PST 23
Peak memory 267848 kb
Host smart-2fc400b7-46ae-4110-bcce-6fcbf2341e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715046906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1715046906
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3028628261
Short name T1219
Test name
Test status
Simulation time 529454959 ps
CPU time 5 seconds
Started Dec 31 01:09:14 PM PST 23
Finished Dec 31 01:09:21 PM PST 23
Peak memory 240064 kb
Host smart-9298bcd4-70b9-4dc2-9e5b-4fc86bd2d298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028628261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3028628261
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_intr.2206940280
Short name T645
Test name
Test status
Simulation time 7075623855 ps
CPU time 34.05 seconds
Started Dec 31 01:09:01 PM PST 23
Finished Dec 31 01:09:43 PM PST 23
Peak memory 220032 kb
Host smart-69798571-1f31-4aca-b4e2-3db0e83e15ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206940280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intr.2206940280
Directory /workspace/14.spi_device_intr/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2258617408
Short name T1398
Test name
Test status
Simulation time 4731669830 ps
CPU time 16.63 seconds
Started Dec 31 01:09:11 PM PST 23
Finished Dec 31 01:09:30 PM PST 23
Peak memory 221788 kb
Host smart-b69d659c-f3b9-4ad6-8614-78405f5e2118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258617408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2258617408
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.605036890
Short name T1612
Test name
Test status
Simulation time 309796432 ps
CPU time 1.1 seconds
Started Dec 31 01:09:12 PM PST 23
Finished Dec 31 01:09:16 PM PST 23
Peak memory 218884 kb
Host smart-77ffc81c-0dbe-4791-97f8-bd54394ed0a6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605036890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.605036890
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3907565156
Short name T1685
Test name
Test status
Simulation time 17999091439 ps
CPU time 11.45 seconds
Started Dec 31 01:09:00 PM PST 23
Finished Dec 31 01:09:20 PM PST 23
Peak memory 238052 kb
Host smart-212b5df3-739c-4759-85d8-593824941acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907565156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3907565156
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1439260520
Short name T111
Test name
Test status
Simulation time 770708313 ps
CPU time 6.07 seconds
Started Dec 31 01:09:11 PM PST 23
Finished Dec 31 01:09:18 PM PST 23
Peak memory 220736 kb
Host smart-3556df6e-5b62-4efb-bdb7-e30885e5f865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439260520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1439260520
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_perf.1939108835
Short name T992
Test name
Test status
Simulation time 353685174263 ps
CPU time 837.92 seconds
Started Dec 31 01:09:18 PM PST 23
Finished Dec 31 01:23:17 PM PST 23
Peak memory 274176 kb
Host smart-128010b0-1ba0-4f48-beaf-4ce19693e93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939108835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_perf.1939108835
Directory /workspace/14.spi_device_perf/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.2973557766
Short name T1727
Test name
Test status
Simulation time 14854694 ps
CPU time 0.75 seconds
Started Dec 31 01:08:55 PM PST 23
Finished Dec 31 01:09:02 PM PST 23
Peak memory 216684 kb
Host smart-f4cbc8d9-89dc-42b7-8e3b-1c76bd9772f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973557766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.2973557766
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4106021362
Short name T1214
Test name
Test status
Simulation time 380731788 ps
CPU time 4.48 seconds
Started Dec 31 01:09:15 PM PST 23
Finished Dec 31 01:09:22 PM PST 23
Peak memory 235896 kb
Host smart-600a8538-7ffa-4af5-b90e-1b470cfeecfd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4106021362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4106021362
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_rx_async_fifo_reset.2870495275
Short name T794
Test name
Test status
Simulation time 18649524 ps
CPU time 0.89 seconds
Started Dec 31 01:09:16 PM PST 23
Finished Dec 31 01:09:20 PM PST 23
Peak memory 208492 kb
Host smart-8eb3c9c0-13d4-4027-83a1-bd038363435b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870495275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_rx_async_fifo_reset.2870495275
Directory /workspace/14.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/14.spi_device_rx_timeout.1794639473
Short name T770
Test name
Test status
Simulation time 1203815926 ps
CPU time 5.21 seconds
Started Dec 31 01:08:55 PM PST 23
Finished Dec 31 01:09:07 PM PST 23
Peak memory 216788 kb
Host smart-ab0a94ff-3f39-425b-a65c-4e62b62082e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794639473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_rx_timeout.1794639473
Directory /workspace/14.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/14.spi_device_smoke.351330042
Short name T1334
Test name
Test status
Simulation time 55467633 ps
CPU time 1.11 seconds
Started Dec 31 01:09:11 PM PST 23
Finished Dec 31 01:09:14 PM PST 23
Peak memory 216776 kb
Host smart-ab310259-3b3b-4e3c-a758-6d40053f8809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351330042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_smoke.351330042
Directory /workspace/14.spi_device_smoke/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.4235522143
Short name T1769
Test name
Test status
Simulation time 40945293962 ps
CPU time 56.37 seconds
Started Dec 31 01:09:13 PM PST 23
Finished Dec 31 01:10:12 PM PST 23
Peak memory 236756 kb
Host smart-d492ce61-44aa-4065-9a5e-09cf0273ef41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235522143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.4235522143
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.865771830
Short name T1301
Test name
Test status
Simulation time 3481832485 ps
CPU time 31.53 seconds
Started Dec 31 01:09:13 PM PST 23
Finished Dec 31 01:09:46 PM PST 23
Peak memory 217264 kb
Host smart-d143a3ec-c05f-48c8-bff8-8140d53cd0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865771830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.865771830
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1750477783
Short name T1776
Test name
Test status
Simulation time 5635470355 ps
CPU time 20.77 seconds
Started Dec 31 01:09:16 PM PST 23
Finished Dec 31 01:09:40 PM PST 23
Peak memory 216940 kb
Host smart-2a503d74-1313-491a-9202-1ba7470ce9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750477783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1750477783
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3832138655
Short name T1768
Test name
Test status
Simulation time 275641739 ps
CPU time 6.29 seconds
Started Dec 31 01:09:16 PM PST 23
Finished Dec 31 01:09:25 PM PST 23
Peak memory 216876 kb
Host smart-6b23dadb-75d9-4f02-92df-8dbd5d15df70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832138655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3832138655
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1316246762
Short name T778
Test name
Test status
Simulation time 290672956 ps
CPU time 1.13 seconds
Started Dec 31 01:09:00 PM PST 23
Finished Dec 31 01:09:10 PM PST 23
Peak memory 208044 kb
Host smart-9cac3d3b-83ff-4414-aee9-a7b814339520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316246762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1316246762
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_tx_async_fifo_reset.3738346179
Short name T1444
Test name
Test status
Simulation time 23104112 ps
CPU time 0.79 seconds
Started Dec 31 01:08:55 PM PST 23
Finished Dec 31 01:09:02 PM PST 23
Peak memory 208444 kb
Host smart-f5c6e20f-5242-406a-b447-1596a59cf742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738346179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tx_async_fifo_reset.3738346179
Directory /workspace/14.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/14.spi_device_txrx.442667800
Short name T751
Test name
Test status
Simulation time 7996215425 ps
CPU time 155.87 seconds
Started Dec 31 01:09:15 PM PST 23
Finished Dec 31 01:11:53 PM PST 23
Peak memory 265460 kb
Host smart-31bb0c9c-6be3-4dcb-9fdf-f1c0ee5dcbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442667800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_txrx.442667800
Directory /workspace/14.spi_device_txrx/latest

Test location /workspace/coverage/default/14.spi_device_upload.3794583078
Short name T1358
Test name
Test status
Simulation time 73981599 ps
CPU time 3.03 seconds
Started Dec 31 01:08:54 PM PST 23
Finished Dec 31 01:09:02 PM PST 23
Peak memory 234480 kb
Host smart-e44760cf-adb2-477e-81b2-379a2c79a173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794583078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3794583078
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_abort.653634724
Short name T755
Test name
Test status
Simulation time 28212397 ps
CPU time 0.77 seconds
Started Dec 31 01:09:21 PM PST 23
Finished Dec 31 01:09:24 PM PST 23
Peak memory 206576 kb
Host smart-f2c78ba9-a4f0-43a7-b706-24625bda6e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653634724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_abort.653634724
Directory /workspace/15.spi_device_abort/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3957224092
Short name T1491
Test name
Test status
Simulation time 65008681 ps
CPU time 0.69 seconds
Started Dec 31 01:09:16 PM PST 23
Finished Dec 31 01:09:19 PM PST 23
Peak memory 206524 kb
Host smart-9f63993d-0fe7-42be-86e6-402f1e7a494b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957224092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3957224092
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_bit_transfer.3735567647
Short name T969
Test name
Test status
Simulation time 1960981939 ps
CPU time 2.95 seconds
Started Dec 31 01:09:11 PM PST 23
Finished Dec 31 01:09:14 PM PST 23
Peak memory 216792 kb
Host smart-255692ad-a5eb-4a76-858a-2e85b23a6e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735567647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_bit_transfer.3735567647
Directory /workspace/15.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/15.spi_device_byte_transfer.4026702151
Short name T1324
Test name
Test status
Simulation time 1130158876 ps
CPU time 3.36 seconds
Started Dec 31 01:09:12 PM PST 23
Finished Dec 31 01:09:17 PM PST 23
Peak memory 216876 kb
Host smart-4cc577ba-6b98-4fc9-a891-003170831e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026702151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_byte_transfer.4026702151
Directory /workspace/15.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3795197904
Short name T260
Test name
Test status
Simulation time 178200877 ps
CPU time 4.32 seconds
Started Dec 31 01:09:17 PM PST 23
Finished Dec 31 01:09:23 PM PST 23
Peak memory 221448 kb
Host smart-e4067580-063f-4a2d-b015-57ae3973c38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795197904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3795197904
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2824564092
Short name T1240
Test name
Test status
Simulation time 23485336 ps
CPU time 0.82 seconds
Started Dec 31 01:08:59 PM PST 23
Finished Dec 31 01:09:09 PM PST 23
Peak memory 207512 kb
Host smart-2f595d07-dc6a-4da4-91cb-d0f03938c822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824564092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2824564092
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_dummy_item_extra_dly.2745864145
Short name T1026
Test name
Test status
Simulation time 102366190470 ps
CPU time 308.79 seconds
Started Dec 31 01:08:58 PM PST 23
Finished Dec 31 01:14:15 PM PST 23
Peak memory 327204 kb
Host smart-e74fb1e4-7a02-4551-96b0-a27a55a1bb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745864145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_dummy_item_extra_dly.2745864145
Directory /workspace/15.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/15.spi_device_fifo_full.2704125955
Short name T1030
Test name
Test status
Simulation time 138073170602 ps
CPU time 720.01 seconds
Started Dec 31 01:09:12 PM PST 23
Finished Dec 31 01:21:13 PM PST 23
Peak memory 282316 kb
Host smart-2edfb92c-426a-4f8a-b2e2-e681c21315bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704125955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_fifo_full.2704125955
Directory /workspace/15.spi_device_fifo_full/latest

Test location /workspace/coverage/default/15.spi_device_fifo_underflow_overflow.1386152940
Short name T1271
Test name
Test status
Simulation time 152341897493 ps
CPU time 765.01 seconds
Started Dec 31 01:09:11 PM PST 23
Finished Dec 31 01:21:58 PM PST 23
Peak memory 466240 kb
Host smart-79c00325-7f1c-4adc-bc0c-98e962dc8cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386152940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_fifo_underflow_overf
low.1386152940
Directory /workspace/15.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1843605011
Short name T1608
Test name
Test status
Simulation time 6752830498 ps
CPU time 47.98 seconds
Started Dec 31 01:09:17 PM PST 23
Finished Dec 31 01:10:07 PM PST 23
Peak memory 249716 kb
Host smart-be5c6bb1-74cc-46f7-ba1c-78872182a2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843605011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1843605011
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2488445569
Short name T22
Test name
Test status
Simulation time 49191152938 ps
CPU time 276.05 seconds
Started Dec 31 01:09:15 PM PST 23
Finished Dec 31 01:13:53 PM PST 23
Peak memory 265288 kb
Host smart-35e6491e-0521-4744-9507-1dddc41a6d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488445569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2488445569
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.4151088886
Short name T600
Test name
Test status
Simulation time 3435210783 ps
CPU time 19.26 seconds
Started Dec 31 01:09:18 PM PST 23
Finished Dec 31 01:09:40 PM PST 23
Peak memory 232824 kb
Host smart-f761b227-6be6-475d-b8ab-9c67c4310bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151088886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.4151088886
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3314135359
Short name T771
Test name
Test status
Simulation time 2173921054 ps
CPU time 9.57 seconds
Started Dec 31 01:09:16 PM PST 23
Finished Dec 31 01:09:28 PM PST 23
Peak memory 220932 kb
Host smart-b34a2689-22c1-4358-ac2d-2f380e37895c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314135359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3314135359
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_intr.3843963184
Short name T1625
Test name
Test status
Simulation time 1940892511 ps
CPU time 4.97 seconds
Started Dec 31 01:09:01 PM PST 23
Finished Dec 31 01:09:14 PM PST 23
Peak memory 216864 kb
Host smart-9bbc53eb-1b79-4e24-9744-64e86c2fef01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843963184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intr.3843963184
Directory /workspace/15.spi_device_intr/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.4193659378
Short name T1004
Test name
Test status
Simulation time 25833340516 ps
CPU time 41.84 seconds
Started Dec 31 01:09:17 PM PST 23
Finished Dec 31 01:10:01 PM PST 23
Peak memory 257604 kb
Host smart-bda22a87-24e8-49e9-8873-134125c842bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193659378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.4193659378
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.4056401415
Short name T922
Test name
Test status
Simulation time 56937039 ps
CPU time 1.04 seconds
Started Dec 31 01:09:11 PM PST 23
Finished Dec 31 01:09:14 PM PST 23
Peak memory 218896 kb
Host smart-ac638f4b-4251-4eee-8d5a-390d87630fe5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056401415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.4056401415
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1616733256
Short name T1389
Test name
Test status
Simulation time 1420087366 ps
CPU time 7.55 seconds
Started Dec 31 01:09:17 PM PST 23
Finished Dec 31 01:09:27 PM PST 23
Peak memory 231976 kb
Host smart-d7741541-daea-4423-b7d7-87497f0ad8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616733256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1616733256
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1889407489
Short name T1241
Test name
Test status
Simulation time 1062162972 ps
CPU time 6 seconds
Started Dec 31 01:09:21 PM PST 23
Finished Dec 31 01:09:29 PM PST 23
Peak memory 218316 kb
Host smart-f1674c41-bb9b-44a3-bb4a-8e7e593f06a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889407489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1889407489
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_perf.2833965134
Short name T624
Test name
Test status
Simulation time 6464380089 ps
CPU time 399.96 seconds
Started Dec 31 01:09:11 PM PST 23
Finished Dec 31 01:15:53 PM PST 23
Peak memory 257832 kb
Host smart-065899be-5b01-44c5-a8c7-948026046d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833965134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_perf.2833965134
Directory /workspace/15.spi_device_perf/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.924086878
Short name T508
Test name
Test status
Simulation time 15584572 ps
CPU time 0.74 seconds
Started Dec 31 01:09:14 PM PST 23
Finished Dec 31 01:09:17 PM PST 23
Peak memory 216716 kb
Host smart-ec4a4a15-0704-433e-bb41-ecf2eab6dec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924086878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.924086878
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2116049108
Short name T31
Test name
Test status
Simulation time 1915266771 ps
CPU time 7.95 seconds
Started Dec 31 01:09:21 PM PST 23
Finished Dec 31 01:09:31 PM PST 23
Peak memory 218888 kb
Host smart-effe9eb2-2d33-4057-8152-6f19704519ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2116049108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2116049108
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_rx_async_fifo_reset.1122204592
Short name T762
Test name
Test status
Simulation time 49511740 ps
CPU time 0.97 seconds
Started Dec 31 01:09:21 PM PST 23
Finished Dec 31 01:09:24 PM PST 23
Peak memory 208460 kb
Host smart-0d1dde9c-a422-4225-99bb-aae529564237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122204592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_rx_async_fifo_reset.1122204592
Directory /workspace/15.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/15.spi_device_rx_timeout.3096976606
Short name T584
Test name
Test status
Simulation time 3817030717 ps
CPU time 4.97 seconds
Started Dec 31 01:09:17 PM PST 23
Finished Dec 31 01:09:24 PM PST 23
Peak memory 216916 kb
Host smart-4b5955ce-67bb-4c23-ad2f-3b737f33c85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096976606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_rx_timeout.3096976606
Directory /workspace/15.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/15.spi_device_smoke.1518321038
Short name T750
Test name
Test status
Simulation time 243456269 ps
CPU time 1.28 seconds
Started Dec 31 01:09:00 PM PST 23
Finished Dec 31 01:09:10 PM PST 23
Peak memory 216772 kb
Host smart-9c76c45b-ffc9-441e-b8f7-10ef3fe34605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518321038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_smoke.1518321038
Directory /workspace/15.spi_device_smoke/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.53765763
Short name T1340
Test name
Test status
Simulation time 108846702584 ps
CPU time 566.4 seconds
Started Dec 31 01:09:14 PM PST 23
Finished Dec 31 01:18:44 PM PST 23
Peak memory 303488 kb
Host smart-c984f3e2-c214-4d1f-9742-1919ad7265fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53765763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress
_all.53765763
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3277373895
Short name T330
Test name
Test status
Simulation time 601502148 ps
CPU time 4.65 seconds
Started Dec 31 01:09:21 PM PST 23
Finished Dec 31 01:09:27 PM PST 23
Peak memory 216804 kb
Host smart-a9447e8b-60bd-4e00-abc8-78dd2102d15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277373895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3277373895
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.894311326
Short name T1409
Test name
Test status
Simulation time 2786365895 ps
CPU time 5.42 seconds
Started Dec 31 01:09:17 PM PST 23
Finished Dec 31 01:09:25 PM PST 23
Peak memory 216868 kb
Host smart-4df0f426-eb78-44d8-bc06-77ba7c6e63f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894311326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.894311326
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3655740938
Short name T1418
Test name
Test status
Simulation time 81182821 ps
CPU time 1.9 seconds
Started Dec 31 01:09:18 PM PST 23
Finished Dec 31 01:09:22 PM PST 23
Peak memory 216860 kb
Host smart-062fba05-a5a6-4aa4-ae36-f98b5bc5a2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655740938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3655740938
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.826038816
Short name T746
Test name
Test status
Simulation time 17425971 ps
CPU time 0.76 seconds
Started Dec 31 01:09:13 PM PST 23
Finished Dec 31 01:09:17 PM PST 23
Peak memory 206888 kb
Host smart-34849228-acdd-4803-be56-8d7374ebb642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826038816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.826038816
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_tx_async_fifo_reset.4069529977
Short name T1025
Test name
Test status
Simulation time 18378589 ps
CPU time 0.78 seconds
Started Dec 31 01:09:16 PM PST 23
Finished Dec 31 01:09:19 PM PST 23
Peak memory 208464 kb
Host smart-2ce8acb9-90d5-4c33-8deb-86b7f2223e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069529977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tx_async_fifo_reset.4069529977
Directory /workspace/15.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/15.spi_device_txrx.2842578559
Short name T107
Test name
Test status
Simulation time 54866901250 ps
CPU time 283.73 seconds
Started Dec 31 01:09:00 PM PST 23
Finished Dec 31 01:13:52 PM PST 23
Peak memory 271932 kb
Host smart-66d0618c-a92e-4b7c-8269-cc6d0383239b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842578559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_txrx.2842578559
Directory /workspace/15.spi_device_txrx/latest

Test location /workspace/coverage/default/15.spi_device_upload.1819035608
Short name T724
Test name
Test status
Simulation time 1726119392 ps
CPU time 2.92 seconds
Started Dec 31 01:09:18 PM PST 23
Finished Dec 31 01:09:22 PM PST 23
Peak memory 219284 kb
Host smart-1065540e-96a9-440c-a492-cba7377c8683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819035608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1819035608
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_abort.2128321246
Short name T768
Test name
Test status
Simulation time 16624751 ps
CPU time 0.73 seconds
Started Dec 31 01:09:21 PM PST 23
Finished Dec 31 01:09:24 PM PST 23
Peak memory 206652 kb
Host smart-70e76028-f1dc-4540-9ce5-766858dda998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128321246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_abort.2128321246
Directory /workspace/16.spi_device_abort/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2465605479
Short name T1701
Test name
Test status
Simulation time 27010404 ps
CPU time 0.75 seconds
Started Dec 31 01:09:11 PM PST 23
Finished Dec 31 01:09:13 PM PST 23
Peak memory 206464 kb
Host smart-cddeff33-6309-44b2-a787-a4d5f4a4fab8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465605479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2465605479
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_bit_transfer.1247295406
Short name T1544
Test name
Test status
Simulation time 557027734 ps
CPU time 2.31 seconds
Started Dec 31 01:09:21 PM PST 23
Finished Dec 31 01:09:26 PM PST 23
Peak memory 216780 kb
Host smart-fbe18981-00a5-4dcb-a354-14552b080f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247295406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_bit_transfer.1247295406
Directory /workspace/16.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/16.spi_device_byte_transfer.1605379516
Short name T452
Test name
Test status
Simulation time 78880976 ps
CPU time 3.21 seconds
Started Dec 31 01:09:17 PM PST 23
Finished Dec 31 01:09:22 PM PST 23
Peak memory 216784 kb
Host smart-c8095011-454e-4507-9bfa-8f5294d2b48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605379516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_byte_transfer.1605379516
Directory /workspace/16.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3574627242
Short name T1408
Test name
Test status
Simulation time 283429573 ps
CPU time 2.86 seconds
Started Dec 31 01:09:21 PM PST 23
Finished Dec 31 01:09:26 PM PST 23
Peak memory 241420 kb
Host smart-c31810cd-bb1f-40da-a863-7483a6d1422d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574627242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3574627242
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.384169529
Short name T1476
Test name
Test status
Simulation time 44868827 ps
CPU time 0.78 seconds
Started Dec 31 01:09:10 PM PST 23
Finished Dec 31 01:09:12 PM PST 23
Peak memory 206576 kb
Host smart-39e45df1-0c9b-44f6-b7eb-795d6b0e211c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384169529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.384169529
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_dummy_item_extra_dly.2528480527
Short name T1119
Test name
Test status
Simulation time 21115344366 ps
CPU time 342.96 seconds
Started Dec 31 01:09:12 PM PST 23
Finished Dec 31 01:14:56 PM PST 23
Peak memory 252160 kb
Host smart-724c4296-0b1e-4a92-bb6f-54c405c8a052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528480527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_dummy_item_extra_dly.2528480527
Directory /workspace/16.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/16.spi_device_extreme_fifo_size.3011182641
Short name T1354
Test name
Test status
Simulation time 40843421768 ps
CPU time 108.87 seconds
Started Dec 31 01:09:21 PM PST 23
Finished Dec 31 01:11:12 PM PST 23
Peak memory 233396 kb
Host smart-1e59551b-9ffb-46e9-8074-54e70796ffef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011182641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_extreme_fifo_size.3011182641
Directory /workspace/16.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/16.spi_device_fifo_full.3216557077
Short name T469
Test name
Test status
Simulation time 47300954924 ps
CPU time 556.72 seconds
Started Dec 31 01:09:17 PM PST 23
Finished Dec 31 01:18:36 PM PST 23
Peak memory 289028 kb
Host smart-bf979f8b-6e8a-42f3-912b-3dab164b66c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216557077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_fifo_full.3216557077
Directory /workspace/16.spi_device_fifo_full/latest

Test location /workspace/coverage/default/16.spi_device_fifo_underflow_overflow.2324740766
Short name T47
Test name
Test status
Simulation time 150433158351 ps
CPU time 1132.01 seconds
Started Dec 31 01:09:12 PM PST 23
Finished Dec 31 01:28:06 PM PST 23
Peak memory 476428 kb
Host smart-68b859e0-b637-4560-9f73-2cccdfe0a95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324740766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_fifo_underflow_overf
low.2324740766
Directory /workspace/16.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.929104578
Short name T1533
Test name
Test status
Simulation time 17959674954 ps
CPU time 94.45 seconds
Started Dec 31 01:09:29 PM PST 23
Finished Dec 31 01:11:07 PM PST 23
Peak memory 250296 kb
Host smart-1deec78d-1b79-4b84-959a-cd15bfdf95c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929104578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.929104578
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2138404715
Short name T1262
Test name
Test status
Simulation time 343646363206 ps
CPU time 272.59 seconds
Started Dec 31 01:09:14 PM PST 23
Finished Dec 31 01:13:50 PM PST 23
Peak memory 265376 kb
Host smart-a457d6a3-9e46-49bd-b02d-ee2db4d34c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138404715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2138404715
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1245965734
Short name T1531
Test name
Test status
Simulation time 10106440970 ps
CPU time 28.11 seconds
Started Dec 31 01:09:27 PM PST 23
Finished Dec 31 01:10:01 PM PST 23
Peak memory 248664 kb
Host smart-b1555de7-c716-4141-92db-81b7af3b1321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245965734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1245965734
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1554358012
Short name T980
Test name
Test status
Simulation time 185103788 ps
CPU time 4.24 seconds
Started Dec 31 01:09:13 PM PST 23
Finished Dec 31 01:09:20 PM PST 23
Peak memory 241512 kb
Host smart-c1a2ae3f-7cc6-4c73-bcbb-5e6806cd8bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554358012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1554358012
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_intr.3288493395
Short name T903
Test name
Test status
Simulation time 6614336170 ps
CPU time 15.25 seconds
Started Dec 31 01:09:17 PM PST 23
Finished Dec 31 01:09:35 PM PST 23
Peak memory 217180 kb
Host smart-b7efd0d9-1a20-401d-b3a4-8d40b50ac7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288493395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intr.3288493395
Directory /workspace/16.spi_device_intr/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1060622898
Short name T1391
Test name
Test status
Simulation time 2880240116 ps
CPU time 5.54 seconds
Started Dec 31 01:09:27 PM PST 23
Finished Dec 31 01:09:38 PM PST 23
Peak memory 218868 kb
Host smart-7386047e-d94a-4b80-96e1-389280369b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060622898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1060622898
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.939790897
Short name T1584
Test name
Test status
Simulation time 33991836 ps
CPU time 1.04 seconds
Started Dec 31 01:09:10 PM PST 23
Finished Dec 31 01:09:12 PM PST 23
Peak memory 218836 kb
Host smart-564e38e5-9dd1-4933-acfc-02c7334b7470
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939790897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.939790897
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1662200671
Short name T702
Test name
Test status
Simulation time 23663099831 ps
CPU time 26.34 seconds
Started Dec 31 01:09:26 PM PST 23
Finished Dec 31 01:09:59 PM PST 23
Peak memory 250692 kb
Host smart-635be7a3-2f73-4fa1-ab7e-4b99a3d95531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662200671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1662200671
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2066257094
Short name T1375
Test name
Test status
Simulation time 21998518348 ps
CPU time 17.8 seconds
Started Dec 31 01:09:12 PM PST 23
Finished Dec 31 01:09:31 PM PST 23
Peak memory 219636 kb
Host smart-cdccd3e4-8b19-4f7f-aa85-af44629a71f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066257094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2066257094
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_perf.2026736952
Short name T1175
Test name
Test status
Simulation time 20032120883 ps
CPU time 315.55 seconds
Started Dec 31 01:09:16 PM PST 23
Finished Dec 31 01:14:34 PM PST 23
Peak memory 240692 kb
Host smart-0378a92b-19f0-4dad-a5c1-887ecf55ddc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026736952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_perf.2026736952
Directory /workspace/16.spi_device_perf/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.3638711038
Short name T1496
Test name
Test status
Simulation time 71864930 ps
CPU time 0.73 seconds
Started Dec 31 01:09:13 PM PST 23
Finished Dec 31 01:09:16 PM PST 23
Peak memory 216580 kb
Host smart-f30309f0-83ef-44f7-8f8e-d746eeb3bfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638711038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.3638711038
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.376828416
Short name T1131
Test name
Test status
Simulation time 418859217 ps
CPU time 3.72 seconds
Started Dec 31 01:09:21 PM PST 23
Finished Dec 31 01:09:27 PM PST 23
Peak memory 220240 kb
Host smart-b28539df-5492-475d-ad2f-6a21000d2945
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=376828416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.376828416
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_rx_async_fifo_reset.2631733772
Short name T1291
Test name
Test status
Simulation time 22033191 ps
CPU time 0.89 seconds
Started Dec 31 01:09:21 PM PST 23
Finished Dec 31 01:09:24 PM PST 23
Peak memory 208376 kb
Host smart-23f33ddf-1205-434c-8f06-bd787e108451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631733772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_rx_async_fifo_reset.2631733772
Directory /workspace/16.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/16.spi_device_rx_timeout.1335123699
Short name T675
Test name
Test status
Simulation time 1044422594 ps
CPU time 6.41 seconds
Started Dec 31 01:09:13 PM PST 23
Finished Dec 31 01:09:22 PM PST 23
Peak memory 216648 kb
Host smart-892a5a5e-58d4-42a1-b931-fef5c580f706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335123699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_rx_timeout.1335123699
Directory /workspace/16.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/16.spi_device_smoke.3996193117
Short name T1676
Test name
Test status
Simulation time 19295715 ps
CPU time 1.07 seconds
Started Dec 31 01:09:17 PM PST 23
Finished Dec 31 01:09:20 PM PST 23
Peak memory 216508 kb
Host smart-c0eed7a3-9ed1-4423-b4d7-b374db973ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996193117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_smoke.3996193117
Directory /workspace/16.spi_device_smoke/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.102248302
Short name T1211
Test name
Test status
Simulation time 350867710629 ps
CPU time 2899.24 seconds
Started Dec 31 01:09:29 PM PST 23
Finished Dec 31 01:57:52 PM PST 23
Peak memory 374256 kb
Host smart-80bbf651-1fed-40bc-9ab7-242b17763f7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102248302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.102248302
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1691182560
Short name T1341
Test name
Test status
Simulation time 8018021230 ps
CPU time 60.28 seconds
Started Dec 31 01:09:22 PM PST 23
Finished Dec 31 01:10:24 PM PST 23
Peak memory 216956 kb
Host smart-fe3a9e3c-fb41-4c03-bee2-9fb439fa1808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691182560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1691182560
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1715716278
Short name T539
Test name
Test status
Simulation time 16865123888 ps
CPU time 24.54 seconds
Started Dec 31 01:09:13 PM PST 23
Finished Dec 31 01:09:40 PM PST 23
Peak memory 216880 kb
Host smart-53eb8b19-8fd8-444b-bdcc-6fb58f5291cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715716278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1715716278
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2883548430
Short name T1091
Test name
Test status
Simulation time 354790422 ps
CPU time 1.88 seconds
Started Dec 31 01:09:27 PM PST 23
Finished Dec 31 01:09:35 PM PST 23
Peak memory 218324 kb
Host smart-bc9d39aa-e7cb-43fc-b81d-8b1f71b230ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883548430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2883548430
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4290780390
Short name T975
Test name
Test status
Simulation time 27264875 ps
CPU time 0.79 seconds
Started Dec 31 01:09:29 PM PST 23
Finished Dec 31 01:09:34 PM PST 23
Peak memory 206912 kb
Host smart-02a580bf-67fa-4d3c-b151-d64f1bb12480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290780390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4290780390
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_txrx.497056275
Short name T1174
Test name
Test status
Simulation time 179128631746 ps
CPU time 569.95 seconds
Started Dec 31 01:09:21 PM PST 23
Finished Dec 31 01:18:54 PM PST 23
Peak memory 249696 kb
Host smart-5a505935-0522-401c-ac05-6c698e806e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497056275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_txrx.497056275
Directory /workspace/16.spi_device_txrx/latest

Test location /workspace/coverage/default/16.spi_device_upload.664172709
Short name T1370
Test name
Test status
Simulation time 291359109 ps
CPU time 4.68 seconds
Started Dec 31 01:09:22 PM PST 23
Finished Dec 31 01:09:29 PM PST 23
Peak memory 219276 kb
Host smart-ba933c57-caa9-49cb-96b7-c5b38fa41983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664172709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.664172709
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_abort.3431915028
Short name T1372
Test name
Test status
Simulation time 59286607 ps
CPU time 0.74 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:09:47 PM PST 23
Peak memory 206656 kb
Host smart-3b1a65bd-e9ac-4df5-adf7-6c5fd2876f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431915028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_abort.3431915028
Directory /workspace/17.spi_device_abort/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.4212497872
Short name T959
Test name
Test status
Simulation time 57516848 ps
CPU time 0.71 seconds
Started Dec 31 01:09:41 PM PST 23
Finished Dec 31 01:09:51 PM PST 23
Peak memory 206492 kb
Host smart-d3ba6704-9848-425e-951c-33ba19be6d2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212497872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
4212497872
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_bit_transfer.3916084976
Short name T700
Test name
Test status
Simulation time 184386576 ps
CPU time 2.6 seconds
Started Dec 31 01:09:35 PM PST 23
Finished Dec 31 01:09:40 PM PST 23
Peak memory 216844 kb
Host smart-bb81941d-947d-4b6b-970b-3c11e098a475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916084976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_bit_transfer.3916084976
Directory /workspace/17.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/17.spi_device_byte_transfer.3520045471
Short name T1325
Test name
Test status
Simulation time 937004714 ps
CPU time 2.92 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:09:49 PM PST 23
Peak memory 216820 kb
Host smart-73f64dfe-eec0-41e6-ae5e-88ee344001ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520045471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_byte_transfer.3520045471
Directory /workspace/17.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.805231232
Short name T1046
Test name
Test status
Simulation time 352031634 ps
CPU time 4.08 seconds
Started Dec 31 01:09:42 PM PST 23
Finished Dec 31 01:09:56 PM PST 23
Peak memory 238276 kb
Host smart-dd92b5df-08fb-4f20-8330-55c543c50e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805231232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.805231232
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2369986112
Short name T515
Test name
Test status
Simulation time 50335976 ps
CPU time 0.78 seconds
Started Dec 31 01:09:22 PM PST 23
Finished Dec 31 01:09:25 PM PST 23
Peak memory 206548 kb
Host smart-b2a9a3f4-6237-4793-a118-0eaffdfd6173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369986112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2369986112
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_dummy_item_extra_dly.2026672031
Short name T1168
Test name
Test status
Simulation time 20281542755 ps
CPU time 163.27 seconds
Started Dec 31 01:09:31 PM PST 23
Finished Dec 31 01:12:17 PM PST 23
Peak memory 255692 kb
Host smart-a7918927-d311-4ad4-a944-8adf7f379273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026672031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_dummy_item_extra_dly.2026672031
Directory /workspace/17.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/17.spi_device_extreme_fifo_size.616737508
Short name T38
Test name
Test status
Simulation time 204472020785 ps
CPU time 908.56 seconds
Started Dec 31 01:09:27 PM PST 23
Finished Dec 31 01:24:41 PM PST 23
Peak memory 219160 kb
Host smart-72b65503-8fda-4077-a7ab-59a6e035af17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616737508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_extreme_fifo_size.616737508
Directory /workspace/17.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/17.spi_device_fifo_full.2667016095
Short name T1309
Test name
Test status
Simulation time 140104660560 ps
CPU time 2079.23 seconds
Started Dec 31 01:09:15 PM PST 23
Finished Dec 31 01:43:57 PM PST 23
Peak memory 267820 kb
Host smart-0b50c736-8d4b-4b27-8f8d-99f4473ce5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667016095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_fifo_full.2667016095
Directory /workspace/17.spi_device_fifo_full/latest

Test location /workspace/coverage/default/17.spi_device_fifo_underflow_overflow.3177877412
Short name T1014
Test name
Test status
Simulation time 16792260538 ps
CPU time 142.97 seconds
Started Dec 31 01:09:21 PM PST 23
Finished Dec 31 01:11:47 PM PST 23
Peak memory 301144 kb
Host smart-c0eaffaf-77cb-4e37-98aa-600eda0b1fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177877412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_fifo_underflow_overf
low.3177877412
Directory /workspace/17.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3911471863
Short name T819
Test name
Test status
Simulation time 2995368584 ps
CPU time 46.73 seconds
Started Dec 31 01:09:36 PM PST 23
Finished Dec 31 01:10:25 PM PST 23
Peak memory 250516 kb
Host smart-cca4e4f4-c170-4a8f-9011-c0491cdbde6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911471863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3911471863
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2017506540
Short name T1633
Test name
Test status
Simulation time 192167668004 ps
CPU time 306.3 seconds
Started Dec 31 01:09:36 PM PST 23
Finished Dec 31 01:14:44 PM PST 23
Peak memory 254992 kb
Host smart-9a62e127-b3a6-42f2-b05a-90e876a2680e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017506540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2017506540
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1179606556
Short name T1556
Test name
Test status
Simulation time 69671326980 ps
CPU time 131.43 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:11:54 PM PST 23
Peak memory 225168 kb
Host smart-96f8cea7-40e3-494b-b517-5553868aa609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179606556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1179606556
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1436858432
Short name T1295
Test name
Test status
Simulation time 675390358 ps
CPU time 10.19 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:09:56 PM PST 23
Peak memory 223712 kb
Host smart-60341f99-2e1d-4272-8d10-08cdd9326f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436858432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1436858432
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.710621271
Short name T1362
Test name
Test status
Simulation time 826360760 ps
CPU time 5.1 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:09:51 PM PST 23
Peak memory 237960 kb
Host smart-6166b6dd-29dd-4301-b42e-f0dae2982687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710621271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.710621271
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3437503580
Short name T598
Test name
Test status
Simulation time 281325359227 ps
CPU time 46 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:10:30 PM PST 23
Peak memory 231164 kb
Host smart-5c20e941-9ec1-41d9-ad84-38028e62c24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437503580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3437503580
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2285932616
Short name T36
Test name
Test status
Simulation time 25478654 ps
CPU time 1.06 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:09:45 PM PST 23
Peak memory 218876 kb
Host smart-697540a5-513d-43e4-b4cb-09350a810faa
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285932616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2285932616
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1060439383
Short name T877
Test name
Test status
Simulation time 2747383308 ps
CPU time 9.16 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:09:53 PM PST 23
Peak memory 239648 kb
Host smart-085221e4-513f-4073-bbf6-ea6869a3319a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060439383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1060439383
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2555839694
Short name T1618
Test name
Test status
Simulation time 32066295803 ps
CPU time 28.91 seconds
Started Dec 31 01:09:35 PM PST 23
Finished Dec 31 01:10:06 PM PST 23
Peak memory 241372 kb
Host smart-6cb7f568-022d-436b-856b-a9b1a7aa2a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555839694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2555839694
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_perf.988038012
Short name T615
Test name
Test status
Simulation time 16324232590 ps
CPU time 272.36 seconds
Started Dec 31 01:09:14 PM PST 23
Finished Dec 31 01:13:49 PM PST 23
Peak memory 249056 kb
Host smart-5f8500f3-ff76-45ed-862d-6e0402ba383f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988038012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_perf.988038012
Directory /workspace/17.spi_device_perf/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.2042312980
Short name T75
Test name
Test status
Simulation time 16199669 ps
CPU time 0.74 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:09:45 PM PST 23
Peak memory 216620 kb
Host smart-d6566b85-7127-4e58-a34f-13ac2f1f3565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042312980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.2042312980
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1331215942
Short name T1622
Test name
Test status
Simulation time 290850569 ps
CPU time 3.5 seconds
Started Dec 31 01:09:36 PM PST 23
Finished Dec 31 01:09:41 PM PST 23
Peak memory 221468 kb
Host smart-bd9cd28a-e028-421c-b397-99b7ae4e79f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1331215942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1331215942
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_rx_async_fifo_reset.4275460381
Short name T503
Test name
Test status
Simulation time 19974396 ps
CPU time 0.86 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:09:45 PM PST 23
Peak memory 208384 kb
Host smart-eb750748-9685-45f8-9797-a0d0c68c1081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275460381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_rx_async_fifo_reset.4275460381
Directory /workspace/17.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/17.spi_device_rx_timeout.2600221582
Short name T506
Test name
Test status
Simulation time 663571087 ps
CPU time 6.19 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:09:52 PM PST 23
Peak memory 216796 kb
Host smart-44c2ebd7-f7ba-4e16-a6dc-57d8eaa11008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600221582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_rx_timeout.2600221582
Directory /workspace/17.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/17.spi_device_smoke.2273796320
Short name T512
Test name
Test status
Simulation time 221251431 ps
CPU time 1.17 seconds
Started Dec 31 01:09:12 PM PST 23
Finished Dec 31 01:09:16 PM PST 23
Peak memory 216592 kb
Host smart-25454187-5647-46c5-a491-584f037543c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273796320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_smoke.2273796320
Directory /workspace/17.spi_device_smoke/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1330757176
Short name T320
Test name
Test status
Simulation time 248794222163 ps
CPU time 1804.21 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:39:49 PM PST 23
Peak memory 471288 kb
Host smart-ff8d4f41-06e7-4a9f-af58-1ace1c4d8144
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330757176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1330757176
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1974146302
Short name T596
Test name
Test status
Simulation time 5605066087 ps
CPU time 22 seconds
Started Dec 31 01:09:40 PM PST 23
Finished Dec 31 01:10:08 PM PST 23
Peak memory 216852 kb
Host smart-eb07089f-ec3a-47b3-b4f3-d3496261562e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974146302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1974146302
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3638482502
Short name T603
Test name
Test status
Simulation time 1404481456 ps
CPU time 3.67 seconds
Started Dec 31 01:09:35 PM PST 23
Finished Dec 31 01:09:41 PM PST 23
Peak memory 216732 kb
Host smart-5f8c1dbd-6f1b-4115-897c-b1b47d73341b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638482502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3638482502
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.669805035
Short name T89
Test name
Test status
Simulation time 152840263 ps
CPU time 0.87 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:09:44 PM PST 23
Peak memory 206968 kb
Host smart-605c889e-41d7-445f-9338-6bfbf0b06120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669805035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.669805035
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_tx_async_fifo_reset.1112254287
Short name T1779
Test name
Test status
Simulation time 21411011 ps
CPU time 0.8 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:09:43 PM PST 23
Peak memory 208344 kb
Host smart-5ae33394-be44-4f12-b5cf-9923cd435700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112254287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tx_async_fifo_reset.1112254287
Directory /workspace/17.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/17.spi_device_txrx.1486911676
Short name T635
Test name
Test status
Simulation time 28098764948 ps
CPU time 81.03 seconds
Started Dec 31 01:09:22 PM PST 23
Finished Dec 31 01:10:45 PM PST 23
Peak memory 256160 kb
Host smart-933f6afb-e6fa-435e-83c2-fd43a379fa16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486911676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_txrx.1486911676
Directory /workspace/17.spi_device_txrx/latest

Test location /workspace/coverage/default/17.spi_device_upload.2932911909
Short name T245
Test name
Test status
Simulation time 447933452 ps
CPU time 6.18 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:09:52 PM PST 23
Peak memory 225080 kb
Host smart-d18b4f96-639b-48ec-a40a-ee4a602ef5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932911909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2932911909
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_abort.320680297
Short name T606
Test name
Test status
Simulation time 51544573 ps
CPU time 0.75 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:09:43 PM PST 23
Peak memory 206644 kb
Host smart-42d585df-8dce-4014-a12b-3167bc239e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320680297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_abort.320680297
Directory /workspace/18.spi_device_abort/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1968571233
Short name T1339
Test name
Test status
Simulation time 17024152 ps
CPU time 0.79 seconds
Started Dec 31 01:09:46 PM PST 23
Finished Dec 31 01:09:56 PM PST 23
Peak memory 206516 kb
Host smart-441312ac-13bb-4586-9033-86d5b9a76fc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968571233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1968571233
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_bit_transfer.2666976395
Short name T1467
Test name
Test status
Simulation time 663433087 ps
CPU time 2.51 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:09:46 PM PST 23
Peak memory 216884 kb
Host smart-8c00b430-84dd-4344-95d5-6ea2543df439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666976395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_bit_transfer.2666976395
Directory /workspace/18.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/18.spi_device_byte_transfer.227760985
Short name T856
Test name
Test status
Simulation time 2591642639 ps
CPU time 2.73 seconds
Started Dec 31 01:09:42 PM PST 23
Finished Dec 31 01:09:54 PM PST 23
Peak memory 216904 kb
Host smart-089a0228-3f60-4383-8613-bbcfb840cc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227760985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_byte_transfer.227760985
Directory /workspace/18.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2516500380
Short name T834
Test name
Test status
Simulation time 4527281299 ps
CPU time 3.5 seconds
Started Dec 31 01:09:36 PM PST 23
Finished Dec 31 01:09:43 PM PST 23
Peak memory 218500 kb
Host smart-2887496a-0c8e-4d20-80a1-312e5aedd1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516500380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2516500380
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.914511147
Short name T943
Test name
Test status
Simulation time 20157143 ps
CPU time 0.82 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:09:41 PM PST 23
Peak memory 207592 kb
Host smart-95cb2b37-8fbd-4189-8675-81009c5e64c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914511147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.914511147
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_dummy_item_extra_dly.462407113
Short name T1572
Test name
Test status
Simulation time 303041725201 ps
CPU time 1086.42 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:27:51 PM PST 23
Peak memory 345324 kb
Host smart-202e0cbc-4ac8-4455-aa8a-7baf93215836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462407113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_dummy_item_extra_dly.462407113
Directory /workspace/18.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/18.spi_device_extreme_fifo_size.850388591
Short name T253
Test name
Test status
Simulation time 194323571057 ps
CPU time 2157.31 seconds
Started Dec 31 01:09:36 PM PST 23
Finished Dec 31 01:45:36 PM PST 23
Peak memory 219020 kb
Host smart-34f70a5e-8696-474a-b8df-e7191e52f6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850388591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_extreme_fifo_size.850388591
Directory /workspace/18.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/18.spi_device_fifo_full.3367864182
Short name T866
Test name
Test status
Simulation time 32176335266 ps
CPU time 1935.17 seconds
Started Dec 31 01:09:36 PM PST 23
Finished Dec 31 01:41:55 PM PST 23
Peak memory 320372 kb
Host smart-7e4bcef4-4790-49f7-89b0-77de67a53232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367864182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_fifo_full.3367864182
Directory /workspace/18.spi_device_fifo_full/latest

Test location /workspace/coverage/default/18.spi_device_fifo_underflow_overflow.479286831
Short name T571
Test name
Test status
Simulation time 64889493767 ps
CPU time 180.44 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:12:46 PM PST 23
Peak memory 296600 kb
Host smart-14f11d45-14b2-4581-9b95-71757553efe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479286831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_fifo_underflow_overfl
ow.479286831
Directory /workspace/18.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.72972024
Short name T827
Test name
Test status
Simulation time 8100929807 ps
CPU time 93.78 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:11:19 PM PST 23
Peak memory 255240 kb
Host smart-d72b7c1f-08bd-4320-bae9-fa849991c9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72972024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.72972024
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2297732664
Short name T1366
Test name
Test status
Simulation time 6961943346 ps
CPU time 20.2 seconds
Started Dec 31 01:09:35 PM PST 23
Finished Dec 31 01:09:57 PM PST 23
Peak memory 241476 kb
Host smart-1b093fcf-169b-441a-b050-8493479c8145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297732664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2297732664
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3809312715
Short name T1623
Test name
Test status
Simulation time 711698155 ps
CPU time 4.61 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:09:50 PM PST 23
Peak memory 218468 kb
Host smart-55b0eb87-b9d0-4cea-89d7-32fccc79b697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809312715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3809312715
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_intr.2424497536
Short name T1470
Test name
Test status
Simulation time 4739850821 ps
CPU time 20.98 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:10:04 PM PST 23
Peak memory 224980 kb
Host smart-59787a51-b76a-4d74-bd46-42a65f7d01f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424497536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intr.2424497536
Directory /workspace/18.spi_device_intr/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.4007810721
Short name T1261
Test name
Test status
Simulation time 2129287443 ps
CPU time 8.36 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:09:54 PM PST 23
Peak memory 223812 kb
Host smart-8ee86f16-65b9-42e7-b724-d53a51aad64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007810721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.4007810721
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1344337876
Short name T1504
Test name
Test status
Simulation time 109120174 ps
CPU time 1.08 seconds
Started Dec 31 01:09:36 PM PST 23
Finished Dec 31 01:09:39 PM PST 23
Peak memory 219000 kb
Host smart-03d738c6-5ad9-4215-aa63-484a42bb2067
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344337876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1344337876
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2801630748
Short name T283
Test name
Test status
Simulation time 1046525191 ps
CPU time 7.76 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:09:52 PM PST 23
Peak memory 240532 kb
Host smart-c172c9af-c7ce-4c9c-a0e7-f06d497d29a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801630748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2801630748
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1319576600
Short name T1284
Test name
Test status
Simulation time 13022456525 ps
CPU time 24.35 seconds
Started Dec 31 01:09:35 PM PST 23
Finished Dec 31 01:10:01 PM PST 23
Peak memory 227596 kb
Host smart-a6f22c3c-9cb5-4e9d-937c-52f7e92eecbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319576600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1319576600
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_perf.1923800991
Short name T998
Test name
Test status
Simulation time 23828099725 ps
CPU time 857.8 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:24:03 PM PST 23
Peak memory 318660 kb
Host smart-65e4fd44-4e3f-4c16-9edb-32599bb825d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923800991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_perf.1923800991
Directory /workspace/18.spi_device_perf/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.2007216487
Short name T1431
Test name
Test status
Simulation time 39861239 ps
CPU time 0.71 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:09:43 PM PST 23
Peak memory 216720 kb
Host smart-15e88ba4-e385-4902-88ea-297b23523066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007216487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.2007216487
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2435895707
Short name T9
Test name
Test status
Simulation time 2268320357 ps
CPU time 5.11 seconds
Started Dec 31 01:09:42 PM PST 23
Finished Dec 31 01:09:58 PM PST 23
Peak memory 234236 kb
Host smart-c0ba1e5d-6175-4640-85c2-f603bbfb5d77
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2435895707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2435895707
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_rx_async_fifo_reset.516070823
Short name T33
Test name
Test status
Simulation time 23473520 ps
CPU time 0.89 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:09:45 PM PST 23
Peak memory 208424 kb
Host smart-76ab586d-be96-4aa7-a6b3-be51cfeba83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516070823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_rx_async_fifo_reset.516070823
Directory /workspace/18.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/18.spi_device_rx_timeout.3244907595
Short name T1629
Test name
Test status
Simulation time 1105636079 ps
CPU time 5.87 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:09:49 PM PST 23
Peak memory 216832 kb
Host smart-1e1708a4-bd80-4560-b127-7c19bb717427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244907595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_rx_timeout.3244907595
Directory /workspace/18.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/18.spi_device_smoke.1613382898
Short name T602
Test name
Test status
Simulation time 31999255 ps
CPU time 0.96 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:09:43 PM PST 23
Peak memory 208320 kb
Host smart-66325c0c-d8e6-4def-892a-155f38b9bb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613382898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_smoke.1613382898
Directory /workspace/18.spi_device_smoke/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2741864625
Short name T1369
Test name
Test status
Simulation time 65379052008 ps
CPU time 539.97 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:18:42 PM PST 23
Peak memory 442900 kb
Host smart-2bac6fb1-4a36-4a87-8847-dd56d6272781
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741864625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2741864625
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2288236333
Short name T91
Test name
Test status
Simulation time 10264626352 ps
CPU time 36.48 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:10:22 PM PST 23
Peak memory 216948 kb
Host smart-7c2674f6-497e-42c9-9468-f5a1c42984dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288236333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2288236333
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.259700668
Short name T1492
Test name
Test status
Simulation time 2702346165 ps
CPU time 5.85 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:09:48 PM PST 23
Peak memory 216856 kb
Host smart-04b5adae-d89d-4174-9a45-a674a4df02a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259700668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.259700668
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.117558426
Short name T94
Test name
Test status
Simulation time 81815199 ps
CPU time 1.2 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:09:44 PM PST 23
Peak memory 216560 kb
Host smart-cc2aedf5-fcb7-4929-be14-59289d23af27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117558426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.117558426
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.150966170
Short name T1637
Test name
Test status
Simulation time 105830335 ps
CPU time 1.09 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:09:43 PM PST 23
Peak memory 208036 kb
Host smart-41d85d0d-b7b2-4cff-85e6-392fc15bcd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150966170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.150966170
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_tx_async_fifo_reset.1683381999
Short name T870
Test name
Test status
Simulation time 28004829 ps
CPU time 0.76 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:09:46 PM PST 23
Peak memory 208444 kb
Host smart-81546299-cf20-4697-8f94-78f9e8f512f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683381999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tx_async_fifo_reset.1683381999
Directory /workspace/18.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/18.spi_device_txrx.2009057693
Short name T258
Test name
Test status
Simulation time 266585217135 ps
CPU time 534.04 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:18:36 PM PST 23
Peak memory 267264 kb
Host smart-ecc427ea-f9d3-4e27-8438-f9fc814b4793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009057693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_txrx.2009057693
Directory /workspace/18.spi_device_txrx/latest

Test location /workspace/coverage/default/18.spi_device_upload.3527191834
Short name T1564
Test name
Test status
Simulation time 37913469523 ps
CPU time 30.09 seconds
Started Dec 31 01:09:40 PM PST 23
Finished Dec 31 01:10:16 PM PST 23
Peak memory 246468 kb
Host smart-486b3f06-091b-407d-8a28-ee32ac4acc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527191834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3527191834
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_abort.541733960
Short name T548
Test name
Test status
Simulation time 17300073 ps
CPU time 0.76 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:09:41 PM PST 23
Peak memory 206552 kb
Host smart-dc979ad4-ce67-45e9-9553-2e8dd6ef7b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541733960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_abort.541733960
Directory /workspace/19.spi_device_abort/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3286642418
Short name T453
Test name
Test status
Simulation time 59716568 ps
CPU time 0.74 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:09:43 PM PST 23
Peak memory 206480 kb
Host smart-eb5fc9c0-1866-4a6f-9295-a1375f59bf69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286642418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3286642418
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_bit_transfer.2015745099
Short name T1553
Test name
Test status
Simulation time 312744922 ps
CPU time 2.55 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:09:45 PM PST 23
Peak memory 216780 kb
Host smart-12d2d9c5-33ac-49fc-b701-44e63ba31b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015745099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_bit_transfer.2015745099
Directory /workspace/19.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/19.spi_device_byte_transfer.553784924
Short name T931
Test name
Test status
Simulation time 2565035580 ps
CPU time 3.09 seconds
Started Dec 31 01:09:44 PM PST 23
Finished Dec 31 01:09:57 PM PST 23
Peak memory 216860 kb
Host smart-ba440526-bcda-4fea-a199-a88f714c9027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553784924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_byte_transfer.553784924
Directory /workspace/19.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.931557801
Short name T626
Test name
Test status
Simulation time 605321987 ps
CPU time 4.82 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:09:47 PM PST 23
Peak memory 225056 kb
Host smart-23a49ac3-4fd8-4c73-a710-091ed85fb48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931557801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.931557801
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.4112900816
Short name T594
Test name
Test status
Simulation time 25014349 ps
CPU time 0.8 seconds
Started Dec 31 01:09:41 PM PST 23
Finished Dec 31 01:09:52 PM PST 23
Peak memory 207628 kb
Host smart-52a156dd-6812-4a1a-ba47-311b631834c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112900816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.4112900816
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_dummy_item_extra_dly.2314977477
Short name T1692
Test name
Test status
Simulation time 25303308756 ps
CPU time 98.01 seconds
Started Dec 31 01:09:35 PM PST 23
Finished Dec 31 01:11:15 PM PST 23
Peak memory 241144 kb
Host smart-0594cb79-fc01-4228-87ce-e23b3308b26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314977477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_dummy_item_extra_dly.2314977477
Directory /workspace/19.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/19.spi_device_extreme_fifo_size.111133887
Short name T847
Test name
Test status
Simulation time 32350881314 ps
CPU time 51.35 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:10:34 PM PST 23
Peak memory 240556 kb
Host smart-21057a13-f293-438c-9f93-2559792efbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111133887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_extreme_fifo_size.111133887
Directory /workspace/19.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/19.spi_device_fifo_full.1319689608
Short name T1498
Test name
Test status
Simulation time 104368887597 ps
CPU time 1515.88 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:35:02 PM PST 23
Peak memory 251296 kb
Host smart-9c167cac-5459-49d2-af64-6b8b8aba1702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319689608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_fifo_full.1319689608
Directory /workspace/19.spi_device_fifo_full/latest

Test location /workspace/coverage/default/19.spi_device_fifo_underflow_overflow.1188668690
Short name T1529
Test name
Test status
Simulation time 12729431990 ps
CPU time 276.65 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:14:19 PM PST 23
Peak memory 342512 kb
Host smart-59fa1c4e-9682-46a2-8aad-a9776757ea6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188668690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_fifo_underflow_overf
low.1188668690
Directory /workspace/19.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.546974623
Short name T14
Test name
Test status
Simulation time 6276132647 ps
CPU time 92.63 seconds
Started Dec 31 01:09:36 PM PST 23
Finished Dec 31 01:11:10 PM PST 23
Peak memory 256808 kb
Host smart-09771f19-2cef-4410-95a3-f4ba3e9b288e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546974623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.546974623
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1696564956
Short name T1394
Test name
Test status
Simulation time 4742890297 ps
CPU time 97.67 seconds
Started Dec 31 01:09:36 PM PST 23
Finished Dec 31 01:11:16 PM PST 23
Peak memory 263920 kb
Host smart-978cb5b6-b986-46cb-a294-6deec614ae0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696564956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1696564956
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2586585254
Short name T1107
Test name
Test status
Simulation time 14945846681 ps
CPU time 18.82 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:10:00 PM PST 23
Peak memory 248388 kb
Host smart-7932b2b2-2c9d-4622-a633-85abd4fe26b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586585254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2586585254
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.903760443
Short name T210
Test name
Test status
Simulation time 99897594 ps
CPU time 4.03 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:09:46 PM PST 23
Peak memory 238344 kb
Host smart-3a7ae29a-fe60-4b42-8a5d-0a9f99f177f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903760443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.903760443
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_intr.309666482
Short name T647
Test name
Test status
Simulation time 15800213600 ps
CPU time 82.7 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:11:06 PM PST 23
Peak memory 241488 kb
Host smart-7dc6a540-995d-42a6-b2a8-07865234c78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309666482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intr.309666482
Directory /workspace/19.spi_device_intr/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2694431345
Short name T261
Test name
Test status
Simulation time 22410786083 ps
CPU time 34.3 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:10:18 PM PST 23
Peak memory 234336 kb
Host smart-5edb7356-d505-4e77-9f83-81c0d2189d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694431345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2694431345
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1887098830
Short name T707
Test name
Test status
Simulation time 106446984 ps
CPU time 1.12 seconds
Started Dec 31 01:09:43 PM PST 23
Finished Dec 31 01:09:54 PM PST 23
Peak memory 218872 kb
Host smart-a9f35a03-dbad-4b0b-83c8-933fa23510b8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887098830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1887098830
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1080402900
Short name T294
Test name
Test status
Simulation time 398796165 ps
CPU time 4.64 seconds
Started Dec 31 01:09:45 PM PST 23
Finished Dec 31 01:10:00 PM PST 23
Peak memory 236212 kb
Host smart-ece8cd0d-e4a1-4fa7-ab1d-692fd9051c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080402900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1080402900
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1706132795
Short name T1587
Test name
Test status
Simulation time 3450147404 ps
CPU time 12.72 seconds
Started Dec 31 01:09:36 PM PST 23
Finished Dec 31 01:09:51 PM PST 23
Peak memory 225092 kb
Host smart-a07f4c6a-55d0-42c4-a684-1d46b40b9ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706132795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1706132795
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_perf.3555906127
Short name T531
Test name
Test status
Simulation time 33372355540 ps
CPU time 1923.36 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:41:48 PM PST 23
Peak memory 249736 kb
Host smart-3102d51d-cf7c-4309-8d74-6ebcbb0c7796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555906127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_perf.3555906127
Directory /workspace/19.spi_device_perf/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.2857160539
Short name T1486
Test name
Test status
Simulation time 24782608 ps
CPU time 0.73 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:09:47 PM PST 23
Peak memory 216648 kb
Host smart-5a063cdb-1f3d-48c0-b9b1-db0149245d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857160539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.2857160539
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2095852109
Short name T1678
Test name
Test status
Simulation time 1085133410 ps
CPU time 6 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:09:52 PM PST 23
Peak memory 220640 kb
Host smart-6f032d92-aae9-4551-b456-4d21d79a2fe0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2095852109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2095852109
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_rx_async_fifo_reset.540533839
Short name T1133
Test name
Test status
Simulation time 208434136 ps
CPU time 0.89 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:09:44 PM PST 23
Peak memory 208444 kb
Host smart-c61bde7e-e317-43f4-8a68-858a3e468b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540533839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_rx_async_fifo_reset.540533839
Directory /workspace/19.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/19.spi_device_rx_timeout.1839944165
Short name T613
Test name
Test status
Simulation time 2507887303 ps
CPU time 6.47 seconds
Started Dec 31 01:09:35 PM PST 23
Finished Dec 31 01:09:44 PM PST 23
Peak memory 216840 kb
Host smart-7cb0f06c-1739-48a9-baf4-bcbc5ffd59db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839944165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_rx_timeout.1839944165
Directory /workspace/19.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/19.spi_device_smoke.1076983112
Short name T614
Test name
Test status
Simulation time 220317995 ps
CPU time 1.01 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:09:42 PM PST 23
Peak memory 207880 kb
Host smart-e052e66f-351a-40ef-9e3d-2a6e1716afbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076983112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_smoke.1076983112
Directory /workspace/19.spi_device_smoke/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1183664636
Short name T956
Test name
Test status
Simulation time 63885347206 ps
CPU time 688.53 seconds
Started Dec 31 01:09:35 PM PST 23
Finished Dec 31 01:21:05 PM PST 23
Peak memory 288204 kb
Host smart-9bd3def7-8356-4847-b587-b7e8e4fc4cca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183664636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1183664636
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1897035181
Short name T1665
Test name
Test status
Simulation time 10909597285 ps
CPU time 40.21 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:10:23 PM PST 23
Peak memory 221736 kb
Host smart-0165d651-9da7-4a9d-9d77-d76725cd6810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897035181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1897035181
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.612667435
Short name T585
Test name
Test status
Simulation time 6043863725 ps
CPU time 10.37 seconds
Started Dec 31 01:09:36 PM PST 23
Finished Dec 31 01:09:48 PM PST 23
Peak memory 216952 kb
Host smart-afe019d2-aa2e-40d2-ac9c-d523fa43e399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612667435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.612667435
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1659277878
Short name T334
Test name
Test status
Simulation time 103327327 ps
CPU time 1.12 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:09:46 PM PST 23
Peak memory 208108 kb
Host smart-9d2bfb33-c8f4-4180-b75f-c047a1920f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659277878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1659277878
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2502956799
Short name T1116
Test name
Test status
Simulation time 218605933 ps
CPU time 0.91 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:09:44 PM PST 23
Peak memory 206864 kb
Host smart-11c2e7ea-409d-4163-a5b3-99df0a4dc5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502956799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2502956799
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_tx_async_fifo_reset.2011037645
Short name T1510
Test name
Test status
Simulation time 49996605 ps
CPU time 0.78 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:09:43 PM PST 23
Peak memory 208392 kb
Host smart-5e77c0e7-3b4c-4520-878c-156be968b295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011037645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tx_async_fifo_reset.2011037645
Directory /workspace/19.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/19.spi_device_txrx.3179340499
Short name T1712
Test name
Test status
Simulation time 56545036694 ps
CPU time 1011.94 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:26:36 PM PST 23
Peak memory 282524 kb
Host smart-c1616bde-1994-49be-9417-d951b3b5d3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179340499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_txrx.3179340499
Directory /workspace/19.spi_device_txrx/latest

Test location /workspace/coverage/default/19.spi_device_upload.1348462409
Short name T843
Test name
Test status
Simulation time 7926896904 ps
CPU time 8.84 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:09:50 PM PST 23
Peak memory 218676 kb
Host smart-6ce94cfe-5c06-44c6-912b-9e5ae6726e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348462409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1348462409
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_abort.3820475350
Short name T1683
Test name
Test status
Simulation time 15849185 ps
CPU time 0.74 seconds
Started Dec 31 01:07:58 PM PST 23
Finished Dec 31 01:07:59 PM PST 23
Peak memory 206556 kb
Host smart-2d4dc93b-9e01-4b1d-9391-84aeacd91e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820475350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_abort.3820475350
Directory /workspace/2.spi_device_abort/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3024411636
Short name T683
Test name
Test status
Simulation time 37233831 ps
CPU time 0.74 seconds
Started Dec 31 01:08:04 PM PST 23
Finished Dec 31 01:08:07 PM PST 23
Peak memory 206456 kb
Host smart-ff812662-2593-43fd-8ca5-ed0b450d7031
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024411636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
024411636
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_bit_transfer.2757424540
Short name T1056
Test name
Test status
Simulation time 329972218 ps
CPU time 3.1 seconds
Started Dec 31 01:07:58 PM PST 23
Finished Dec 31 01:08:03 PM PST 23
Peak memory 216600 kb
Host smart-533b206f-3f12-4f3f-8603-c7fdfe4628d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757424540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_bit_transfer.2757424540
Directory /workspace/2.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/2.spi_device_byte_transfer.970668929
Short name T752
Test name
Test status
Simulation time 489170121 ps
CPU time 3 seconds
Started Dec 31 01:08:24 PM PST 23
Finished Dec 31 01:08:28 PM PST 23
Peak memory 216792 kb
Host smart-e9e31e5d-4d80-42b5-9bb6-3e449900f523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970668929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_byte_transfer.970668929
Directory /workspace/2.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1697163906
Short name T723
Test name
Test status
Simulation time 2584569032 ps
CPU time 6.02 seconds
Started Dec 31 01:08:05 PM PST 23
Finished Dec 31 01:08:14 PM PST 23
Peak memory 220448 kb
Host smart-21e61eae-5837-461b-92d5-2960a2d9b53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697163906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1697163906
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.667500570
Short name T1490
Test name
Test status
Simulation time 55317484 ps
CPU time 0.79 seconds
Started Dec 31 01:07:47 PM PST 23
Finished Dec 31 01:07:49 PM PST 23
Peak memory 207576 kb
Host smart-d986f675-3978-401e-9e53-763dd26a0817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667500570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.667500570
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_dummy_item_extra_dly.526408408
Short name T792
Test name
Test status
Simulation time 103736403142 ps
CPU time 362.93 seconds
Started Dec 31 01:07:57 PM PST 23
Finished Dec 31 01:14:01 PM PST 23
Peak memory 291804 kb
Host smart-caf5ecd1-8274-4047-bbb8-26b5a13e5b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526408408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_dummy_item_extra_dly.526408408
Directory /workspace/2.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/2.spi_device_extreme_fifo_size.4134814134
Short name T1743
Test name
Test status
Simulation time 42059955144 ps
CPU time 1422.92 seconds
Started Dec 31 01:07:58 PM PST 23
Finished Dec 31 01:31:43 PM PST 23
Peak memory 219196 kb
Host smart-95d182de-d974-4afd-990e-022deaa4d467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134814134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_extreme_fifo_size.4134814134
Directory /workspace/2.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/2.spi_device_fifo_full.856308189
Short name T1734
Test name
Test status
Simulation time 28551630741 ps
CPU time 1578.91 seconds
Started Dec 31 01:08:05 PM PST 23
Finished Dec 31 01:34:26 PM PST 23
Peak memory 281156 kb
Host smart-2b315daf-ec54-482b-a728-f26cf4dd919f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856308189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_fifo_full.856308189
Directory /workspace/2.spi_device_fifo_full/latest

Test location /workspace/coverage/default/2.spi_device_fifo_underflow_overflow.885369452
Short name T855
Test name
Test status
Simulation time 43151237319 ps
CPU time 345.72 seconds
Started Dec 31 01:07:48 PM PST 23
Finished Dec 31 01:13:35 PM PST 23
Peak memory 426868 kb
Host smart-9dea96e7-504a-4d07-99f8-bbba6fdb3d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885369452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_fifo_underflow_overflo
w.885369452
Directory /workspace/2.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.4267931171
Short name T1747
Test name
Test status
Simulation time 4537396490 ps
CPU time 105.94 seconds
Started Dec 31 01:08:06 PM PST 23
Finished Dec 31 01:09:54 PM PST 23
Peak memory 254748 kb
Host smart-c7fa2c6b-60d9-44af-9633-ef089243f2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267931171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.4267931171
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1054410940
Short name T1187
Test name
Test status
Simulation time 1378658947 ps
CPU time 31.9 seconds
Started Dec 31 01:08:04 PM PST 23
Finished Dec 31 01:08:39 PM PST 23
Peak memory 250444 kb
Host smart-c541b323-37e4-4fa5-825f-9621c6d898d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054410940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1054410940
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3910360446
Short name T1148
Test name
Test status
Simulation time 2086577699 ps
CPU time 12.8 seconds
Started Dec 31 01:07:50 PM PST 23
Finished Dec 31 01:08:04 PM PST 23
Peak memory 252324 kb
Host smart-fbca800e-7143-4b55-b679-f6b8add54bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910360446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3910360446
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2133063439
Short name T230
Test name
Test status
Simulation time 9026817370 ps
CPU time 9.63 seconds
Started Dec 31 01:08:03 PM PST 23
Finished Dec 31 01:08:14 PM PST 23
Peak memory 236764 kb
Host smart-d8abfd55-8cc7-4fea-9baf-40e0e1bab86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133063439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2133063439
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_intr.1364695172
Short name T1092
Test name
Test status
Simulation time 7598199831 ps
CPU time 26.61 seconds
Started Dec 31 01:08:04 PM PST 23
Finished Dec 31 01:08:33 PM PST 23
Peak memory 225172 kb
Host smart-9bce9327-3c0e-4eb5-b5d9-811e73c3d21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364695172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intr.1364695172
Directory /workspace/2.spi_device_intr/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2541033511
Short name T1413
Test name
Test status
Simulation time 15421299010 ps
CPU time 48.26 seconds
Started Dec 31 01:07:47 PM PST 23
Finished Dec 31 01:08:36 PM PST 23
Peak memory 241024 kb
Host smart-48c02d47-4175-4aa5-b53c-4c2c77ff0def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541033511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2541033511
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3918276029
Short name T756
Test name
Test status
Simulation time 14982331 ps
CPU time 1.05 seconds
Started Dec 31 01:08:01 PM PST 23
Finished Dec 31 01:08:03 PM PST 23
Peak memory 218900 kb
Host smart-b4660a9e-8f22-4f9a-868c-e2050a5e1e37
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918276029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3918276029
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.4208843444
Short name T1559
Test name
Test status
Simulation time 76708136690 ps
CPU time 57.41 seconds
Started Dec 31 01:08:46 PM PST 23
Finished Dec 31 01:09:44 PM PST 23
Peak memory 251604 kb
Host smart-14e5969b-01dd-4531-a17e-be9b6f090df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208843444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.4208843444
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2809017794
Short name T1127
Test name
Test status
Simulation time 2071236785 ps
CPU time 8.45 seconds
Started Dec 31 01:07:47 PM PST 23
Finished Dec 31 01:07:57 PM PST 23
Peak memory 225016 kb
Host smart-8ba2461d-9973-4901-99a1-22aa05993cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809017794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2809017794
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_perf.4107809563
Short name T1720
Test name
Test status
Simulation time 228607639290 ps
CPU time 1461.16 seconds
Started Dec 31 01:08:24 PM PST 23
Finished Dec 31 01:32:46 PM PST 23
Peak memory 273944 kb
Host smart-c8e38708-6e28-4e93-b8ee-c67a7de3562d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107809563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_perf.4107809563
Directory /workspace/2.spi_device_perf/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.1479985865
Short name T1751
Test name
Test status
Simulation time 43262900 ps
CPU time 0.72 seconds
Started Dec 31 01:07:47 PM PST 23
Finished Dec 31 01:07:49 PM PST 23
Peak memory 216708 kb
Host smart-77282bd8-f59f-47df-8f37-b4c65452c954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479985865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.1479985865
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3889324833
Short name T153
Test name
Test status
Simulation time 691149638 ps
CPU time 3.77 seconds
Started Dec 31 01:08:05 PM PST 23
Finished Dec 31 01:08:11 PM PST 23
Peak memory 219760 kb
Host smart-b16f334c-b319-429b-9203-37f8136a764e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3889324833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3889324833
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_rx_async_fifo_reset.3739110546
Short name T1482
Test name
Test status
Simulation time 142687378 ps
CPU time 0.92 seconds
Started Dec 31 01:08:02 PM PST 23
Finished Dec 31 01:08:05 PM PST 23
Peak memory 208520 kb
Host smart-9f6e160e-b5ce-4505-b750-79c3e900cfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739110546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_rx_async_fifo_reset.3739110546
Directory /workspace/2.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/2.spi_device_rx_timeout.3419700486
Short name T1117
Test name
Test status
Simulation time 1297177977 ps
CPU time 5.93 seconds
Started Dec 31 01:07:48 PM PST 23
Finished Dec 31 01:07:55 PM PST 23
Peak memory 216792 kb
Host smart-fd6bb4f1-aa12-4d60-bd3e-eb75ef59459f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419700486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_rx_timeout.3419700486
Directory /workspace/2.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1804342154
Short name T78
Test name
Test status
Simulation time 135522793 ps
CPU time 1.25 seconds
Started Dec 31 01:08:01 PM PST 23
Finished Dec 31 01:08:03 PM PST 23
Peak memory 238144 kb
Host smart-5ca7cc4f-8e3e-4284-9fe9-0341b55e3ddc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804342154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1804342154
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_smoke.1290216933
Short name T569
Test name
Test status
Simulation time 105409782 ps
CPU time 1.09 seconds
Started Dec 31 01:07:48 PM PST 23
Finished Dec 31 01:07:50 PM PST 23
Peak memory 208348 kb
Host smart-87e7a8f4-8e58-4b0d-84bc-3281cd6c973b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290216933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_smoke.1290216933
Directory /workspace/2.spi_device_smoke/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.4129606178
Short name T122
Test name
Test status
Simulation time 488953512512 ps
CPU time 1294.6 seconds
Started Dec 31 01:07:47 PM PST 23
Finished Dec 31 01:29:23 PM PST 23
Peak memory 380172 kb
Host smart-9dacdea1-482e-4070-9bd1-4295cfe6a531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129606178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.4129606178
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.474825285
Short name T329
Test name
Test status
Simulation time 8694435353 ps
CPU time 74.87 seconds
Started Dec 31 01:08:06 PM PST 23
Finished Dec 31 01:09:23 PM PST 23
Peak memory 217148 kb
Host smart-4b3789f6-acf2-413a-8d05-1c6e496959c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474825285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.474825285
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1603269962
Short name T1260
Test name
Test status
Simulation time 882494496 ps
CPU time 6.34 seconds
Started Dec 31 01:07:47 PM PST 23
Finished Dec 31 01:07:55 PM PST 23
Peak memory 216780 kb
Host smart-30a82204-5d35-4f8a-9f8c-084a74ad2e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603269962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1603269962
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3022742073
Short name T1521
Test name
Test status
Simulation time 103556318 ps
CPU time 6.07 seconds
Started Dec 31 01:08:27 PM PST 23
Finished Dec 31 01:08:34 PM PST 23
Peak memory 216792 kb
Host smart-6952cfea-fe6b-46aa-839a-eff993bef299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022742073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3022742073
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3149052513
Short name T549
Test name
Test status
Simulation time 172357037 ps
CPU time 1.07 seconds
Started Dec 31 01:08:28 PM PST 23
Finished Dec 31 01:08:31 PM PST 23
Peak memory 208024 kb
Host smart-4ff63d46-4884-4f60-901f-3cf81f4d739f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149052513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3149052513
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_tx_async_fifo_reset.345590140
Short name T699
Test name
Test status
Simulation time 29574198 ps
CPU time 0.8 seconds
Started Dec 31 01:08:07 PM PST 23
Finished Dec 31 01:08:10 PM PST 23
Peak memory 208356 kb
Host smart-58da4576-c2ec-4a63-952d-69c2b3288035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345590140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tx_async_fifo_reset.345590140
Directory /workspace/2.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/2.spi_device_txrx.2679258545
Short name T1057
Test name
Test status
Simulation time 28722941402 ps
CPU time 175.98 seconds
Started Dec 31 01:08:04 PM PST 23
Finished Dec 31 01:11:02 PM PST 23
Peak memory 287972 kb
Host smart-f79a7b2c-815f-4749-8345-b082dae28b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679258545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_txrx.2679258545
Directory /workspace/2.spi_device_txrx/latest

Test location /workspace/coverage/default/2.spi_device_upload.4255935785
Short name T577
Test name
Test status
Simulation time 5185539802 ps
CPU time 11.24 seconds
Started Dec 31 01:08:05 PM PST 23
Finished Dec 31 01:08:18 PM PST 23
Peak memory 234620 kb
Host smart-17b5e70c-e4c1-4e2f-ba12-8f878f8847a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255935785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.4255935785
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_abort.992975935
Short name T1038
Test name
Test status
Simulation time 17951106 ps
CPU time 0.76 seconds
Started Dec 31 01:09:43 PM PST 23
Finished Dec 31 01:09:54 PM PST 23
Peak memory 206648 kb
Host smart-6e0b1087-9eab-4b7b-9bba-37ab171bc9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992975935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_abort.992975935
Directory /workspace/20.spi_device_abort/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1942026945
Short name T70
Test name
Test status
Simulation time 35796526 ps
CPU time 0.74 seconds
Started Dec 31 01:09:42 PM PST 23
Finished Dec 31 01:09:53 PM PST 23
Peak memory 206512 kb
Host smart-73ac5c8a-8965-4bb5-9fd0-bf2732e9db7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942026945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1942026945
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_bit_transfer.3307594540
Short name T674
Test name
Test status
Simulation time 1546133623 ps
CPU time 2.29 seconds
Started Dec 31 01:09:35 PM PST 23
Finished Dec 31 01:09:40 PM PST 23
Peak memory 216736 kb
Host smart-6b049343-dc3d-42a6-b937-0363ae044f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307594540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_bit_transfer.3307594540
Directory /workspace/20.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/20.spi_device_byte_transfer.2044265350
Short name T1766
Test name
Test status
Simulation time 228308014 ps
CPU time 3.35 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:09:46 PM PST 23
Peak memory 216744 kb
Host smart-4cf33dc1-df93-4a0d-9d4a-66fb4916b644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044265350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_byte_transfer.2044265350
Directory /workspace/20.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2508954025
Short name T1412
Test name
Test status
Simulation time 4391505238 ps
CPU time 6 seconds
Started Dec 31 01:09:47 PM PST 23
Finished Dec 31 01:10:02 PM PST 23
Peak memory 222656 kb
Host smart-82834c16-720f-48bb-9779-3fc99c49ec43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508954025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2508954025
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2131888145
Short name T514
Test name
Test status
Simulation time 51906011 ps
CPU time 0.78 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:09:42 PM PST 23
Peak memory 207560 kb
Host smart-02db90c1-c816-4741-89f3-4ba6895e4c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131888145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2131888145
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_dummy_item_extra_dly.786930474
Short name T1654
Test name
Test status
Simulation time 58419683324 ps
CPU time 525.27 seconds
Started Dec 31 01:09:34 PM PST 23
Finished Dec 31 01:18:21 PM PST 23
Peak memory 249720 kb
Host smart-2114d1d5-d4bc-4079-a5c3-4b01c61d9cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786930474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_dummy_item_extra_dly.786930474
Directory /workspace/20.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/20.spi_device_extreme_fifo_size.582741559
Short name T691
Test name
Test status
Simulation time 77854141750 ps
CPU time 951.26 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:25:37 PM PST 23
Peak memory 225056 kb
Host smart-fa0a9974-c17f-4060-ad6b-32aa7d6d0f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582741559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_extreme_fifo_size.582741559
Directory /workspace/20.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/20.spi_device_fifo_full.3166621426
Short name T1567
Test name
Test status
Simulation time 61140670076 ps
CPU time 374.05 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:15:59 PM PST 23
Peak memory 302184 kb
Host smart-10ad37fd-a7bc-4590-92ac-0715ed1a5f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166621426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_fifo_full.3166621426
Directory /workspace/20.spi_device_fifo_full/latest

Test location /workspace/coverage/default/20.spi_device_fifo_underflow_overflow.3088516051
Short name T178
Test name
Test status
Simulation time 131907279737 ps
CPU time 211.18 seconds
Started Dec 31 01:09:36 PM PST 23
Finished Dec 31 01:13:09 PM PST 23
Peak memory 284468 kb
Host smart-5249bcae-62e6-4e4d-9c7c-4eede3c85d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088516051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_fifo_underflow_overf
low.3088516051
Directory /workspace/20.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.652723799
Short name T1196
Test name
Test status
Simulation time 25478328265 ps
CPU time 58.95 seconds
Started Dec 31 01:09:41 PM PST 23
Finished Dec 31 01:10:51 PM PST 23
Peak memory 238216 kb
Host smart-77850e8b-0149-4269-95d6-bd0f4b2c4e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652723799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.652723799
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.4176791639
Short name T1538
Test name
Test status
Simulation time 16481316501 ps
CPU time 36.1 seconds
Started Dec 31 01:09:47 PM PST 23
Finished Dec 31 01:10:32 PM PST 23
Peak memory 238996 kb
Host smart-c9a01624-5d4a-4046-abb8-622c6b31f424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176791639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.4176791639
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.886272749
Short name T1217
Test name
Test status
Simulation time 19752856590 ps
CPU time 116.81 seconds
Started Dec 31 01:09:42 PM PST 23
Finished Dec 31 01:11:49 PM PST 23
Peak memory 249912 kb
Host smart-a9503705-d5c2-40bb-88fc-bf95be187c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886272749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.886272749
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.32579909
Short name T779
Test name
Test status
Simulation time 2518696950 ps
CPU time 11.41 seconds
Started Dec 31 01:09:38 PM PST 23
Finished Dec 31 01:09:55 PM PST 23
Peak memory 257212 kb
Host smart-8c9ae5e4-6e9a-4074-b85d-c46be7c29347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32579909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.32579909
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1290717497
Short name T1125
Test name
Test status
Simulation time 3430108652 ps
CPU time 4.85 seconds
Started Dec 31 01:09:36 PM PST 23
Finished Dec 31 01:09:42 PM PST 23
Peak memory 221304 kb
Host smart-3e62ef9b-25a6-479d-b865-2bb2e7b0be85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290717497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1290717497
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_intr.1806487755
Short name T1393
Test name
Test status
Simulation time 6331886027 ps
CPU time 34.44 seconds
Started Dec 31 01:09:44 PM PST 23
Finished Dec 31 01:10:28 PM PST 23
Peak memory 225172 kb
Host smart-91dafb86-bedb-4884-8b15-5bab22e9c1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806487755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intr.1806487755
Directory /workspace/20.spi_device_intr/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.188274698
Short name T722
Test name
Test status
Simulation time 20914221567 ps
CPU time 19.12 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:10:05 PM PST 23
Peak memory 218920 kb
Host smart-b2b7078a-3969-4718-b9f4-2d6ce2224185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188274698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.188274698
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2832004123
Short name T284
Test name
Test status
Simulation time 1965288417 ps
CPU time 8.09 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:09:53 PM PST 23
Peak memory 241508 kb
Host smart-1e2fbec2-fc7a-4a34-bb21-5768237ccc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832004123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2832004123
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2215052221
Short name T1699
Test name
Test status
Simulation time 14718216262 ps
CPU time 48.36 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:10:30 PM PST 23
Peak memory 236480 kb
Host smart-90f65e58-4075-42e8-9072-1f9e8e349d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215052221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2215052221
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_perf.3445034528
Short name T841
Test name
Test status
Simulation time 19212805518 ps
CPU time 573.34 seconds
Started Dec 31 01:09:34 PM PST 23
Finished Dec 31 01:19:09 PM PST 23
Peak memory 281104 kb
Host smart-2320f412-ad71-4dfb-a1be-44a56ad8db60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445034528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_perf.3445034528
Directory /workspace/20.spi_device_perf/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2141163636
Short name T1251
Test name
Test status
Simulation time 5829125140 ps
CPU time 7.24 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:09:53 PM PST 23
Peak memory 220692 kb
Host smart-ad7c1b7a-b9df-4230-ac78-fed18ff7b28b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2141163636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2141163636
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_rx_async_fifo_reset.1248051829
Short name T464
Test name
Test status
Simulation time 18012229 ps
CPU time 0.86 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:09:45 PM PST 23
Peak memory 208500 kb
Host smart-1810f860-d4d8-4003-bd91-15ec0bf832f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248051829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_rx_async_fifo_reset.1248051829
Directory /workspace/20.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/20.spi_device_rx_timeout.3764375926
Short name T733
Test name
Test status
Simulation time 1845514026 ps
CPU time 5.05 seconds
Started Dec 31 01:09:40 PM PST 23
Finished Dec 31 01:09:56 PM PST 23
Peak memory 216816 kb
Host smart-4611632e-a220-460e-a70e-01ce8de7d1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764375926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_rx_timeout.3764375926
Directory /workspace/20.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/20.spi_device_smoke.1696427868
Short name T1008
Test name
Test status
Simulation time 17940483 ps
CPU time 0.98 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:09:41 PM PST 23
Peak memory 208020 kb
Host smart-beda8b5f-d950-40ff-98e2-f4a8554697fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696427868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_smoke.1696427868
Directory /workspace/20.spi_device_smoke/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3093645892
Short name T1466
Test name
Test status
Simulation time 164045695995 ps
CPU time 1168.21 seconds
Started Dec 31 01:09:46 PM PST 23
Finished Dec 31 01:29:24 PM PST 23
Peak memory 389536 kb
Host smart-eed6f049-5c1f-4810-be62-ab8bc57bb679
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093645892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3093645892
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2967669769
Short name T325
Test name
Test status
Simulation time 2783374708 ps
CPU time 22.29 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:10:04 PM PST 23
Peak memory 216996 kb
Host smart-59ce5211-7bc9-4d9a-819e-12581c60e118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967669769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2967669769
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1446278948
Short name T651
Test name
Test status
Simulation time 424933119 ps
CPU time 3.3 seconds
Started Dec 31 01:09:46 PM PST 23
Finished Dec 31 01:09:59 PM PST 23
Peak memory 216800 kb
Host smart-40a45278-2c07-45f7-928f-c818003addc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446278948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1446278948
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3662192560
Short name T629
Test name
Test status
Simulation time 112338574 ps
CPU time 2.16 seconds
Started Dec 31 01:09:35 PM PST 23
Finished Dec 31 01:09:39 PM PST 23
Peak memory 216816 kb
Host smart-dd526c91-00c1-4cf7-924c-7f96a0457e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662192560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3662192560
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3189568205
Short name T655
Test name
Test status
Simulation time 130697289 ps
CPU time 0.91 seconds
Started Dec 31 01:09:46 PM PST 23
Finished Dec 31 01:09:56 PM PST 23
Peak memory 206848 kb
Host smart-8e81789c-70d7-4434-a502-325be8e72fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189568205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3189568205
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_tx_async_fifo_reset.3869711087
Short name T882
Test name
Test status
Simulation time 58335249 ps
CPU time 0.78 seconds
Started Dec 31 01:09:36 PM PST 23
Finished Dec 31 01:09:39 PM PST 23
Peak memory 208480 kb
Host smart-46daeb07-bd3b-467a-a894-704a3aa5084d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869711087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tx_async_fifo_reset.3869711087
Directory /workspace/20.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/20.spi_device_txrx.3663449097
Short name T522
Test name
Test status
Simulation time 19673561907 ps
CPU time 210.55 seconds
Started Dec 31 01:09:40 PM PST 23
Finished Dec 31 01:13:17 PM PST 23
Peak memory 301108 kb
Host smart-9f17836b-dfa6-41bf-bf1e-175bad7cbf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663449097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_txrx.3663449097
Directory /workspace/20.spi_device_txrx/latest

Test location /workspace/coverage/default/20.spi_device_upload.548501604
Short name T1548
Test name
Test status
Simulation time 16365544746 ps
CPU time 48.28 seconds
Started Dec 31 01:09:37 PM PST 23
Finished Dec 31 01:10:29 PM PST 23
Peak memory 243760 kb
Host smart-042ef185-a109-47e7-b2c9-74f0fd7ff8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548501604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.548501604
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_abort.3506156250
Short name T1501
Test name
Test status
Simulation time 13315764 ps
CPU time 0.73 seconds
Started Dec 31 01:09:46 PM PST 23
Finished Dec 31 01:09:56 PM PST 23
Peak memory 206488 kb
Host smart-b81a8280-d68b-4639-a58f-1d95d252b1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506156250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_abort.3506156250
Directory /workspace/21.spi_device_abort/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.685227038
Short name T528
Test name
Test status
Simulation time 12614886 ps
CPU time 0.74 seconds
Started Dec 31 01:10:04 PM PST 23
Finished Dec 31 01:10:08 PM PST 23
Peak memory 206552 kb
Host smart-721a5d5e-3990-412e-98f2-92ee8c41c298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685227038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.685227038
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_bit_transfer.1898457164
Short name T1435
Test name
Test status
Simulation time 304098918 ps
CPU time 3.08 seconds
Started Dec 31 01:09:42 PM PST 23
Finished Dec 31 01:09:55 PM PST 23
Peak memory 216660 kb
Host smart-d5465583-8818-482a-afce-2e971bdde462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898457164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_bit_transfer.1898457164
Directory /workspace/21.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/21.spi_device_byte_transfer.1085146285
Short name T684
Test name
Test status
Simulation time 239349658 ps
CPU time 2.8 seconds
Started Dec 31 01:09:46 PM PST 23
Finished Dec 31 01:09:58 PM PST 23
Peak memory 216644 kb
Host smart-451b941e-edcf-41ce-878e-f925c5db5535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085146285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_byte_transfer.1085146285
Directory /workspace/21.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.696181665
Short name T1288
Test name
Test status
Simulation time 297716741 ps
CPU time 2.87 seconds
Started Dec 31 01:09:59 PM PST 23
Finished Dec 31 01:10:04 PM PST 23
Peak memory 218856 kb
Host smart-5bcfe09a-d59f-4f2a-bbe5-9f399ca07391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696181665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.696181665
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1129372469
Short name T759
Test name
Test status
Simulation time 54836698 ps
CPU time 0.75 seconds
Started Dec 31 01:09:44 PM PST 23
Finished Dec 31 01:09:55 PM PST 23
Peak memory 207564 kb
Host smart-82d057a3-753c-4378-867b-7708fc7ab400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129372469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1129372469
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_dummy_item_extra_dly.570190911
Short name T745
Test name
Test status
Simulation time 139295373817 ps
CPU time 247.93 seconds
Started Dec 31 01:09:40 PM PST 23
Finished Dec 31 01:13:58 PM PST 23
Peak memory 272464 kb
Host smart-a779c961-6e18-46c0-9d9b-0d4162e4612c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570190911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_dummy_item_extra_dly.570190911
Directory /workspace/21.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/21.spi_device_extreme_fifo_size.902119697
Short name T1475
Test name
Test status
Simulation time 43859841685 ps
CPU time 1950.19 seconds
Started Dec 31 01:09:42 PM PST 23
Finished Dec 31 01:42:23 PM PST 23
Peak memory 219048 kb
Host smart-08992e2a-9fee-4132-80a8-abe5f772b8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902119697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_extreme_fifo_size.902119697
Directory /workspace/21.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/21.spi_device_fifo_full.3600705685
Short name T704
Test name
Test status
Simulation time 30109845533 ps
CPU time 762.13 seconds
Started Dec 31 01:09:40 PM PST 23
Finished Dec 31 01:22:33 PM PST 23
Peak memory 307388 kb
Host smart-74d5c500-eb19-42aa-8ef6-acd633d69662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600705685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_fifo_full.3600705685
Directory /workspace/21.spi_device_fifo_full/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.947346015
Short name T1192
Test name
Test status
Simulation time 5289118572 ps
CPU time 26.37 seconds
Started Dec 31 01:09:40 PM PST 23
Finished Dec 31 01:10:17 PM PST 23
Peak memory 253256 kb
Host smart-54ea8d32-2fbb-4542-b724-53c18e1f210d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947346015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.947346015
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2429697565
Short name T156
Test name
Test status
Simulation time 5036987748 ps
CPU time 14.02 seconds
Started Dec 31 01:09:36 PM PST 23
Finished Dec 31 01:09:53 PM PST 23
Peak memory 255964 kb
Host smart-86db1d07-4552-4e3d-863f-5008e61265d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429697565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2429697565
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.427919401
Short name T1437
Test name
Test status
Simulation time 448473923 ps
CPU time 4.88 seconds
Started Dec 31 01:09:45 PM PST 23
Finished Dec 31 01:10:00 PM PST 23
Peak memory 220648 kb
Host smart-6f9bce5c-40dc-4955-a5a0-6c1669836eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427919401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.427919401
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_intr.577598475
Short name T1770
Test name
Test status
Simulation time 42665490845 ps
CPU time 44.81 seconds
Started Dec 31 01:09:39 PM PST 23
Finished Dec 31 01:10:31 PM PST 23
Peak memory 224324 kb
Host smart-b3cc00bc-191a-4fa9-a8e1-101a051a999c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577598475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intr.577598475
Directory /workspace/21.spi_device_intr/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.4273947374
Short name T1411
Test name
Test status
Simulation time 16825556859 ps
CPU time 14.09 seconds
Started Dec 31 01:09:42 PM PST 23
Finished Dec 31 01:10:06 PM PST 23
Peak memory 235028 kb
Host smart-959389d0-824e-4229-91c7-0539cca77d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273947374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.4273947374
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3246959060
Short name T1715
Test name
Test status
Simulation time 2004597131 ps
CPU time 6.63 seconds
Started Dec 31 01:09:42 PM PST 23
Finished Dec 31 01:09:59 PM PST 23
Peak memory 234144 kb
Host smart-360d64c3-11d7-43a2-9d01-1c7cb0885900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246959060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3246959060
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3966501418
Short name T617
Test name
Test status
Simulation time 1783320615 ps
CPU time 6.68 seconds
Started Dec 31 01:09:45 PM PST 23
Finished Dec 31 01:10:01 PM PST 23
Peak memory 238436 kb
Host smart-1cf02965-e806-44df-a46b-a4ea950b6835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966501418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3966501418
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_perf.1655595666
Short name T1347
Test name
Test status
Simulation time 16196507605 ps
CPU time 439.7 seconds
Started Dec 31 01:09:45 PM PST 23
Finished Dec 31 01:17:14 PM PST 23
Peak memory 273836 kb
Host smart-0fa06a2b-2045-4273-a62d-58bead061903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655595666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_perf.1655595666
Directory /workspace/21.spi_device_perf/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.169708407
Short name T155
Test name
Test status
Simulation time 1956974752 ps
CPU time 5.48 seconds
Started Dec 31 01:09:44 PM PST 23
Finished Dec 31 01:10:00 PM PST 23
Peak memory 220244 kb
Host smart-e07cd4ba-9110-4227-9cf1-c38bbc02dfc9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=169708407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.169708407
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_rx_async_fifo_reset.729070041
Short name T952
Test name
Test status
Simulation time 142433073 ps
CPU time 0.95 seconds
Started Dec 31 01:09:42 PM PST 23
Finished Dec 31 01:09:53 PM PST 23
Peak memory 208504 kb
Host smart-5fab7430-10b0-46fd-a0cf-9b13d47a9f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729070041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_rx_async_fifo_reset.729070041
Directory /workspace/21.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/21.spi_device_rx_timeout.669821442
Short name T1132
Test name
Test status
Simulation time 2131319579 ps
CPU time 5.72 seconds
Started Dec 31 01:09:44 PM PST 23
Finished Dec 31 01:10:00 PM PST 23
Peak memory 216828 kb
Host smart-bb05163d-ddd2-4d31-a8bb-81b23360ba32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669821442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_rx_timeout.669821442
Directory /workspace/21.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/21.spi_device_smoke.1061767258
Short name T1592
Test name
Test status
Simulation time 171960437 ps
CPU time 1.15 seconds
Started Dec 31 01:09:40 PM PST 23
Finished Dec 31 01:09:52 PM PST 23
Peak memory 208324 kb
Host smart-f44daab1-4142-47b7-8097-3972e2ed5576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061767258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_smoke.1061767258
Directory /workspace/21.spi_device_smoke/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1214134432
Short name T842
Test name
Test status
Simulation time 355883202963 ps
CPU time 1091.03 seconds
Started Dec 31 01:10:00 PM PST 23
Finished Dec 31 01:28:13 PM PST 23
Peak memory 520128 kb
Host smart-a1061e67-c31f-4137-a94e-3361734df50b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214134432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1214134432
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2032450354
Short name T825
Test name
Test status
Simulation time 14671094507 ps
CPU time 30.82 seconds
Started Dec 31 01:09:42 PM PST 23
Finished Dec 31 01:10:23 PM PST 23
Peak memory 216996 kb
Host smart-6bdd26b4-c1e5-4506-a679-07cd25293689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032450354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2032450354
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3511374753
Short name T803
Test name
Test status
Simulation time 1298952484 ps
CPU time 9.03 seconds
Started Dec 31 01:09:44 PM PST 23
Finished Dec 31 01:10:03 PM PST 23
Peak memory 216780 kb
Host smart-0a815a15-1b40-45ae-ae14-fddea63f7aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511374753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3511374753
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3247561217
Short name T728
Test name
Test status
Simulation time 1509112422 ps
CPU time 2.8 seconds
Started Dec 31 01:09:43 PM PST 23
Finished Dec 31 01:09:56 PM PST 23
Peak memory 216860 kb
Host smart-2635a093-af94-4c0f-b221-cbc6eb1f1177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247561217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3247561217
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3436186438
Short name T1733
Test name
Test status
Simulation time 605173241 ps
CPU time 1.2 seconds
Started Dec 31 01:09:44 PM PST 23
Finished Dec 31 01:09:56 PM PST 23
Peak memory 208068 kb
Host smart-30b62cd5-8476-4c2c-84b9-7d47210eb8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436186438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3436186438
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_tx_async_fifo_reset.1462863897
Short name T780
Test name
Test status
Simulation time 15889325 ps
CPU time 0.77 seconds
Started Dec 31 01:09:42 PM PST 23
Finished Dec 31 01:09:53 PM PST 23
Peak memory 208504 kb
Host smart-f0b59b97-5f04-4b75-bcf8-277a236d2da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462863897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tx_async_fifo_reset.1462863897
Directory /workspace/21.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/21.spi_device_txrx.1041138304
Short name T1230
Test name
Test status
Simulation time 22031768237 ps
CPU time 212.07 seconds
Started Dec 31 01:09:42 PM PST 23
Finished Dec 31 01:13:24 PM PST 23
Peak memory 270704 kb
Host smart-9c097e75-508d-41db-b9ec-0d1001207e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041138304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_txrx.1041138304
Directory /workspace/21.spi_device_txrx/latest

Test location /workspace/coverage/default/21.spi_device_upload.510764766
Short name T1719
Test name
Test status
Simulation time 2439929590 ps
CPU time 12.49 seconds
Started Dec 31 01:09:40 PM PST 23
Finished Dec 31 01:10:03 PM PST 23
Peak memory 247460 kb
Host smart-dc3fb5ca-82d2-4ca2-a88c-34ae4622cf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510764766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.510764766
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_abort.108822801
Short name T1473
Test name
Test status
Simulation time 44519717 ps
CPU time 0.77 seconds
Started Dec 31 01:10:03 PM PST 23
Finished Dec 31 01:10:07 PM PST 23
Peak memory 206580 kb
Host smart-08b5cc3d-8a87-4316-84ad-9318f4c3f9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108822801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_abort.108822801
Directory /workspace/22.spi_device_abort/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1163039213
Short name T1597
Test name
Test status
Simulation time 44171441 ps
CPU time 0.72 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:21 PM PST 23
Peak memory 206428 kb
Host smart-3ee030f4-c18c-4851-9845-683318af0bf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163039213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1163039213
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_bit_transfer.3871191513
Short name T926
Test name
Test status
Simulation time 201524739 ps
CPU time 2.87 seconds
Started Dec 31 01:10:00 PM PST 23
Finished Dec 31 01:10:05 PM PST 23
Peak memory 216768 kb
Host smart-77693a3e-5010-44e0-be7a-ee59ab634f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871191513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_bit_transfer.3871191513
Directory /workspace/22.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/22.spi_device_byte_transfer.2541489397
Short name T537
Test name
Test status
Simulation time 1890450773 ps
CPU time 3.27 seconds
Started Dec 31 01:10:19 PM PST 23
Finished Dec 31 01:10:31 PM PST 23
Peak memory 216796 kb
Host smart-9f9084dd-de0a-451a-b3b1-fa5b9c0ac28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541489397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_byte_transfer.2541489397
Directory /workspace/22.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2459994653
Short name T272
Test name
Test status
Simulation time 2259649086 ps
CPU time 6.36 seconds
Started Dec 31 01:10:13 PM PST 23
Finished Dec 31 01:10:21 PM PST 23
Peak memory 238568 kb
Host smart-a90088b7-1e1f-402d-82fb-13f06c5fc4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459994653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2459994653
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3784366059
Short name T1010
Test name
Test status
Simulation time 15000819 ps
CPU time 0.78 seconds
Started Dec 31 01:10:02 PM PST 23
Finished Dec 31 01:10:06 PM PST 23
Peak memory 207584 kb
Host smart-38fe10e4-357e-4042-ad08-b84f60ac3a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784366059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3784366059
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_dummy_item_extra_dly.3307995785
Short name T1298
Test name
Test status
Simulation time 651274495851 ps
CPU time 991.06 seconds
Started Dec 31 01:10:13 PM PST 23
Finished Dec 31 01:26:46 PM PST 23
Peak memory 250852 kb
Host smart-9e227d92-59ae-47fb-a3e4-29b0776c55a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307995785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_dummy_item_extra_dly.3307995785
Directory /workspace/22.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/22.spi_device_extreme_fifo_size.1035166819
Short name T1320
Test name
Test status
Simulation time 178867988105 ps
CPU time 838.35 seconds
Started Dec 31 01:09:40 PM PST 23
Finished Dec 31 01:23:49 PM PST 23
Peak memory 220212 kb
Host smart-76cbee1e-e27c-4f35-bd07-27ffc6a9ddad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035166819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_extreme_fifo_size.1035166819
Directory /workspace/22.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/22.spi_device_fifo_full.488321081
Short name T578
Test name
Test status
Simulation time 155823243916 ps
CPU time 780.46 seconds
Started Dec 31 01:09:40 PM PST 23
Finished Dec 31 01:22:47 PM PST 23
Peak memory 271748 kb
Host smart-b6bc800a-22a8-4ea1-bd0f-85fa41a182dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488321081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_fifo_full.488321081
Directory /workspace/22.spi_device_fifo_full/latest

Test location /workspace/coverage/default/22.spi_device_fifo_underflow_overflow.727487240
Short name T106
Test name
Test status
Simulation time 183927144794 ps
CPU time 184.18 seconds
Started Dec 31 01:09:59 PM PST 23
Finished Dec 31 01:13:06 PM PST 23
Peak memory 311372 kb
Host smart-6489d1af-7244-43b6-bc7b-f13f6c9b0474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727487240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_fifo_underflow_overfl
ow.727487240
Directory /workspace/22.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3280919969
Short name T241
Test name
Test status
Simulation time 5869461300 ps
CPU time 65.25 seconds
Started Dec 31 01:10:13 PM PST 23
Finished Dec 31 01:11:20 PM PST 23
Peak memory 240432 kb
Host smart-ffb1a12d-5007-4296-8dea-ea9e9fb9b22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280919969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3280919969
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1476193301
Short name T208
Test name
Test status
Simulation time 22710224383 ps
CPU time 125.22 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:12:22 PM PST 23
Peak memory 259784 kb
Host smart-3bc978e0-f92b-4efa-b620-2360b50c3746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476193301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1476193301
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2460676335
Short name T1169
Test name
Test status
Simulation time 5357894314 ps
CPU time 15.6 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:10:32 PM PST 23
Peak memory 238524 kb
Host smart-85933eed-f3b6-4124-8222-55a6c15d9aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460676335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2460676335
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1219390306
Short name T1405
Test name
Test status
Simulation time 67467905 ps
CPU time 3.59 seconds
Started Dec 31 01:10:19 PM PST 23
Finished Dec 31 01:10:31 PM PST 23
Peak memory 238400 kb
Host smart-8e129cc9-a6bc-483c-a3e4-48b86fdf875a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219390306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1219390306
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_intr.2839296383
Short name T1072
Test name
Test status
Simulation time 12359400059 ps
CPU time 57.22 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:11:14 PM PST 23
Peak memory 232716 kb
Host smart-fc7e9d31-f2da-4bf7-9cf6-5574edc1de26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839296383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intr.2839296383
Directory /workspace/22.spi_device_intr/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3190782481
Short name T717
Test name
Test status
Simulation time 67549111877 ps
CPU time 47.9 seconds
Started Dec 31 01:10:13 PM PST 23
Finished Dec 31 01:11:03 PM PST 23
Peak memory 241508 kb
Host smart-1ce75439-4ab5-4377-ac8f-bb76d8f6663c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190782481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3190782481
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2860427652
Short name T554
Test name
Test status
Simulation time 3348013275 ps
CPU time 9.02 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 01:10:27 PM PST 23
Peak memory 238880 kb
Host smart-350e31a9-7e15-49f2-be0e-1cb1d3e72faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860427652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2860427652
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1037325475
Short name T782
Test name
Test status
Simulation time 6874443551 ps
CPU time 21.94 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 01:10:40 PM PST 23
Peak memory 219376 kb
Host smart-15f1dbcf-a49b-40b2-a1f0-4d96341841f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037325475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1037325475
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_perf.724875417
Short name T1782
Test name
Test status
Simulation time 19889528094 ps
CPU time 519.43 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 01:18:57 PM PST 23
Peak memory 266740 kb
Host smart-00456d4e-506b-49b1-b727-374910eb1df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724875417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_perf.724875417
Directory /workspace/22.spi_device_perf/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3425481182
Short name T536
Test name
Test status
Simulation time 1037789812 ps
CPU time 5.53 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 01:10:24 PM PST 23
Peak memory 218640 kb
Host smart-aaca524d-cf0e-473f-a368-147eb1c4464e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3425481182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3425481182
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_rx_async_fifo_reset.3134768475
Short name T68
Test name
Test status
Simulation time 125748565 ps
CPU time 0.91 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:10:27 PM PST 23
Peak memory 208516 kb
Host smart-136f17df-a9e6-4444-8ef9-493adbf33a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134768475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_rx_async_fifo_reset.3134768475
Directory /workspace/22.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/22.spi_device_rx_timeout.3264060226
Short name T1602
Test name
Test status
Simulation time 1516400271 ps
CPU time 4.61 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:10:20 PM PST 23
Peak memory 216660 kb
Host smart-488f0278-4344-4350-b90d-5c475e4d6084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264060226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_rx_timeout.3264060226
Directory /workspace/22.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/22.spi_device_smoke.75028539
Short name T1263
Test name
Test status
Simulation time 95716278 ps
CPU time 1.1 seconds
Started Dec 31 01:09:59 PM PST 23
Finished Dec 31 01:10:02 PM PST 23
Peak memory 208100 kb
Host smart-678614db-f970-4c03-ba25-2d3db47c9337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75028539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_smoke.75028539
Directory /workspace/22.spi_device_smoke/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.774817902
Short name T1276
Test name
Test status
Simulation time 2326642165705 ps
CPU time 3496.46 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 02:08:33 PM PST 23
Peak memory 812076 kb
Host smart-9aefa1ef-b576-4447-92c4-11fd71575fc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774817902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.774817902
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3581293155
Short name T1645
Test name
Test status
Simulation time 952032866 ps
CPU time 13.2 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:33 PM PST 23
Peak memory 217096 kb
Host smart-0c043153-3b81-4aa6-b55a-41a50b6fa08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581293155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3581293155
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1911500270
Short name T1650
Test name
Test status
Simulation time 190593346 ps
CPU time 2.14 seconds
Started Dec 31 01:10:01 PM PST 23
Finished Dec 31 01:10:06 PM PST 23
Peak memory 216604 kb
Host smart-a0a36965-e742-4468-9e5b-8e57739d4f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911500270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1911500270
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.4117982964
Short name T1582
Test name
Test status
Simulation time 458614957 ps
CPU time 2.04 seconds
Started Dec 31 01:10:23 PM PST 23
Finished Dec 31 01:10:33 PM PST 23
Peak memory 216808 kb
Host smart-9688c3c9-b6e5-4010-b862-09195f545e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117982964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.4117982964
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.718701840
Short name T500
Test name
Test status
Simulation time 240181603 ps
CPU time 1.02 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 01:10:20 PM PST 23
Peak memory 207976 kb
Host smart-e3940ba3-c01b-4f1a-a854-0e93373c6502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718701840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.718701840
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_tx_async_fifo_reset.374522105
Short name T1337
Test name
Test status
Simulation time 16394517 ps
CPU time 0.79 seconds
Started Dec 31 01:10:02 PM PST 23
Finished Dec 31 01:10:07 PM PST 23
Peak memory 208460 kb
Host smart-6437d2fd-f7d4-4f0d-94b9-aaaf0a916a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374522105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tx_async_fifo_reset.374522105
Directory /workspace/22.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/22.spi_device_txrx.2168405758
Short name T1758
Test name
Test status
Simulation time 77789733255 ps
CPU time 357.94 seconds
Started Dec 31 01:09:44 PM PST 23
Finished Dec 31 01:15:52 PM PST 23
Peak memory 299200 kb
Host smart-33a501b7-0363-43aa-8c7f-1e9721462d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168405758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_txrx.2168405758
Directory /workspace/22.spi_device_txrx/latest

Test location /workspace/coverage/default/22.spi_device_upload.1998139539
Short name T749
Test name
Test status
Simulation time 12824708701 ps
CPU time 14.36 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:38 PM PST 23
Peak memory 225180 kb
Host smart-d8e057b2-a378-4e42-91c5-74f1a3de8c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998139539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1998139539
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_abort.2869767165
Short name T1718
Test name
Test status
Simulation time 53771538 ps
CPU time 0.74 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:10:17 PM PST 23
Peak memory 206444 kb
Host smart-809aa9f5-5396-41da-b3c1-ab37d7e808e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869767165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_abort.2869767165
Directory /workspace/23.spi_device_abort/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2475392858
Short name T1641
Test name
Test status
Simulation time 10069290 ps
CPU time 0.73 seconds
Started Dec 31 01:10:13 PM PST 23
Finished Dec 31 01:10:15 PM PST 23
Peak memory 206492 kb
Host smart-c3eb8f03-ee78-48b4-b188-a63a2b393968
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475392858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2475392858
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_bit_transfer.2913805233
Short name T489
Test name
Test status
Simulation time 1965408440 ps
CPU time 3.16 seconds
Started Dec 31 01:10:04 PM PST 23
Finished Dec 31 01:10:11 PM PST 23
Peak memory 216792 kb
Host smart-d7d65896-a144-4cd4-b16d-fa4a9e364497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913805233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_bit_transfer.2913805233
Directory /workspace/23.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/23.spi_device_byte_transfer.4225717077
Short name T729
Test name
Test status
Simulation time 306945125 ps
CPU time 3.2 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:24 PM PST 23
Peak memory 216888 kb
Host smart-e43a4fd5-d05b-47bb-8ece-ec6705f9a837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225717077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_byte_transfer.4225717077
Directory /workspace/23.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1034324004
Short name T1018
Test name
Test status
Simulation time 1274500310 ps
CPU time 3.93 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:24 PM PST 23
Peak memory 220716 kb
Host smart-359d0536-46fc-483a-9801-a4538d8e7c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034324004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1034324004
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3427352964
Short name T102
Test name
Test status
Simulation time 21120774 ps
CPU time 0.75 seconds
Started Dec 31 01:10:01 PM PST 23
Finished Dec 31 01:10:05 PM PST 23
Peak memory 206532 kb
Host smart-0862c11f-a132-4f28-ad0c-4953e12b9370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427352964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3427352964
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_dummy_item_extra_dly.3054454560
Short name T690
Test name
Test status
Simulation time 50732698147 ps
CPU time 708.94 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:22:16 PM PST 23
Peak memory 294896 kb
Host smart-5259aaf1-690b-4ac1-a874-53be14b122f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054454560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_dummy_item_extra_dly.3054454560
Directory /workspace/23.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/23.spi_device_extreme_fifo_size.3222346974
Short name T817
Test name
Test status
Simulation time 181672882924 ps
CPU time 2152.1 seconds
Started Dec 31 01:10:31 PM PST 23
Finished Dec 31 01:46:31 PM PST 23
Peak memory 218996 kb
Host smart-0f944018-ba4d-44fc-9fc4-b865ea70130a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222346974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_extreme_fifo_size.3222346974
Directory /workspace/23.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/23.spi_device_fifo_full.1778990084
Short name T55
Test name
Test status
Simulation time 16490696889 ps
CPU time 354.66 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:16:17 PM PST 23
Peak memory 269204 kb
Host smart-17b52569-f3c5-4930-96e9-333255be6012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778990084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_fifo_full.1778990084
Directory /workspace/23.spi_device_fifo_full/latest

Test location /workspace/coverage/default/23.spi_device_fifo_underflow_overflow.2293253574
Short name T1376
Test name
Test status
Simulation time 92661041660 ps
CPU time 288.34 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:15:14 PM PST 23
Peak memory 322704 kb
Host smart-dca7266f-f1f1-4a93-9eca-2b44995a8089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293253574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_fifo_underflow_overf
low.2293253574
Directory /workspace/23.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1805690992
Short name T29
Test name
Test status
Simulation time 50364887736 ps
CPU time 61.26 seconds
Started Dec 31 01:10:02 PM PST 23
Finished Dec 31 01:11:06 PM PST 23
Peak memory 241536 kb
Host smart-0049ef49-9797-413c-b464-ca50d780fdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805690992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1805690992
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.341891868
Short name T698
Test name
Test status
Simulation time 50845540187 ps
CPU time 406.71 seconds
Started Dec 31 01:10:13 PM PST 23
Finished Dec 31 01:17:02 PM PST 23
Peak memory 255980 kb
Host smart-afbcb225-2eeb-4144-aae2-d9e4845793ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341891868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.341891868
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.4035040776
Short name T32
Test name
Test status
Simulation time 6353346375 ps
CPU time 17.9 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:10:35 PM PST 23
Peak memory 241040 kb
Host smart-6428ec5d-879c-421f-956d-e1cbd4b7380c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035040776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.4035040776
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3895781106
Short name T217
Test name
Test status
Simulation time 696621261 ps
CPU time 4.95 seconds
Started Dec 31 01:10:03 PM PST 23
Finished Dec 31 01:10:12 PM PST 23
Peak memory 235288 kb
Host smart-c128d66e-7be5-4e3d-8fb4-bfd2bba79ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895781106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3895781106
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_intr.2231494958
Short name T1594
Test name
Test status
Simulation time 9065482668 ps
CPU time 8.66 seconds
Started Dec 31 01:10:03 PM PST 23
Finished Dec 31 01:10:15 PM PST 23
Peak memory 221752 kb
Host smart-07603fbc-e4ff-461c-9dcd-b14daed6dac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231494958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intr.2231494958
Directory /workspace/23.spi_device_intr/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1506548474
Short name T219
Test name
Test status
Simulation time 60250187830 ps
CPU time 42.74 seconds
Started Dec 31 01:10:19 PM PST 23
Finished Dec 31 01:11:11 PM PST 23
Peak memory 237692 kb
Host smart-a958afc3-72a9-45bb-bc2b-c686602d0d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506548474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1506548474
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.918745048
Short name T1550
Test name
Test status
Simulation time 2021415609 ps
CPU time 6.93 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:10:23 PM PST 23
Peak memory 240036 kb
Host smart-3228c1f2-39da-499f-b3a1-40e81995f545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918745048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.918745048
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.184611535
Short name T1290
Test name
Test status
Simulation time 17745605418 ps
CPU time 17.51 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:40 PM PST 23
Peak memory 237940 kb
Host smart-da04164a-ab9c-463f-998b-f522515d3a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184611535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.184611535
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_perf.161596578
Short name T1736
Test name
Test status
Simulation time 47549377706 ps
CPU time 744.72 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:22:49 PM PST 23
Peak memory 272728 kb
Host smart-392a83e0-c5e5-4fa0-8f96-210217930f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161596578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_perf.161596578
Directory /workspace/23.spi_device_perf/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.78571247
Short name T1442
Test name
Test status
Simulation time 658856315 ps
CPU time 3.88 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:25 PM PST 23
Peak memory 234136 kb
Host smart-17d015c3-da73-4b8c-b73e-40fae49dc9eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=78571247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direc
t.78571247
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_rx_async_fifo_reset.2636910918
Short name T1147
Test name
Test status
Simulation time 26455737 ps
CPU time 0.92 seconds
Started Dec 31 01:10:19 PM PST 23
Finished Dec 31 01:10:29 PM PST 23
Peak memory 208480 kb
Host smart-9f7b514f-9e6b-48ec-8b16-159edd17cef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636910918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_rx_async_fifo_reset.2636910918
Directory /workspace/23.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/23.spi_device_rx_timeout.2548543717
Short name T1781
Test name
Test status
Simulation time 2894961425 ps
CPU time 7.2 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 01:10:25 PM PST 23
Peak memory 216904 kb
Host smart-58b7b871-f8d3-4d56-b1ef-d566fcaf052a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548543717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_rx_timeout.2548543717
Directory /workspace/23.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/23.spi_device_smoke.2329099193
Short name T546
Test name
Test status
Simulation time 27908577 ps
CPU time 1.06 seconds
Started Dec 31 01:10:05 PM PST 23
Finished Dec 31 01:10:09 PM PST 23
Peak memory 208384 kb
Host smart-9147882e-9c75-4e22-857a-7cdd2cdc471c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329099193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_smoke.2329099193
Directory /workspace/23.spi_device_smoke/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.281263288
Short name T1545
Test name
Test status
Simulation time 3688319076 ps
CPU time 34.1 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:55 PM PST 23
Peak memory 216744 kb
Host smart-7fc6ff65-6e82-4ec1-87ab-c068a177d935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281263288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.281263288
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1845962263
Short name T904
Test name
Test status
Simulation time 6423951307 ps
CPU time 20.7 seconds
Started Dec 31 01:10:01 PM PST 23
Finished Dec 31 01:10:24 PM PST 23
Peak memory 216848 kb
Host smart-4cec82cb-9d4c-4fb6-b776-18e92f3984a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845962263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1845962263
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2719163903
Short name T1519
Test name
Test status
Simulation time 261225501 ps
CPU time 1.96 seconds
Started Dec 31 01:10:02 PM PST 23
Finished Dec 31 01:10:08 PM PST 23
Peak memory 216876 kb
Host smart-7f8f4c90-7f65-4c50-9429-6bcb1953ea90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719163903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2719163903
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3096081305
Short name T495
Test name
Test status
Simulation time 37302228 ps
CPU time 0.9 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:10:17 PM PST 23
Peak memory 208032 kb
Host smart-11190c16-7ffc-4854-a34e-d89ec86f361a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096081305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3096081305
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_tx_async_fifo_reset.1715549756
Short name T1428
Test name
Test status
Simulation time 17242992 ps
CPU time 0.77 seconds
Started Dec 31 01:10:01 PM PST 23
Finished Dec 31 01:10:04 PM PST 23
Peak memory 208496 kb
Host smart-96ece8f6-5cd6-4dc6-b779-aa7cdbe461db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715549756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tx_async_fifo_reset.1715549756
Directory /workspace/23.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/23.spi_device_txrx.1590247709
Short name T1249
Test name
Test status
Simulation time 62639276494 ps
CPU time 659.42 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:21:16 PM PST 23
Peak memory 266056 kb
Host smart-f647cd14-aaeb-48b8-a322-ae4dd45f0310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590247709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_txrx.1590247709
Directory /workspace/23.spi_device_txrx/latest

Test location /workspace/coverage/default/23.spi_device_upload.3995105168
Short name T579
Test name
Test status
Simulation time 1376597039 ps
CPU time 7.64 seconds
Started Dec 31 01:10:02 PM PST 23
Finished Dec 31 01:10:13 PM PST 23
Peak memory 239992 kb
Host smart-37062a31-c6ec-42bf-8fd5-4277553aaed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995105168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3995105168
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_abort.3356958421
Short name T900
Test name
Test status
Simulation time 22985684 ps
CPU time 0.76 seconds
Started Dec 31 01:10:03 PM PST 23
Finished Dec 31 01:10:07 PM PST 23
Peak memory 206608 kb
Host smart-b554a59e-0b1e-44dd-8017-1c697b21f690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356958421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_abort.3356958421
Directory /workspace/24.spi_device_abort/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1830654161
Short name T490
Test name
Test status
Simulation time 15234686 ps
CPU time 0.75 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 01:10:19 PM PST 23
Peak memory 206520 kb
Host smart-7e70c55d-da7e-4bc0-8d01-4b35605dad69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830654161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1830654161
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_bit_transfer.1204793483
Short name T1069
Test name
Test status
Simulation time 1657559909 ps
CPU time 3.24 seconds
Started Dec 31 01:10:13 PM PST 23
Finished Dec 31 01:10:17 PM PST 23
Peak memory 216720 kb
Host smart-6a9ac980-392d-4b07-9942-307dbe950c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204793483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_bit_transfer.1204793483
Directory /workspace/24.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/24.spi_device_byte_transfer.3569744118
Short name T742
Test name
Test status
Simulation time 88208644 ps
CPU time 2.17 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:25 PM PST 23
Peak memory 216800 kb
Host smart-6184fea4-cef1-41e0-a004-4bd9816d47c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569744118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_byte_transfer.3569744118
Directory /workspace/24.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1467503146
Short name T1570
Test name
Test status
Simulation time 2363829394 ps
CPU time 5.99 seconds
Started Dec 31 01:10:00 PM PST 23
Finished Dec 31 01:10:08 PM PST 23
Peak memory 241196 kb
Host smart-126df1e8-899c-4433-8981-27c7990a91e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467503146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1467503146
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.994721278
Short name T478
Test name
Test status
Simulation time 17877666 ps
CPU time 0.78 seconds
Started Dec 31 01:10:13 PM PST 23
Finished Dec 31 01:10:15 PM PST 23
Peak memory 207584 kb
Host smart-b1c2ae05-721a-4711-b8b0-17a0db877383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994721278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.994721278
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_dummy_item_extra_dly.2918915186
Short name T1275
Test name
Test status
Simulation time 97794136519 ps
CPU time 198.06 seconds
Started Dec 31 01:10:02 PM PST 23
Finished Dec 31 01:13:23 PM PST 23
Peak memory 273952 kb
Host smart-1b8aef5d-ad52-4b67-a57a-84887a5cd548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918915186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_dummy_item_extra_dly.2918915186
Directory /workspace/24.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/24.spi_device_extreme_fifo_size.2556126698
Short name T40
Test name
Test status
Simulation time 620573866169 ps
CPU time 1013.02 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:27:18 PM PST 23
Peak memory 219056 kb
Host smart-3209057a-e406-46bf-a591-0539d8685d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556126698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_extreme_fifo_size.2556126698
Directory /workspace/24.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/24.spi_device_fifo_full.63242298
Short name T1471
Test name
Test status
Simulation time 52288273512 ps
CPU time 901.01 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 01:25:19 PM PST 23
Peak memory 256344 kb
Host smart-08da63ad-17a0-4dd2-8095-6a2be0a97b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63242298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_fifo_full.63242298
Directory /workspace/24.spi_device_fifo_full/latest

Test location /workspace/coverage/default/24.spi_device_fifo_underflow_overflow.3564896373
Short name T820
Test name
Test status
Simulation time 253795635872 ps
CPU time 393.06 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:16:57 PM PST 23
Peak memory 449812 kb
Host smart-16328e48-f5a1-4364-8666-5b4ffd10b4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564896373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_fifo_underflow_overf
low.3564896373
Directory /workspace/24.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2542782945
Short name T1039
Test name
Test status
Simulation time 14227303787 ps
CPU time 80.85 seconds
Started Dec 31 01:10:19 PM PST 23
Finished Dec 31 01:11:48 PM PST 23
Peak memory 257892 kb
Host smart-597d8570-9a9f-4f22-b05d-a7371ca6ac97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542782945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2542782945
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.608752906
Short name T1624
Test name
Test status
Simulation time 54977628379 ps
CPU time 411.71 seconds
Started Dec 31 01:10:04 PM PST 23
Finished Dec 31 01:16:59 PM PST 23
Peak memory 273540 kb
Host smart-7192793a-1aa4-427d-984f-b7b4c0fdcc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608752906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.608752906
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1269724939
Short name T1189
Test name
Test status
Simulation time 229454846 ps
CPU time 7.41 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:10:34 PM PST 23
Peak memory 249740 kb
Host smart-384df128-9ab3-47d3-8cd5-2775ea0fa43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269724939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1269724939
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.4028776344
Short name T896
Test name
Test status
Simulation time 593421801 ps
CPU time 3.97 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:10:20 PM PST 23
Peak memory 218176 kb
Host smart-dd11621c-97ab-43c7-975e-b04734e2d604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028776344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.4028776344
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_intr.1437847107
Short name T1481
Test name
Test status
Simulation time 12109886718 ps
CPU time 20.66 seconds
Started Dec 31 01:10:01 PM PST 23
Finished Dec 31 01:10:24 PM PST 23
Peak memory 222576 kb
Host smart-7da7ebbf-c758-4725-8c02-3d72114ad8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437847107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intr.1437847107
Directory /workspace/24.spi_device_intr/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3900635765
Short name T773
Test name
Test status
Simulation time 13771862990 ps
CPU time 18.52 seconds
Started Dec 31 01:10:03 PM PST 23
Finished Dec 31 01:10:25 PM PST 23
Peak memory 233916 kb
Host smart-06807bca-1bc3-4353-b4bf-530e885867e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900635765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3900635765
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2534634759
Short name T930
Test name
Test status
Simulation time 2570729790 ps
CPU time 8.58 seconds
Started Dec 31 01:10:13 PM PST 23
Finished Dec 31 01:10:22 PM PST 23
Peak memory 219932 kb
Host smart-e7c63fa0-e2e7-46e8-86a6-f269a773b449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534634759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2534634759
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1729188511
Short name T1615
Test name
Test status
Simulation time 52257348329 ps
CPU time 32.34 seconds
Started Dec 31 01:10:13 PM PST 23
Finished Dec 31 01:10:47 PM PST 23
Peak memory 249080 kb
Host smart-d8fcbd51-27d9-4466-82d1-cc618d91ba96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729188511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1729188511
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_perf.4179704707
Short name T1367
Test name
Test status
Simulation time 9896307297 ps
CPU time 442.73 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 01:17:40 PM PST 23
Peak memory 252908 kb
Host smart-b671f43d-3c96-4957-a2bc-09c3b3fb8b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179704707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_perf.4179704707
Directory /workspace/24.spi_device_perf/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2832531683
Short name T725
Test name
Test status
Simulation time 421233371 ps
CPU time 4.42 seconds
Started Dec 31 01:10:02 PM PST 23
Finished Dec 31 01:10:10 PM PST 23
Peak memory 234344 kb
Host smart-61ba434c-72b7-440a-80f7-91e55c6d9db0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2832531683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2832531683
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_rx_timeout.4184370979
Short name T1737
Test name
Test status
Simulation time 482674031 ps
CPU time 4.95 seconds
Started Dec 31 01:10:01 PM PST 23
Finished Dec 31 01:10:08 PM PST 23
Peak memory 216812 kb
Host smart-e20f0e53-8191-4108-8727-69ab345b29bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184370979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_rx_timeout.4184370979
Directory /workspace/24.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/24.spi_device_smoke.2008736220
Short name T1672
Test name
Test status
Simulation time 341056176 ps
CPU time 1.1 seconds
Started Dec 31 01:10:21 PM PST 23
Finished Dec 31 01:10:31 PM PST 23
Peak memory 208368 kb
Host smart-37ffd7ba-9c64-4936-a400-4fda6efc6148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008736220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_smoke.2008736220
Directory /workspace/24.spi_device_smoke/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.938281915
Short name T1022
Test name
Test status
Simulation time 167444946000 ps
CPU time 1717.9 seconds
Started Dec 31 01:10:13 PM PST 23
Finished Dec 31 01:38:52 PM PST 23
Peak memory 400052 kb
Host smart-1c8e2cfd-bfa4-420f-a6b0-748fd8a674de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938281915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.938281915
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2360669721
Short name T1106
Test name
Test status
Simulation time 16932729037 ps
CPU time 80.6 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:11:41 PM PST 23
Peak memory 216780 kb
Host smart-7b36adaa-bbf2-4cd1-8550-957c2fbdcbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360669721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2360669721
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3819906989
Short name T1377
Test name
Test status
Simulation time 27031026628 ps
CPU time 25.65 seconds
Started Dec 31 01:10:13 PM PST 23
Finished Dec 31 01:10:41 PM PST 23
Peak memory 216832 kb
Host smart-9c049d0e-ad2e-481d-8305-ad6b75f8154e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819906989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3819906989
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2935863834
Short name T1693
Test name
Test status
Simulation time 124788136 ps
CPU time 1.77 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:10:27 PM PST 23
Peak memory 216896 kb
Host smart-743e95a0-bccb-404d-a49d-05054d012dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935863834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2935863834
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.768111296
Short name T1268
Test name
Test status
Simulation time 62296164 ps
CPU time 0.9 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:26 PM PST 23
Peak memory 206828 kb
Host smart-69ea02a6-0911-4eb8-82d0-8a2cefb094a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768111296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.768111296
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_tx_async_fifo_reset.590837134
Short name T836
Test name
Test status
Simulation time 13547382 ps
CPU time 0.8 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:22 PM PST 23
Peak memory 208436 kb
Host smart-f3ba25e3-8d22-4281-b355-c73b84ac3773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590837134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tx_async_fifo_reset.590837134
Directory /workspace/24.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/24.spi_device_txrx.1256924070
Short name T459
Test name
Test status
Simulation time 53632751814 ps
CPU time 293.84 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:15:16 PM PST 23
Peak memory 288356 kb
Host smart-b7d5eeac-1934-4e28-b57b-da323c613a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256924070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_txrx.1256924070
Directory /workspace/24.spi_device_txrx/latest

Test location /workspace/coverage/default/24.spi_device_upload.1272796949
Short name T280
Test name
Test status
Simulation time 3512255185 ps
CPU time 18.73 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 01:10:37 PM PST 23
Peak memory 253636 kb
Host smart-97e81f11-fb9f-462c-9f7e-a82f5969a7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272796949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1272796949
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_abort.2695402227
Short name T1595
Test name
Test status
Simulation time 15664829 ps
CPU time 0.76 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:22 PM PST 23
Peak memory 206648 kb
Host smart-5ee56abd-b1bb-4823-bf3d-a34d12bc639d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695402227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_abort.2695402227
Directory /workspace/25.spi_device_abort/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1564186933
Short name T823
Test name
Test status
Simulation time 11198445 ps
CPU time 0.72 seconds
Started Dec 31 01:10:35 PM PST 23
Finished Dec 31 01:10:45 PM PST 23
Peak memory 206520 kb
Host smart-24074d89-ec4f-479a-b8a0-410aab059bcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564186933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1564186933
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_bit_transfer.286181652
Short name T630
Test name
Test status
Simulation time 212121143 ps
CPU time 2.94 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:22 PM PST 23
Peak memory 216888 kb
Host smart-41cae1c3-1398-4e19-a075-bdf5f3ecc54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286181652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_bit_transfer.286181652
Directory /workspace/25.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/25.spi_device_byte_transfer.3705145186
Short name T1656
Test name
Test status
Simulation time 822630521 ps
CPU time 3.13 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:25 PM PST 23
Peak memory 216792 kb
Host smart-abbdfc2e-7d0c-4583-8bcd-8e6715d5aad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705145186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_byte_transfer.3705145186
Directory /workspace/25.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.13212584
Short name T1523
Test name
Test status
Simulation time 73559293 ps
CPU time 2.68 seconds
Started Dec 31 01:10:22 PM PST 23
Finished Dec 31 01:10:33 PM PST 23
Peak memory 239308 kb
Host smart-70cae5f8-72b9-4da3-9aac-da223457eee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13212584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.13212584
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3416549439
Short name T796
Test name
Test status
Simulation time 115133848 ps
CPU time 0.8 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:23 PM PST 23
Peak memory 207588 kb
Host smart-a417ce09-2fa6-4fe7-b7cd-3981b3fc5b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416549439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3416549439
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_dummy_item_extra_dly.1701879666
Short name T1264
Test name
Test status
Simulation time 37098833464 ps
CPU time 283.6 seconds
Started Dec 31 01:10:01 PM PST 23
Finished Dec 31 01:14:47 PM PST 23
Peak memory 292692 kb
Host smart-7d4363c2-8282-4bfb-b6a9-3d6500e1fd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701879666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_dummy_item_extra_dly.1701879666
Directory /workspace/25.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/25.spi_device_extreme_fifo_size.3907309730
Short name T1318
Test name
Test status
Simulation time 6925671869 ps
CPU time 42.17 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:11:08 PM PST 23
Peak memory 225100 kb
Host smart-5cff52d1-efeb-4136-846d-16145fe60e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907309730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_extreme_fifo_size.3907309730
Directory /workspace/25.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/25.spi_device_fifo_full.4014907737
Short name T867
Test name
Test status
Simulation time 26904314163 ps
CPU time 414.32 seconds
Started Dec 31 01:10:02 PM PST 23
Finished Dec 31 01:17:00 PM PST 23
Peak memory 266160 kb
Host smart-60b1362a-c328-44c1-af68-d9e597a75e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014907737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_fifo_full.4014907737
Directory /workspace/25.spi_device_fifo_full/latest

Test location /workspace/coverage/default/25.spi_device_fifo_underflow_overflow.3521291449
Short name T628
Test name
Test status
Simulation time 243803880041 ps
CPU time 416.84 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 01:17:15 PM PST 23
Peak memory 421320 kb
Host smart-fdb05e1b-574b-40e8-949f-dc3ec1565d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521291449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_fifo_underflow_overf
low.3521291449
Directory /workspace/25.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2867032856
Short name T194
Test name
Test status
Simulation time 82636652101 ps
CPU time 152.47 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:12:56 PM PST 23
Peak memory 271724 kb
Host smart-61790611-9510-4ce9-9224-308f4e2fe15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867032856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2867032856
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1171305396
Short name T1040
Test name
Test status
Simulation time 5244744487 ps
CPU time 19.99 seconds
Started Dec 31 01:10:34 PM PST 23
Finished Dec 31 01:11:04 PM PST 23
Peak memory 240788 kb
Host smart-20292736-750f-4496-96f2-e1f6010329dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171305396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1171305396
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.491139987
Short name T1250
Test name
Test status
Simulation time 494800564 ps
CPU time 3.39 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:10:30 PM PST 23
Peak memory 233240 kb
Host smart-80cd9328-b8a9-475c-8a84-6bfb58a710ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491139987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.491139987
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_intr.3319370201
Short name T479
Test name
Test status
Simulation time 12915681938 ps
CPU time 17.72 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:42 PM PST 23
Peak memory 223644 kb
Host smart-e85eefcb-453e-4b09-89c1-554fbc10c7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319370201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intr.3319370201
Directory /workspace/25.spi_device_intr/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2824378132
Short name T1474
Test name
Test status
Simulation time 159268586 ps
CPU time 4.36 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:27 PM PST 23
Peak memory 218524 kb
Host smart-79010397-5ce0-4fd3-8f2e-90fc251f5345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824378132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2824378132
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3996247110
Short name T1257
Test name
Test status
Simulation time 16483617408 ps
CPU time 26.12 seconds
Started Dec 31 01:10:19 PM PST 23
Finished Dec 31 01:10:54 PM PST 23
Peak memory 248436 kb
Host smart-25629353-51c1-41f1-8152-be479484b5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996247110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3996247110
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2186181746
Short name T659
Test name
Test status
Simulation time 7690678454 ps
CPU time 11.67 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 01:10:29 PM PST 23
Peak memory 220268 kb
Host smart-4f20cfaa-93fc-4540-8ca7-cde5edb3aad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186181746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2186181746
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_perf.3745434549
Short name T1035
Test name
Test status
Simulation time 128208761843 ps
CPU time 2072.57 seconds
Started Dec 31 01:10:19 PM PST 23
Finished Dec 31 01:45:01 PM PST 23
Peak memory 249756 kb
Host smart-06f1e68f-5b7d-480d-9ca0-c68360210170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745434549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_perf.3745434549
Directory /workspace/25.spi_device_perf/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1905331613
Short name T152
Test name
Test status
Simulation time 491980116 ps
CPU time 4.63 seconds
Started Dec 31 01:10:33 PM PST 23
Finished Dec 31 01:10:49 PM PST 23
Peak memory 218932 kb
Host smart-2af38dd2-b318-4557-948c-8562e9b9a891
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1905331613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1905331613
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_rx_async_fifo_reset.3636640610
Short name T582
Test name
Test status
Simulation time 136359959 ps
CPU time 0.9 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:23 PM PST 23
Peak memory 208472 kb
Host smart-1a68305f-ffa3-48f5-84f2-d507588839e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636640610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_rx_async_fifo_reset.3636640610
Directory /workspace/25.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/25.spi_device_rx_timeout.4042305075
Short name T865
Test name
Test status
Simulation time 2413538867 ps
CPU time 5.42 seconds
Started Dec 31 01:10:00 PM PST 23
Finished Dec 31 01:10:08 PM PST 23
Peak memory 216836 kb
Host smart-53546707-0823-44a4-b039-655fa0b83905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042305075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_rx_timeout.4042305075
Directory /workspace/25.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/25.spi_device_smoke.1678329006
Short name T620
Test name
Test status
Simulation time 75004660 ps
CPU time 1.05 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:21 PM PST 23
Peak memory 208124 kb
Host smart-7cef03d6-81fe-4bca-9b08-17d02c06ff74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678329006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_smoke.1678329006
Directory /workspace/25.spi_device_smoke/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.643638824
Short name T1287
Test name
Test status
Simulation time 104593794906 ps
CPU time 498.6 seconds
Started Dec 31 01:10:22 PM PST 23
Finished Dec 31 01:18:49 PM PST 23
Peak memory 543120 kb
Host smart-2ba93659-57b0-40bf-8bf3-2d9e79c43ea1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643638824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.643638824
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1633911822
Short name T1151
Test name
Test status
Simulation time 64118200686 ps
CPU time 157.22 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 01:12:56 PM PST 23
Peak memory 217068 kb
Host smart-23509322-89d9-4654-b17a-bc2e9f29f26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633911822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1633911822
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2397139737
Short name T1738
Test name
Test status
Simulation time 2968081433 ps
CPU time 8.8 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:10:25 PM PST 23
Peak memory 216800 kb
Host smart-6de5cd75-df17-4293-85aa-817ce569f897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397139737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2397139737
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1745235550
Short name T1590
Test name
Test status
Simulation time 82663852 ps
CPU time 1.15 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:10:26 PM PST 23
Peak memory 208272 kb
Host smart-ff09f924-1e73-43eb-8159-d5b3d6fdd0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745235550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1745235550
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.429199882
Short name T1407
Test name
Test status
Simulation time 181346305 ps
CPU time 0.89 seconds
Started Dec 31 01:10:19 PM PST 23
Finished Dec 31 01:10:29 PM PST 23
Peak memory 206916 kb
Host smart-c8d05262-20f6-45cd-aa98-d3ce06f1ab91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429199882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.429199882
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_tx_async_fifo_reset.1121061116
Short name T945
Test name
Test status
Simulation time 13040358 ps
CPU time 0.77 seconds
Started Dec 31 01:10:20 PM PST 23
Finished Dec 31 01:10:30 PM PST 23
Peak memory 208464 kb
Host smart-6cfc8479-6ede-4591-bfe9-6db8ba9251e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121061116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tx_async_fifo_reset.1121061116
Directory /workspace/25.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/25.spi_device_txrx.1882137846
Short name T1616
Test name
Test status
Simulation time 23158498728 ps
CPU time 488.35 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:18:24 PM PST 23
Peak memory 236448 kb
Host smart-962cf1d5-cd10-476e-a05f-013ede877e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882137846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_txrx.1882137846
Directory /workspace/25.spi_device_txrx/latest

Test location /workspace/coverage/default/25.spi_device_upload.1257558555
Short name T1009
Test name
Test status
Simulation time 1623116254 ps
CPU time 16.51 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:40 PM PST 23
Peak memory 233292 kb
Host smart-93c8c12a-824a-465e-8217-103fa8c55049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257558555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1257558555
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_abort.897149355
Short name T965
Test name
Test status
Simulation time 32368367 ps
CPU time 0.74 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:24 PM PST 23
Peak memory 206660 kb
Host smart-4e24ede3-f0d0-4da1-8da4-a3852dc65b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897149355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_abort.897149355
Directory /workspace/26.spi_device_abort/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3580959231
Short name T533
Test name
Test status
Simulation time 41097487 ps
CPU time 0.75 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:23 PM PST 23
Peak memory 206480 kb
Host smart-fb873cc1-80c5-4cca-852e-fd9a1780be08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580959231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3580959231
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_bit_transfer.129907274
Short name T879
Test name
Test status
Simulation time 90032368 ps
CPU time 1.97 seconds
Started Dec 31 01:10:53 PM PST 23
Finished Dec 31 01:10:57 PM PST 23
Peak memory 216864 kb
Host smart-c159db53-44ec-44de-9756-6336f4b253f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129907274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_bit_transfer.129907274
Directory /workspace/26.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/26.spi_device_byte_transfer.2429084765
Short name T747
Test name
Test status
Simulation time 119018737 ps
CPU time 2.52 seconds
Started Dec 31 01:10:50 PM PST 23
Finished Dec 31 01:10:55 PM PST 23
Peak memory 216864 kb
Host smart-c783eb5d-05a8-4f81-8191-cc0daf953d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429084765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_byte_transfer.2429084765
Directory /workspace/26.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2669354814
Short name T1071
Test name
Test status
Simulation time 2055243515 ps
CPU time 7.03 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:29 PM PST 23
Peak memory 220328 kb
Host smart-4163c421-5308-4a49-af5f-aeeea9264669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669354814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2669354814
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2420140477
Short name T1080
Test name
Test status
Simulation time 16069394 ps
CPU time 0.78 seconds
Started Dec 31 01:10:53 PM PST 23
Finished Dec 31 01:10:57 PM PST 23
Peak memory 206468 kb
Host smart-3e724b3a-9c42-42e3-b3e2-ee6d2af087d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420140477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2420140477
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_dummy_item_extra_dly.3322646930
Short name T547
Test name
Test status
Simulation time 84087956212 ps
CPU time 705.7 seconds
Started Dec 31 01:10:33 PM PST 23
Finished Dec 31 01:22:26 PM PST 23
Peak memory 266160 kb
Host smart-3f331ac6-5b4d-4103-804b-30fff6506442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322646930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_dummy_item_extra_dly.3322646930
Directory /workspace/26.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/26.spi_device_extreme_fifo_size.1583574375
Short name T1006
Test name
Test status
Simulation time 54596191204 ps
CPU time 2800.96 seconds
Started Dec 31 01:10:33 PM PST 23
Finished Dec 31 01:57:21 PM PST 23
Peak memory 218980 kb
Host smart-18c53b98-490f-454c-aa7e-ed9b6c298027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583574375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_extreme_fifo_size.1583574375
Directory /workspace/26.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/26.spi_device_fifo_full.1277317730
Short name T180
Test name
Test status
Simulation time 196986998277 ps
CPU time 685.77 seconds
Started Dec 31 01:10:32 PM PST 23
Finished Dec 31 01:22:05 PM PST 23
Peak memory 292848 kb
Host smart-d0ebc995-d814-43b2-a3f2-9d4a994e800a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277317730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_fifo_full.1277317730
Directory /workspace/26.spi_device_fifo_full/latest

Test location /workspace/coverage/default/26.spi_device_fifo_underflow_overflow.246085477
Short name T1121
Test name
Test status
Simulation time 70191987696 ps
CPU time 386.51 seconds
Started Dec 31 01:10:34 PM PST 23
Finished Dec 31 01:17:11 PM PST 23
Peak memory 555496 kb
Host smart-b68f973c-ce8c-4907-b2ba-20119de6ee38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246085477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_fifo_underflow_overfl
ow.246085477
Directory /workspace/26.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2687908623
Short name T229
Test name
Test status
Simulation time 279515844458 ps
CPU time 583.06 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:20:03 PM PST 23
Peak memory 272348 kb
Host smart-c1d395be-22f2-4164-ac13-8ec02ab5b071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687908623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2687908623
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1063453758
Short name T1299
Test name
Test status
Simulation time 42405881787 ps
CPU time 335.47 seconds
Started Dec 31 01:10:20 PM PST 23
Finished Dec 31 01:16:04 PM PST 23
Peak memory 264004 kb
Host smart-e3eeee34-c942-483d-b727-3e0df82966cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063453758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1063453758
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1854690839
Short name T1425
Test name
Test status
Simulation time 10108402736 ps
CPU time 17.89 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 01:10:37 PM PST 23
Peak memory 231636 kb
Host smart-cbcb60e9-f299-4827-be7f-30ddf0d05197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854690839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1854690839
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1598449428
Short name T781
Test name
Test status
Simulation time 1867021548 ps
CPU time 4.93 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:10:22 PM PST 23
Peak memory 240848 kb
Host smart-f6b58e2a-06f1-4722-b982-2e8cfc3a1508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598449428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1598449428
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_intr.69344375
Short name T1694
Test name
Test status
Simulation time 16564064881 ps
CPU time 55.65 seconds
Started Dec 31 01:10:19 PM PST 23
Finished Dec 31 01:11:24 PM PST 23
Peak memory 223068 kb
Host smart-8b839d40-978b-484a-aeb9-eb2ef01e89ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69344375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intr.69344375
Directory /workspace/26.spi_device_intr/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2339163984
Short name T958
Test name
Test status
Simulation time 2540674034 ps
CPU time 7.51 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:10:34 PM PST 23
Peak memory 227572 kb
Host smart-b4424480-3954-4573-a8d8-180c946732a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339163984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2339163984
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.67129726
Short name T312
Test name
Test status
Simulation time 5614071503 ps
CPU time 21.06 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:43 PM PST 23
Peak memory 241424 kb
Host smart-60c81edc-57e5-40e1-b067-b3a69081cd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67129726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.67129726
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2443414536
Short name T1514
Test name
Test status
Simulation time 14690626056 ps
CPU time 23.04 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:46 PM PST 23
Peak memory 219116 kb
Host smart-7e356876-2bf9-4981-8f73-58dc451c35a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443414536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2443414536
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_perf.278206913
Short name T1511
Test name
Test status
Simulation time 202693866199 ps
CPU time 1094.85 seconds
Started Dec 31 01:10:34 PM PST 23
Finished Dec 31 01:28:59 PM PST 23
Peak memory 262296 kb
Host smart-dd8951ba-cdb4-4a1b-9772-7d5597837a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278206913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_perf.278206913
Directory /workspace/26.spi_device_perf/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.16976680
Short name T676
Test name
Test status
Simulation time 124019252 ps
CPU time 3.72 seconds
Started Dec 31 01:10:23 PM PST 23
Finished Dec 31 01:10:35 PM PST 23
Peak memory 220684 kb
Host smart-f6796b2a-6342-45aa-8cb9-5f23a5b661e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=16976680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direc
t.16976680
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_rx_async_fifo_reset.3339554991
Short name T1748
Test name
Test status
Simulation time 27628461 ps
CPU time 0.92 seconds
Started Dec 31 01:10:01 PM PST 23
Finished Dec 31 01:10:04 PM PST 23
Peak memory 208412 kb
Host smart-ea496795-40d7-4933-9a6f-70989f04b36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339554991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_rx_async_fifo_reset.3339554991
Directory /workspace/26.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/26.spi_device_rx_timeout.386260906
Short name T473
Test name
Test status
Simulation time 2677840224 ps
CPU time 5.98 seconds
Started Dec 31 01:10:49 PM PST 23
Finished Dec 31 01:10:56 PM PST 23
Peak memory 216916 kb
Host smart-7091a4c5-fa73-4d1c-96ad-640cfed44f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386260906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_rx_timeout.386260906
Directory /workspace/26.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/26.spi_device_smoke.2169587860
Short name T1024
Test name
Test status
Simulation time 26967038 ps
CPU time 1.07 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:26 PM PST 23
Peak memory 208356 kb
Host smart-639d05be-161c-4148-932a-39e8e40a58da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169587860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_smoke.2169587860
Directory /workspace/26.spi_device_smoke/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.958747767
Short name T1659
Test name
Test status
Simulation time 128557722885 ps
CPU time 3857.93 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 02:14:45 PM PST 23
Peak memory 350604 kb
Host smart-8f6f179a-e604-4028-8831-4d966f982e01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958747767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.958747767
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.4026582971
Short name T891
Test name
Test status
Simulation time 731538435 ps
CPU time 3.76 seconds
Started Dec 31 01:10:51 PM PST 23
Finished Dec 31 01:10:57 PM PST 23
Peak memory 217148 kb
Host smart-f94f9088-4362-409b-9f36-856664cb342a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026582971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.4026582971
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1902627296
Short name T854
Test name
Test status
Simulation time 6136977815 ps
CPU time 13.41 seconds
Started Dec 31 01:10:53 PM PST 23
Finished Dec 31 01:11:09 PM PST 23
Peak memory 216860 kb
Host smart-d6affa88-7623-4a11-8918-4223e60bd3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902627296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1902627296
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1118187598
Short name T816
Test name
Test status
Simulation time 249482248 ps
CPU time 2.1 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:10:19 PM PST 23
Peak memory 216780 kb
Host smart-8783a122-2544-44b8-ac06-0bd5caafd12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118187598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1118187598
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2022981473
Short name T1086
Test name
Test status
Simulation time 37103002 ps
CPU time 0.79 seconds
Started Dec 31 01:10:19 PM PST 23
Finished Dec 31 01:10:29 PM PST 23
Peak memory 206824 kb
Host smart-6cdf8145-892d-49fe-bafe-0c659c37e860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022981473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2022981473
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_tx_async_fifo_reset.719738734
Short name T929
Test name
Test status
Simulation time 17714277 ps
CPU time 0.77 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:20 PM PST 23
Peak memory 208372 kb
Host smart-7c2e4c82-6243-492e-a364-2c5538bc3c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719738734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tx_async_fifo_reset.719738734
Directory /workspace/26.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/26.spi_device_txrx.307231875
Short name T1193
Test name
Test status
Simulation time 100979113929 ps
CPU time 168.53 seconds
Started Dec 31 01:10:33 PM PST 23
Finished Dec 31 01:13:29 PM PST 23
Peak memory 249456 kb
Host smart-409abf4c-e19c-40d5-a400-39ed5534f203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307231875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_txrx.307231875
Directory /workspace/26.spi_device_txrx/latest

Test location /workspace/coverage/default/26.spi_device_upload.533712012
Short name T269
Test name
Test status
Simulation time 2460454070 ps
CPU time 6.58 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:30 PM PST 23
Peak memory 220912 kb
Host smart-54984df1-7207-466d-9e1d-feb4038bb9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533712012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.533712012
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_abort.947044031
Short name T1755
Test name
Test status
Simulation time 49485543 ps
CPU time 0.74 seconds
Started Dec 31 01:10:19 PM PST 23
Finished Dec 31 01:10:29 PM PST 23
Peak memory 206572 kb
Host smart-d0986a3f-0791-4d12-a9dd-636fc9b606ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947044031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_abort.947044031
Directory /workspace/27.spi_device_abort/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.975736246
Short name T1286
Test name
Test status
Simulation time 19741214 ps
CPU time 0.71 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:24 PM PST 23
Peak memory 206524 kb
Host smart-aacb3ef8-a7a8-49e8-a9ab-75080ae9ac9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975736246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.975736246
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_bit_transfer.3660972360
Short name T497
Test name
Test status
Simulation time 844550397 ps
CPU time 2.88 seconds
Started Dec 31 01:10:32 PM PST 23
Finished Dec 31 01:10:42 PM PST 23
Peak memory 216764 kb
Host smart-433f9e66-e13b-42f3-bb39-d6dd3738c1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660972360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_bit_transfer.3660972360
Directory /workspace/27.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/27.spi_device_byte_transfer.54288787
Short name T1245
Test name
Test status
Simulation time 428796449 ps
CPU time 3.03 seconds
Started Dec 31 01:10:35 PM PST 23
Finished Dec 31 01:10:47 PM PST 23
Peak memory 216768 kb
Host smart-76ef40d2-4229-4016-b48b-ae989f484a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54288787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_byte_transfer.54288787
Directory /workspace/27.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3797522470
Short name T1177
Test name
Test status
Simulation time 34444926 ps
CPU time 2.43 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:10:18 PM PST 23
Peak memory 218560 kb
Host smart-2dcdebb2-6b1d-485f-bd38-378c9e7d4b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797522470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3797522470
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3447639905
Short name T472
Test name
Test status
Simulation time 24460266 ps
CPU time 0.8 seconds
Started Dec 31 01:10:32 PM PST 23
Finished Dec 31 01:10:40 PM PST 23
Peak memory 206504 kb
Host smart-cc361ffa-d285-4d8e-88b2-0be1193fafa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447639905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3447639905
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_dummy_item_extra_dly.2972967890
Short name T567
Test name
Test status
Simulation time 51575066124 ps
CPU time 119.3 seconds
Started Dec 31 01:10:19 PM PST 23
Finished Dec 31 01:12:28 PM PST 23
Peak memory 260752 kb
Host smart-fb3e89d4-d26c-402a-a91b-fbbe5a4ee121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972967890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_dummy_item_extra_dly.2972967890
Directory /workspace/27.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/27.spi_device_extreme_fifo_size.3118608618
Short name T1644
Test name
Test status
Simulation time 12569474797 ps
CPU time 41.1 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:11:03 PM PST 23
Peak memory 233320 kb
Host smart-2c6b0fcf-88e9-4ce8-ac9d-96f4f6910110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118608618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_extreme_fifo_size.3118608618
Directory /workspace/27.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/27.spi_device_fifo_full.4091956313
Short name T895
Test name
Test status
Simulation time 43628947748 ps
CPU time 2129.5 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:45:57 PM PST 23
Peak memory 255804 kb
Host smart-1ff7ba72-33f7-4223-90da-00091a6dd939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091956313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_fifo_full.4091956313
Directory /workspace/27.spi_device_fifo_full/latest

Test location /workspace/coverage/default/27.spi_device_fifo_underflow_overflow.2900088353
Short name T1479
Test name
Test status
Simulation time 205437977315 ps
CPU time 405.11 seconds
Started Dec 31 01:10:23 PM PST 23
Finished Dec 31 01:17:16 PM PST 23
Peak memory 450008 kb
Host smart-4923d7c6-d188-48d0-a864-ce99358230fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900088353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_fifo_underflow_overf
low.2900088353
Directory /workspace/27.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.4111916002
Short name T1095
Test name
Test status
Simulation time 160964415384 ps
CPU time 97.21 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:12:04 PM PST 23
Peak memory 256468 kb
Host smart-4f4bcf04-0315-4481-9924-a5fd03cf4ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111916002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.4111916002
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.623537408
Short name T1562
Test name
Test status
Simulation time 4214454237 ps
CPU time 96.06 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:11:59 PM PST 23
Peak memory 253704 kb
Host smart-90fa4a80-d934-41c8-b201-b56566f68000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623537408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.623537408
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2121327159
Short name T1696
Test name
Test status
Simulation time 38509094707 ps
CPU time 109.03 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:12:15 PM PST 23
Peak memory 256196 kb
Host smart-1d1a5182-bd66-40b6-a7ba-df69ee18b2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121327159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2121327159
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.201388184
Short name T1508
Test name
Test status
Simulation time 13993588392 ps
CPU time 39.97 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:11:06 PM PST 23
Peak memory 236972 kb
Host smart-273f491c-2611-47b8-a687-9b6cf1c9045a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201388184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.201388184
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3024318061
Short name T784
Test name
Test status
Simulation time 1258924316 ps
CPU time 3.64 seconds
Started Dec 31 01:10:21 PM PST 23
Finished Dec 31 01:10:34 PM PST 23
Peak memory 233252 kb
Host smart-362e6715-6711-4d8e-89ce-0adc981ae26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024318061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3024318061
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_intr.2465622028
Short name T646
Test name
Test status
Simulation time 15790028052 ps
CPU time 34.72 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:11:00 PM PST 23
Peak memory 240900 kb
Host smart-3958d9e1-3574-4b8a-ae49-096fd225b9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465622028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intr.2465622028
Directory /workspace/27.spi_device_intr/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3549781923
Short name T1415
Test name
Test status
Simulation time 5967234914 ps
CPU time 18.69 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:10:44 PM PST 23
Peak memory 241456 kb
Host smart-dad44a65-5504-4054-9d7e-ace95de3a712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549781923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3549781923
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1544342529
Short name T1686
Test name
Test status
Simulation time 14785898950 ps
CPU time 11.15 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:36 PM PST 23
Peak memory 219940 kb
Host smart-a994ebda-9a79-437f-9667-7e74e03dc1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544342529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1544342529
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3055360499
Short name T1269
Test name
Test status
Simulation time 2763201681 ps
CPU time 12.06 seconds
Started Dec 31 01:10:20 PM PST 23
Finished Dec 31 01:10:41 PM PST 23
Peak memory 238040 kb
Host smart-1494cbe8-8788-4dab-8326-5717cae2f34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055360499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3055360499
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_perf.3816617075
Short name T977
Test name
Test status
Simulation time 8327404001 ps
CPU time 523.77 seconds
Started Dec 31 01:10:30 PM PST 23
Finished Dec 31 01:19:17 PM PST 23
Peak memory 270160 kb
Host smart-39898b3f-424d-4cf7-90bd-fe62fae85763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816617075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_perf.3816617075
Directory /workspace/27.spi_device_perf/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.937320327
Short name T1502
Test name
Test status
Simulation time 536073658 ps
CPU time 4.51 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:26 PM PST 23
Peak memory 234212 kb
Host smart-87acdfdd-d386-4533-b3a5-14ebe6121750
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=937320327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.937320327
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_rx_async_fifo_reset.2022814562
Short name T1356
Test name
Test status
Simulation time 16320555 ps
CPU time 0.89 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:10:27 PM PST 23
Peak memory 208488 kb
Host smart-61de5d3f-d106-4757-b4e9-99b003adb173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022814562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_rx_async_fifo_reset.2022814562
Directory /workspace/27.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/27.spi_device_rx_timeout.1186578059
Short name T938
Test name
Test status
Simulation time 903826155 ps
CPU time 5.5 seconds
Started Dec 31 01:10:34 PM PST 23
Finished Dec 31 01:10:50 PM PST 23
Peak memory 216776 kb
Host smart-e858f58c-8ea5-424d-becf-fb98038857aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186578059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_rx_timeout.1186578059
Directory /workspace/27.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/27.spi_device_smoke.2021143108
Short name T446
Test name
Test status
Simulation time 77951657 ps
CPU time 1 seconds
Started Dec 31 01:10:19 PM PST 23
Finished Dec 31 01:10:29 PM PST 23
Peak memory 208056 kb
Host smart-5ad1acf7-d90c-4857-b87e-ee04b9e727f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021143108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_smoke.2021143108
Directory /workspace/27.spi_device_smoke/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.585273414
Short name T921
Test name
Test status
Simulation time 5937971896 ps
CPU time 45.95 seconds
Started Dec 31 01:10:30 PM PST 23
Finished Dec 31 01:11:19 PM PST 23
Peak memory 216888 kb
Host smart-0511d0d7-ff5c-4be6-ac27-928c0e98d664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585273414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.585273414
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.701033027
Short name T1247
Test name
Test status
Simulation time 2795141469 ps
CPU time 9.6 seconds
Started Dec 31 01:10:33 PM PST 23
Finished Dec 31 01:10:50 PM PST 23
Peak memory 216912 kb
Host smart-5ca3640a-f3ea-435e-ad7b-1a578a116e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701033027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.701033027
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.4221060211
Short name T553
Test name
Test status
Simulation time 529429817 ps
CPU time 2.08 seconds
Started Dec 31 01:10:33 PM PST 23
Finished Dec 31 01:10:44 PM PST 23
Peak memory 216800 kb
Host smart-b8d6e810-24cc-4ced-841d-ece56ccf518e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221060211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.4221060211
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3717634298
Short name T1195
Test name
Test status
Simulation time 83534969 ps
CPU time 0.85 seconds
Started Dec 31 01:10:31 PM PST 23
Finished Dec 31 01:10:39 PM PST 23
Peak memory 206880 kb
Host smart-86cf2570-8775-4e60-81d6-63a0e7972b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717634298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3717634298
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_tx_async_fifo_reset.803714250
Short name T1076
Test name
Test status
Simulation time 58628696 ps
CPU time 0.77 seconds
Started Dec 31 01:10:33 PM PST 23
Finished Dec 31 01:10:45 PM PST 23
Peak memory 208372 kb
Host smart-c2feda39-40e6-451e-a4c4-2d75770ce87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803714250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tx_async_fifo_reset.803714250
Directory /workspace/27.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/27.spi_device_txrx.483223037
Short name T649
Test name
Test status
Simulation time 109551173087 ps
CPU time 359.2 seconds
Started Dec 31 01:10:19 PM PST 23
Finished Dec 31 01:16:26 PM PST 23
Peak memory 265112 kb
Host smart-4b20d429-effe-435d-9c3c-ccbda9b03ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483223037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_txrx.483223037
Directory /workspace/27.spi_device_txrx/latest

Test location /workspace/coverage/default/27.spi_device_upload.2726970538
Short name T292
Test name
Test status
Simulation time 27718250899 ps
CPU time 26.24 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:47 PM PST 23
Peak memory 251948 kb
Host smart-87aa8473-83d0-49ad-ad29-19177a796c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726970538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2726970538
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_abort.594870602
Short name T1213
Test name
Test status
Simulation time 21841940 ps
CPU time 0.74 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:23 PM PST 23
Peak memory 206536 kb
Host smart-78efbd1e-2957-4476-a89b-05b4c293c2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594870602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_abort.594870602
Directory /workspace/28.spi_device_abort/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2340248547
Short name T5
Test name
Test status
Simulation time 12602500 ps
CPU time 0.76 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:24 PM PST 23
Peak memory 206456 kb
Host smart-d5337541-5955-4d56-842e-a427d0fe29a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340248547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2340248547
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_bit_transfer.487108942
Short name T716
Test name
Test status
Simulation time 746641971 ps
CPU time 2.52 seconds
Started Dec 31 01:10:23 PM PST 23
Finished Dec 31 01:10:34 PM PST 23
Peak memory 216768 kb
Host smart-6d031756-226b-41c8-b27d-6cb58eadc0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487108942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_bit_transfer.487108942
Directory /workspace/28.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/28.spi_device_byte_transfer.3622672234
Short name T541
Test name
Test status
Simulation time 409364337 ps
CPU time 3.4 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:10:20 PM PST 23
Peak memory 216852 kb
Host smart-44aed083-8baa-4add-b835-cc1f7375362d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622672234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_byte_transfer.3622672234
Directory /workspace/28.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2249035835
Short name T718
Test name
Test status
Simulation time 336258068 ps
CPU time 3.75 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:24 PM PST 23
Peak memory 225044 kb
Host smart-89ee7739-0a1a-477c-919b-d38394c20263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249035835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2249035835
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1805759363
Short name T1202
Test name
Test status
Simulation time 37275514 ps
CPU time 0.71 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:22 PM PST 23
Peak memory 206564 kb
Host smart-3971afdb-7c32-4729-b8a8-c3c8f4f9ad4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805759363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1805759363
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_dummy_item_extra_dly.2849067099
Short name T880
Test name
Test status
Simulation time 68524967938 ps
CPU time 253.06 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:14:35 PM PST 23
Peak memory 304892 kb
Host smart-81a73951-e88e-4cbb-ab3c-745ac475f299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849067099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_dummy_item_extra_dly.2849067099
Directory /workspace/28.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/28.spi_device_extreme_fifo_size.4016686903
Short name T1
Test name
Test status
Simulation time 5523953366 ps
CPU time 20.47 seconds
Started Dec 31 01:10:22 PM PST 23
Finished Dec 31 01:10:51 PM PST 23
Peak memory 224108 kb
Host smart-52ca8758-3c6a-47ab-8aa6-fd3adae028aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016686903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_extreme_fifo_size.4016686903
Directory /workspace/28.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/28.spi_device_fifo_full.2358109720
Short name T491
Test name
Test status
Simulation time 42076161334 ps
CPU time 641.13 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:21:04 PM PST 23
Peak memory 273528 kb
Host smart-77b7898a-1245-4283-a55c-ec68cbabfab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358109720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_fifo_full.2358109720
Directory /workspace/28.spi_device_fifo_full/latest

Test location /workspace/coverage/default/28.spi_device_fifo_underflow_overflow.312919748
Short name T1156
Test name
Test status
Simulation time 226145222491 ps
CPU time 374.87 seconds
Started Dec 31 01:10:13 PM PST 23
Finished Dec 31 01:16:30 PM PST 23
Peak memory 389904 kb
Host smart-16d1eac4-bd2b-455a-82e2-d445fe28b124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312919748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_fifo_underflow_overfl
ow.312919748
Directory /workspace/28.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.723841333
Short name T925
Test name
Test status
Simulation time 3856111362 ps
CPU time 41.31 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:11:08 PM PST 23
Peak memory 251624 kb
Host smart-07923be1-eeef-44d5-ad13-f7b8c28e92cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723841333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.723841333
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2282723802
Short name T304
Test name
Test status
Simulation time 13561463929 ps
CPU time 132.64 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:12:34 PM PST 23
Peak memory 268416 kb
Host smart-176d9057-29e3-45d9-89b0-6f9e17ae5186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282723802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2282723802
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.4273657920
Short name T852
Test name
Test status
Simulation time 4613941439 ps
CPU time 24.3 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 01:10:42 PM PST 23
Peak memory 249776 kb
Host smart-ea2cb567-1748-4feb-bba7-f20fd5b01fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273657920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4273657920
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.358476911
Short name T1194
Test name
Test status
Simulation time 2008693408 ps
CPU time 5.96 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:10:33 PM PST 23
Peak memory 235516 kb
Host smart-b8c21192-9d34-40b6-ac7e-b271f968ed8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358476911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.358476911
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_intr.3372271011
Short name T1771
Test name
Test status
Simulation time 35613880031 ps
CPU time 68.01 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:11:34 PM PST 23
Peak memory 240304 kb
Host smart-5ace86e3-9e81-4826-97be-56f09b499d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372271011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intr.3372271011
Directory /workspace/28.spi_device_intr/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1162146179
Short name T1723
Test name
Test status
Simulation time 30679409959 ps
CPU time 24.54 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:46 PM PST 23
Peak memory 231080 kb
Host smart-f6b00493-cdca-4851-9954-88ab425f891b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162146179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1162146179
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2902756289
Short name T311
Test name
Test status
Simulation time 59978863063 ps
CPU time 34.44 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 01:10:53 PM PST 23
Peak memory 233268 kb
Host smart-eeaf5e6e-cceb-4361-b637-8de44084edcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902756289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2902756289
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1886701252
Short name T1236
Test name
Test status
Simulation time 8249705856 ps
CPU time 29.72 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:10:47 PM PST 23
Peak memory 239184 kb
Host smart-34f3bcec-2541-4d20-a9e5-711e167fd043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886701252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1886701252
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_perf.4055710444
Short name T488
Test name
Test status
Simulation time 53564055186 ps
CPU time 1622.36 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:37:18 PM PST 23
Peak memory 290692 kb
Host smart-5411d58d-bc6c-421a-9459-729f8b06845e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055710444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_perf.4055710444
Directory /workspace/28.spi_device_perf/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1839408909
Short name T1459
Test name
Test status
Simulation time 4697140864 ps
CPU time 7.11 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:10:24 PM PST 23
Peak memory 235944 kb
Host smart-1c4968e2-8e08-4a7f-bf22-337a2d537a7c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1839408909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1839408909
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_rx_async_fifo_reset.3173963177
Short name T1163
Test name
Test status
Simulation time 20797554 ps
CPU time 0.88 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 01:10:19 PM PST 23
Peak memory 208500 kb
Host smart-cff018f4-6ed4-49db-8823-36eeff98bd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173963177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_rx_async_fifo_reset.3173963177
Directory /workspace/28.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/28.spi_device_rx_timeout.836407970
Short name T462
Test name
Test status
Simulation time 3091206952 ps
CPU time 5.86 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:28 PM PST 23
Peak memory 216872 kb
Host smart-226b1ed3-83b1-41c0-b4f4-970f328c0510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836407970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_rx_timeout.836407970
Directory /workspace/28.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/28.spi_device_smoke.1411318544
Short name T513
Test name
Test status
Simulation time 31365774 ps
CPU time 1.17 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:10:18 PM PST 23
Peak memory 216864 kb
Host smart-64072639-9d36-4fde-bb86-16efea15803f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411318544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_smoke.1411318544
Directory /workspace/28.spi_device_smoke/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3188037828
Short name T148
Test name
Test status
Simulation time 28460646158 ps
CPU time 181.22 seconds
Started Dec 31 01:10:13 PM PST 23
Finished Dec 31 01:13:15 PM PST 23
Peak memory 274308 kb
Host smart-02c8cda6-cdc6-4f19-bb64-b44625df161b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188037828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3188037828
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1786165366
Short name T1726
Test name
Test status
Simulation time 12526557401 ps
CPU time 86.49 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:11:50 PM PST 23
Peak memory 221916 kb
Host smart-5ee44ab7-ee45-44b2-9ec4-1bacf0393cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786165366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1786165366
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.446597955
Short name T1468
Test name
Test status
Simulation time 1712321087 ps
CPU time 4.75 seconds
Started Dec 31 01:10:13 PM PST 23
Finished Dec 31 01:10:19 PM PST 23
Peak memory 216716 kb
Host smart-b2239b8c-d159-40e3-b431-5f143fbb2cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446597955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.446597955
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2566068641
Short name T599
Test name
Test status
Simulation time 39610137 ps
CPU time 0.96 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:23 PM PST 23
Peak memory 207792 kb
Host smart-9510da05-01cb-428d-952b-85e545151380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566068641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2566068641
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2970672035
Short name T1126
Test name
Test status
Simulation time 142919221 ps
CPU time 0.94 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:10:17 PM PST 23
Peak memory 206908 kb
Host smart-49daaed8-b454-432a-910f-0e80fe05a633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970672035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2970672035
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_tx_async_fifo_reset.2849685489
Short name T789
Test name
Test status
Simulation time 63325805 ps
CPU time 0.77 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:25 PM PST 23
Peak memory 208504 kb
Host smart-ac6a4e45-f3a5-4d8a-8d72-2e455e05b422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849685489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tx_async_fifo_reset.2849685489
Directory /workspace/28.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/28.spi_device_txrx.509637851
Short name T1155
Test name
Test status
Simulation time 76199691927 ps
CPU time 255.39 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:14:35 PM PST 23
Peak memory 257988 kb
Host smart-656759c8-62b7-45f4-800f-58659dca666f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509637851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_txrx.509637851
Directory /workspace/28.spi_device_txrx/latest

Test location /workspace/coverage/default/28.spi_device_upload.1040246421
Short name T1784
Test name
Test status
Simulation time 2167577526 ps
CPU time 9.25 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:31 PM PST 23
Peak memory 249712 kb
Host smart-8f40dad4-311c-4cf6-95fa-5fcff15bda80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040246421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1040246421
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_abort.2017568257
Short name T1767
Test name
Test status
Simulation time 51108275 ps
CPU time 0.76 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:23 PM PST 23
Peak memory 206608 kb
Host smart-49eadd40-ab6d-4849-b4cb-e3dbed7d19e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017568257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_abort.2017568257
Directory /workspace/29.spi_device_abort/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2159124018
Short name T1103
Test name
Test status
Simulation time 24390582 ps
CPU time 0.72 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:25 PM PST 23
Peak memory 206524 kb
Host smart-0bd9e1bf-e29a-4df3-88fb-b67d5856991f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159124018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2159124018
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_bit_transfer.2005795497
Short name T1494
Test name
Test status
Simulation time 158255623 ps
CPU time 2.53 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:23 PM PST 23
Peak memory 216868 kb
Host smart-04aba850-40c5-49fc-b54d-8dbabaa25ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005795497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_bit_transfer.2005795497
Directory /workspace/29.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/29.spi_device_byte_transfer.2771334654
Short name T482
Test name
Test status
Simulation time 247145942 ps
CPU time 2.68 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:10:20 PM PST 23
Peak memory 216692 kb
Host smart-ae4a1dbc-113a-46c2-ad08-c06a71a238cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771334654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_byte_transfer.2771334654
Directory /workspace/29.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3629989054
Short name T1238
Test name
Test status
Simulation time 219739416 ps
CPU time 3.19 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:26 PM PST 23
Peak memory 239964 kb
Host smart-a28183e8-7d57-49d8-8843-f86a34ad2688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629989054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3629989054
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.846880450
Short name T1530
Test name
Test status
Simulation time 57570935 ps
CPU time 0.77 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:25 PM PST 23
Peak memory 207616 kb
Host smart-b183ae2a-6e55-49d5-b786-607b95b60f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846880450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.846880450
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_dummy_item_extra_dly.955171115
Short name T1438
Test name
Test status
Simulation time 54818708064 ps
CPU time 327.62 seconds
Started Dec 31 01:10:12 PM PST 23
Finished Dec 31 01:15:40 PM PST 23
Peak memory 282212 kb
Host smart-fd6bf080-16e7-4f99-b57e-094600a8ac2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955171115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_dummy_item_extra_dly.955171115
Directory /workspace/29.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/29.spi_device_extreme_fifo_size.3888332979
Short name T255
Test name
Test status
Simulation time 614252004573 ps
CPU time 3621.6 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 02:10:41 PM PST 23
Peak memory 225204 kb
Host smart-063b7c0d-6a00-4f19-a462-2176acbe9d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888332979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_extreme_fifo_size.3888332979
Directory /workspace/29.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/29.spi_device_fifo_full.2389266809
Short name T1129
Test name
Test status
Simulation time 120221248274 ps
CPU time 1143.7 seconds
Started Dec 31 01:10:20 PM PST 23
Finished Dec 31 01:29:33 PM PST 23
Peak memory 274408 kb
Host smart-47d6ad12-b8da-4e96-ab13-60a46489818d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389266809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_fifo_full.2389266809
Directory /workspace/29.spi_device_fifo_full/latest

Test location /workspace/coverage/default/29.spi_device_fifo_underflow_overflow.3861104890
Short name T1456
Test name
Test status
Simulation time 61800880777 ps
CPU time 222.86 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:14:04 PM PST 23
Peak memory 373140 kb
Host smart-68eeba0c-ddc4-487d-8859-5725a0937cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861104890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_fifo_underflow_overf
low.3861104890
Directory /workspace/29.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2911730827
Short name T1506
Test name
Test status
Simulation time 12744876455 ps
CPU time 35.01 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:11:00 PM PST 23
Peak memory 253188 kb
Host smart-3e2638ce-f1c7-4c26-a37c-ef2e476934a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911730827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2911730827
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1179212665
Short name T227
Test name
Test status
Simulation time 92975349233 ps
CPU time 192.94 seconds
Started Dec 31 01:10:19 PM PST 23
Finished Dec 31 01:13:41 PM PST 23
Peak memory 266200 kb
Host smart-c8eeba92-782f-4113-8a20-b57160b052fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179212665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1179212665
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.480605145
Short name T191
Test name
Test status
Simulation time 97380053861 ps
CPU time 147.26 seconds
Started Dec 31 01:10:19 PM PST 23
Finished Dec 31 01:12:55 PM PST 23
Peak memory 249840 kb
Host smart-bffaa3ae-35a5-4112-8f0d-d1b4deb6da5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480605145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.480605145
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1015026612
Short name T985
Test name
Test status
Simulation time 887162054 ps
CPU time 7.42 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 01:10:25 PM PST 23
Peak memory 231884 kb
Host smart-7edeb23d-e102-4ce0-a60d-7dce8ee4dd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015026612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1015026612
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1177739000
Short name T1224
Test name
Test status
Simulation time 10910832620 ps
CPU time 7.14 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:32 PM PST 23
Peak memory 239880 kb
Host smart-4f3ca987-6f7a-46c0-b9ee-339ce0280bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177739000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1177739000
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_intr.3611991227
Short name T54
Test name
Test status
Simulation time 122816206067 ps
CPU time 127.92 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:12:30 PM PST 23
Peak memory 240832 kb
Host smart-710dd705-9894-4e50-8891-a62223a2d472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611991227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intr.3611991227
Directory /workspace/29.spi_device_intr/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.960440525
Short name T666
Test name
Test status
Simulation time 11321980275 ps
CPU time 30.05 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:10:56 PM PST 23
Peak memory 231772 kb
Host smart-b7af02ab-1e8e-4a83-8462-e3f3196f0787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960440525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.960440525
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2724574258
Short name T641
Test name
Test status
Simulation time 964985810 ps
CPU time 8.03 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:31 PM PST 23
Peak memory 230640 kb
Host smart-5ff380c1-221d-489c-a0d6-805d13679433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724574258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2724574258
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1631264724
Short name T1403
Test name
Test status
Simulation time 1841004524 ps
CPU time 3.83 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:10:31 PM PST 23
Peak memory 238856 kb
Host smart-e9fcc069-6ff9-41a1-a196-1928a5e9dad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631264724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1631264724
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_perf.3842357211
Short name T1050
Test name
Test status
Simulation time 154771170637 ps
CPU time 720.66 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:22:16 PM PST 23
Peak memory 251788 kb
Host smart-921e2602-96f3-459c-8811-d311af4edf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842357211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_perf.3842357211
Directory /workspace/29.spi_device_perf/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2561993517
Short name T518
Test name
Test status
Simulation time 374329852 ps
CPU time 5.09 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:30 PM PST 23
Peak memory 234264 kb
Host smart-1645a09b-ce6f-47e8-bf21-1729c04b5c0f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2561993517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2561993517
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_rx_async_fifo_reset.1936236030
Short name T2
Test name
Test status
Simulation time 22902830 ps
CPU time 0.88 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:23 PM PST 23
Peak memory 208368 kb
Host smart-aaad5a50-2d30-4ff0-958f-3a8841ba02b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936236030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_rx_async_fifo_reset.1936236030
Directory /workspace/29.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/29.spi_device_rx_timeout.3603091922
Short name T840
Test name
Test status
Simulation time 2116654138 ps
CPU time 5.09 seconds
Started Dec 31 01:10:20 PM PST 23
Finished Dec 31 01:10:34 PM PST 23
Peak memory 216808 kb
Host smart-844b8c46-4bd5-499e-840d-afd34886ba63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603091922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_rx_timeout.3603091922
Directory /workspace/29.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/29.spi_device_smoke.2337731670
Short name T1465
Test name
Test status
Simulation time 25379832 ps
CPU time 1.05 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:24 PM PST 23
Peak memory 208296 kb
Host smart-6cfd17ce-0d47-4252-b3e1-8f2216771fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337731670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_smoke.2337731670
Directory /workspace/29.spi_device_smoke/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3828183982
Short name T721
Test name
Test status
Simulation time 206174726249 ps
CPU time 2094.77 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:45:21 PM PST 23
Peak memory 513772 kb
Host smart-6cadebd1-058c-4b77-b34d-9472cf931250
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828183982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3828183982
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3092924464
Short name T1097
Test name
Test status
Simulation time 11036133700 ps
CPU time 32.63 seconds
Started Dec 31 01:10:15 PM PST 23
Finished Dec 31 01:10:50 PM PST 23
Peak memory 217004 kb
Host smart-582e7455-71bc-4e29-bef5-2f42c87529c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092924464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3092924464
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1516677181
Short name T99
Test name
Test status
Simulation time 1600985725 ps
CPU time 10.77 seconds
Started Dec 31 01:10:14 PM PST 23
Finished Dec 31 01:10:28 PM PST 23
Peak memory 216788 kb
Host smart-f09c6dfe-2c8f-435e-ac41-906d98c55f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516677181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1516677181
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3841833580
Short name T1047
Test name
Test status
Simulation time 59582369 ps
CPU time 1.92 seconds
Started Dec 31 01:10:17 PM PST 23
Finished Dec 31 01:10:25 PM PST 23
Peak memory 216860 kb
Host smart-694eb624-bbad-45a8-a093-c6080d03d162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841833580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3841833580
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2015191779
Short name T461
Test name
Test status
Simulation time 42444265 ps
CPU time 0.89 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:20 PM PST 23
Peak memory 206948 kb
Host smart-35b99567-bb44-419d-bef0-8c8d1bd3a1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015191779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2015191779
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_tx_async_fifo_reset.757381325
Short name T1053
Test name
Test status
Simulation time 155461160 ps
CPU time 0.76 seconds
Started Dec 31 01:10:21 PM PST 23
Finished Dec 31 01:10:31 PM PST 23
Peak memory 208448 kb
Host smart-917025cf-17ad-40c3-8485-cf4313799142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757381325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tx_async_fifo_reset.757381325
Directory /workspace/29.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/29.spi_device_txrx.791826101
Short name T504
Test name
Test status
Simulation time 59062096683 ps
CPU time 141.24 seconds
Started Dec 31 01:10:21 PM PST 23
Finished Dec 31 01:12:51 PM PST 23
Peak memory 273028 kb
Host smart-e0112403-898e-488c-a39b-ace31ee995ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791826101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_txrx.791826101
Directory /workspace/29.spi_device_txrx/latest

Test location /workspace/coverage/default/29.spi_device_upload.2347399564
Short name T1083
Test name
Test status
Simulation time 334842604 ps
CPU time 4.13 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:24 PM PST 23
Peak memory 219396 kb
Host smart-33653f1b-67b8-4b0e-985f-0bf6e8f274e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347399564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2347399564
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.146115841
Short name T521
Test name
Test status
Simulation time 46169369 ps
CPU time 0.78 seconds
Started Dec 31 01:08:57 PM PST 23
Finished Dec 31 01:09:05 PM PST 23
Peak memory 206476 kb
Host smart-570476c2-9c2d-415d-a857-57dd8cbcdf61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146115841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.146115841
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_bit_transfer.1084505648
Short name T912
Test name
Test status
Simulation time 1300728826 ps
CPU time 2.19 seconds
Started Dec 31 01:08:27 PM PST 23
Finished Dec 31 01:08:31 PM PST 23
Peak memory 216744 kb
Host smart-b1dd7da0-07da-409f-aa70-619101a6713b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084505648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_bit_transfer.1084505648
Directory /workspace/3.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/3.spi_device_byte_transfer.3809139586
Short name T1777
Test name
Test status
Simulation time 579420107 ps
CPU time 2.88 seconds
Started Dec 31 01:07:58 PM PST 23
Finished Dec 31 01:08:01 PM PST 23
Peak memory 216828 kb
Host smart-e9a0a571-bf7d-4842-8a45-145f36c76d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809139586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_byte_transfer.3809139586
Directory /workspace/3.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1528074957
Short name T1461
Test name
Test status
Simulation time 554231355 ps
CPU time 4.61 seconds
Started Dec 31 01:08:59 PM PST 23
Finished Dec 31 01:09:12 PM PST 23
Peak memory 241372 kb
Host smart-039cdc26-a11b-4bc8-a74d-3de47c383115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528074957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1528074957
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2578879835
Short name T1682
Test name
Test status
Simulation time 47903467 ps
CPU time 0.75 seconds
Started Dec 31 01:08:28 PM PST 23
Finished Dec 31 01:08:30 PM PST 23
Peak memory 207628 kb
Host smart-d476fa00-5262-43a6-8dac-09d13bcb4909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578879835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2578879835
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_dummy_item_extra_dly.3183535473
Short name T1396
Test name
Test status
Simulation time 49616259826 ps
CPU time 403.41 seconds
Started Dec 31 01:08:10 PM PST 23
Finished Dec 31 01:14:55 PM PST 23
Peak memory 257424 kb
Host smart-7fb43bdb-36d7-4c22-aeac-9480f2caa5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183535473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_dummy_item_extra_dly.3183535473
Directory /workspace/3.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/3.spi_device_extreme_fifo_size.138805470
Short name T901
Test name
Test status
Simulation time 16236803676 ps
CPU time 77.34 seconds
Started Dec 31 01:08:07 PM PST 23
Finished Dec 31 01:09:27 PM PST 23
Peak memory 233292 kb
Host smart-2ccf6e46-783c-4f0b-a061-a151aa4f3164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138805470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_extreme_fifo_size.138805470
Directory /workspace/3.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/3.spi_device_fifo_full.2760927538
Short name T1188
Test name
Test status
Simulation time 168247820063 ps
CPU time 737.65 seconds
Started Dec 31 01:08:04 PM PST 23
Finished Dec 31 01:20:24 PM PST 23
Peak memory 264820 kb
Host smart-b38e564f-06aa-4aea-a20a-c82090d30952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760927538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_fifo_full.2760927538
Directory /workspace/3.spi_device_fifo_full/latest

Test location /workspace/coverage/default/3.spi_device_fifo_underflow_overflow.3155077584
Short name T1424
Test name
Test status
Simulation time 27672787696 ps
CPU time 251.97 seconds
Started Dec 31 01:08:27 PM PST 23
Finished Dec 31 01:12:40 PM PST 23
Peak memory 385564 kb
Host smart-48a117a7-220d-4d1a-a52e-4298c67e3f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155077584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_fifo_underflow_overfl
ow.3155077584
Directory /workspace/3.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3022170229
Short name T1353
Test name
Test status
Simulation time 90921499684 ps
CPU time 60.51 seconds
Started Dec 31 01:08:56 PM PST 23
Finished Dec 31 01:10:04 PM PST 23
Peak memory 249704 kb
Host smart-b80a3460-02e6-4149-acfb-1aedfe6dfc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022170229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3022170229
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3493712106
Short name T324
Test name
Test status
Simulation time 2120205485 ps
CPU time 17.24 seconds
Started Dec 31 01:08:49 PM PST 23
Finished Dec 31 01:09:09 PM PST 23
Peak memory 223392 kb
Host smart-30cf4e41-5762-467f-9625-0d4ff5f559f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493712106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3493712106
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3770467772
Short name T1305
Test name
Test status
Simulation time 12479953223 ps
CPU time 11.82 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:09:07 PM PST 23
Peak memory 225076 kb
Host smart-4e167bc8-fae1-4234-bf7e-ae3a3842d608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770467772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3770467772
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_intr.2563975297
Short name T618
Test name
Test status
Simulation time 6119199037 ps
CPU time 49.53 seconds
Started Dec 31 01:08:02 PM PST 23
Finished Dec 31 01:08:52 PM PST 23
Peak memory 230288 kb
Host smart-33a7b005-265d-425e-bc5e-3e2012f9ad6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563975297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intr.2563975297
Directory /workspace/3.spi_device_intr/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1561733991
Short name T17
Test name
Test status
Simulation time 1325331658 ps
CPU time 7.37 seconds
Started Dec 31 01:08:55 PM PST 23
Finished Dec 31 01:09:08 PM PST 23
Peak memory 238108 kb
Host smart-fb1a367c-aa5e-4b78-9682-a95bf29e0603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561733991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1561733991
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1272654498
Short name T621
Test name
Test status
Simulation time 237007537 ps
CPU time 1.07 seconds
Started Dec 31 01:08:27 PM PST 23
Finished Dec 31 01:08:30 PM PST 23
Peak memory 218832 kb
Host smart-51691022-d197-40aa-85fc-06f46453226a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272654498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1272654498
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3585778193
Short name T51
Test name
Test status
Simulation time 5774796645 ps
CPU time 16.96 seconds
Started Dec 31 01:08:54 PM PST 23
Finished Dec 31 01:09:16 PM PST 23
Peak memory 233332 kb
Host smart-b28e6b0b-5409-4031-914c-c3c5804cf89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585778193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3585778193
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2692697121
Short name T1669
Test name
Test status
Simulation time 9803748994 ps
CPU time 10.56 seconds
Started Dec 31 01:08:48 PM PST 23
Finished Dec 31 01:09:01 PM PST 23
Peak memory 228076 kb
Host smart-9ab1be50-3433-43ef-bf9e-fc5bf1d48376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692697121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2692697121
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_perf.3077906226
Short name T587
Test name
Test status
Simulation time 57501217208 ps
CPU time 371.5 seconds
Started Dec 31 01:07:57 PM PST 23
Finished Dec 31 01:14:10 PM PST 23
Peak memory 249716 kb
Host smart-885e9838-1ee1-444d-a6cb-4e7b3c971bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077906226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_perf.3077906226
Directory /workspace/3.spi_device_perf/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.1398431823
Short name T1658
Test name
Test status
Simulation time 35467772 ps
CPU time 0.71 seconds
Started Dec 31 01:08:06 PM PST 23
Finished Dec 31 01:08:09 PM PST 23
Peak memory 216704 kb
Host smart-d0ed9e99-66f1-49d0-aea8-437175c2f8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398431823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.1398431823
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.729198543
Short name T1002
Test name
Test status
Simulation time 9168830693 ps
CPU time 6.48 seconds
Started Dec 31 01:08:56 PM PST 23
Finished Dec 31 01:09:10 PM PST 23
Peak memory 234472 kb
Host smart-35376358-7b35-4396-92ad-99a2b30af876
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=729198543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.729198543
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_rx_async_fifo_reset.3174430121
Short name T534
Test name
Test status
Simulation time 156643505 ps
CPU time 0.91 seconds
Started Dec 31 01:08:36 PM PST 23
Finished Dec 31 01:08:40 PM PST 23
Peak memory 208436 kb
Host smart-e3f20633-584c-4beb-b25c-fcd8be8e74f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174430121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_rx_async_fifo_reset.3174430121
Directory /workspace/3.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/3.spi_device_rx_timeout.1969323703
Short name T1084
Test name
Test status
Simulation time 5635474002 ps
CPU time 7.19 seconds
Started Dec 31 01:08:24 PM PST 23
Finished Dec 31 01:08:33 PM PST 23
Peak memory 216836 kb
Host smart-3db373a7-955d-4165-ab57-151f482844b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969323703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_rx_timeout.1969323703
Directory /workspace/3.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.706284863
Short name T79
Test name
Test status
Simulation time 653374627 ps
CPU time 1.06 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:08:57 PM PST 23
Peak memory 238084 kb
Host smart-4d24ad3c-050c-4bbb-aa1c-7e2dd9a95c02
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706284863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.706284863
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_smoke.2671534268
Short name T657
Test name
Test status
Simulation time 236567109 ps
CPU time 1.06 seconds
Started Dec 31 01:08:28 PM PST 23
Finished Dec 31 01:08:30 PM PST 23
Peak memory 208184 kb
Host smart-72cebb0b-11e7-46ac-95a4-a06c8154d220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671534268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_smoke.2671534268
Directory /workspace/3.spi_device_smoke/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3821376857
Short name T149
Test name
Test status
Simulation time 262379832511 ps
CPU time 1354.42 seconds
Started Dec 31 01:08:55 PM PST 23
Finished Dec 31 01:31:35 PM PST 23
Peak memory 545368 kb
Host smart-a2be3418-8c12-4a80-b277-2dabea042063
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821376857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3821376857
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1688187992
Short name T1460
Test name
Test status
Simulation time 12134771399 ps
CPU time 200.98 seconds
Started Dec 31 01:08:47 PM PST 23
Finished Dec 31 01:12:09 PM PST 23
Peak memory 216820 kb
Host smart-246f1938-b6ff-4334-923f-e9f177005669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688187992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1688187992
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2280619851
Short name T1329
Test name
Test status
Simulation time 7499306658 ps
CPU time 22.75 seconds
Started Dec 31 01:08:48 PM PST 23
Finished Dec 31 01:09:12 PM PST 23
Peak memory 216820 kb
Host smart-92afb279-2eca-44d9-bf60-8ef9f972ddb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280619851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2280619851
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2674137382
Short name T845
Test name
Test status
Simulation time 123055077 ps
CPU time 1.96 seconds
Started Dec 31 01:08:51 PM PST 23
Finished Dec 31 01:08:56 PM PST 23
Peak memory 216828 kb
Host smart-5bb7c5dd-b219-4fb7-bb8e-a9089c198ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674137382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2674137382
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1677192439
Short name T889
Test name
Test status
Simulation time 286071781 ps
CPU time 1.04 seconds
Started Dec 31 01:08:37 PM PST 23
Finished Dec 31 01:08:42 PM PST 23
Peak memory 207072 kb
Host smart-93955c7e-37c5-434f-9e26-7259f6b63b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677192439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1677192439
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_tx_async_fifo_reset.1036523523
Short name T673
Test name
Test status
Simulation time 22795141 ps
CPU time 0.77 seconds
Started Dec 31 01:08:10 PM PST 23
Finished Dec 31 01:08:12 PM PST 23
Peak memory 208428 kb
Host smart-3b7e271a-d9d2-4569-8ee7-0500077c9e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036523523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tx_async_fifo_reset.1036523523
Directory /workspace/3.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/3.spi_device_txrx.3019300848
Short name T1344
Test name
Test status
Simulation time 167605359093 ps
CPU time 542.77 seconds
Started Dec 31 01:08:05 PM PST 23
Finished Dec 31 01:17:11 PM PST 23
Peak memory 299244 kb
Host smart-fe1ca7ef-bb3d-4c8f-9ba1-17d0cc0e0551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019300848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_txrx.3019300848
Directory /workspace/3.spi_device_txrx/latest

Test location /workspace/coverage/default/3.spi_device_upload.4144355477
Short name T84
Test name
Test status
Simulation time 12815419300 ps
CPU time 41.96 seconds
Started Dec 31 01:08:54 PM PST 23
Finished Dec 31 01:09:41 PM PST 23
Peak memory 240952 kb
Host smart-9318e2b5-20ee-4b1f-a1ae-937ed9659e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144355477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.4144355477
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_abort.1814340400
Short name T881
Test name
Test status
Simulation time 14359138 ps
CPU time 0.8 seconds
Started Dec 31 01:10:51 PM PST 23
Finished Dec 31 01:10:53 PM PST 23
Peak memory 206648 kb
Host smart-034aa686-7f06-4f6f-9efd-2cf779ded876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814340400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_abort.1814340400
Directory /workspace/30.spi_device_abort/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1919759248
Short name T1153
Test name
Test status
Simulation time 52586714 ps
CPU time 0.74 seconds
Started Dec 31 01:10:35 PM PST 23
Finished Dec 31 01:10:45 PM PST 23
Peak memory 206492 kb
Host smart-70e33c8f-0066-4775-b228-3820e7e7501c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919759248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1919759248
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_bit_transfer.2161910801
Short name T1421
Test name
Test status
Simulation time 71573960 ps
CPU time 2.18 seconds
Started Dec 31 01:10:34 PM PST 23
Finished Dec 31 01:10:46 PM PST 23
Peak memory 216848 kb
Host smart-92ce9aac-8c5b-4a63-8032-c34a86fcdfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161910801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_bit_transfer.2161910801
Directory /workspace/30.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/30.spi_device_byte_transfer.743826749
Short name T1383
Test name
Test status
Simulation time 850692513 ps
CPU time 3.18 seconds
Started Dec 31 01:10:33 PM PST 23
Finished Dec 31 01:10:46 PM PST 23
Peak memory 216784 kb
Host smart-d28849da-cfbe-4137-b159-64523bfaa919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743826749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_byte_transfer.743826749
Directory /workspace/30.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3864028967
Short name T858
Test name
Test status
Simulation time 16356908 ps
CPU time 0.8 seconds
Started Dec 31 01:10:34 PM PST 23
Finished Dec 31 01:10:45 PM PST 23
Peak memory 207620 kb
Host smart-a15981d8-c5fd-4e4a-9b8f-0453fecfbb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864028967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3864028967
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_dummy_item_extra_dly.2632788759
Short name T1578
Test name
Test status
Simulation time 101194185090 ps
CPU time 199.83 seconds
Started Dec 31 01:10:20 PM PST 23
Finished Dec 31 01:13:49 PM PST 23
Peak memory 286468 kb
Host smart-7095294a-b7b0-4f92-8ef6-3d6b5f46f145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632788759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_dummy_item_extra_dly.2632788759
Directory /workspace/30.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/30.spi_device_extreme_fifo_size.2393990720
Short name T1232
Test name
Test status
Simulation time 9036475316 ps
CPU time 35.52 seconds
Started Dec 31 01:10:33 PM PST 23
Finished Dec 31 01:11:18 PM PST 23
Peak memory 236788 kb
Host smart-2b16525a-bda1-4253-b45b-1b693faf2743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393990720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_extreme_fifo_size.2393990720
Directory /workspace/30.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/30.spi_device_fifo_full.756448255
Short name T682
Test name
Test status
Simulation time 150071170687 ps
CPU time 923.3 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:25:50 PM PST 23
Peak memory 261348 kb
Host smart-56121f78-d9a2-468d-82a8-47ba181e4322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756448255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_fifo_full.756448255
Directory /workspace/30.spi_device_fifo_full/latest

Test location /workspace/coverage/default/30.spi_device_fifo_underflow_overflow.2720002971
Short name T1631
Test name
Test status
Simulation time 81241761523 ps
CPU time 370.33 seconds
Started Dec 31 01:10:19 PM PST 23
Finished Dec 31 01:16:38 PM PST 23
Peak memory 382036 kb
Host smart-87f58d5e-0ef9-403f-982c-4af9693b5624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720002971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_fifo_underflow_overf
low.2720002971
Directory /workspace/30.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.895357558
Short name T859
Test name
Test status
Simulation time 21953061107 ps
CPU time 113.62 seconds
Started Dec 31 01:10:51 PM PST 23
Finished Dec 31 01:12:46 PM PST 23
Peak memory 256832 kb
Host smart-500f3907-b154-4f58-b3f3-b5a18837c87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895357558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.895357558
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3117922312
Short name T176
Test name
Test status
Simulation time 16825059693 ps
CPU time 125.78 seconds
Started Dec 31 01:10:50 PM PST 23
Finished Dec 31 01:12:57 PM PST 23
Peak memory 254556 kb
Host smart-06a9387c-4b16-4ee7-a8f4-5f70fb58470f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117922312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3117922312
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1464599100
Short name T1588
Test name
Test status
Simulation time 899845408 ps
CPU time 9.96 seconds
Started Dec 31 01:10:50 PM PST 23
Finished Dec 31 01:11:02 PM PST 23
Peak memory 241508 kb
Host smart-0f3a77d8-7d2d-45e8-beb3-3fdcdf176727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464599100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1464599100
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1153626866
Short name T236
Test name
Test status
Simulation time 3150521918 ps
CPU time 8.81 seconds
Started Dec 31 01:10:34 PM PST 23
Finished Dec 31 01:10:53 PM PST 23
Peak memory 241488 kb
Host smart-0cbe1735-260b-4405-a19a-56497b3d40e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153626866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1153626866
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_intr.2113008127
Short name T574
Test name
Test status
Simulation time 14043523820 ps
CPU time 47.87 seconds
Started Dec 31 01:10:33 PM PST 23
Finished Dec 31 01:11:28 PM PST 23
Peak memory 232732 kb
Host smart-9b50557c-11b0-4c8a-9a60-8535f94635d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113008127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intr.2113008127
Directory /workspace/30.spi_device_intr/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3266997489
Short name T216
Test name
Test status
Simulation time 904227873 ps
CPU time 13.87 seconds
Started Dec 31 01:10:50 PM PST 23
Finished Dec 31 01:11:06 PM PST 23
Peak memory 253840 kb
Host smart-7a2d96e1-f185-4914-ae47-b18ac8e0f55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266997489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3266997489
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2806078494
Short name T1384
Test name
Test status
Simulation time 1250865563 ps
CPU time 7.53 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:11:25 PM PST 23
Peak memory 219452 kb
Host smart-08856634-f0f4-4190-a841-ee9275580def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806078494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2806078494
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_perf.3176118057
Short name T1273
Test name
Test status
Simulation time 9997908513 ps
CPU time 710.6 seconds
Started Dec 31 01:10:33 PM PST 23
Finished Dec 31 01:22:31 PM PST 23
Peak memory 273508 kb
Host smart-d3764848-df5e-48fb-b1a2-582dad5f80ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176118057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_perf.3176118057
Directory /workspace/30.spi_device_perf/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1937197459
Short name T1042
Test name
Test status
Simulation time 2038164670 ps
CPU time 7.17 seconds
Started Dec 31 01:10:49 PM PST 23
Finished Dec 31 01:10:58 PM PST 23
Peak memory 220952 kb
Host smart-37e73b35-eec3-436c-a0f0-4a108b9614ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1937197459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1937197459
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_rx_async_fifo_reset.1317200101
Short name T1609
Test name
Test status
Simulation time 46672573 ps
CPU time 0.93 seconds
Started Dec 31 01:10:35 PM PST 23
Finished Dec 31 01:10:45 PM PST 23
Peak memory 208460 kb
Host smart-b4aa895b-eb22-4786-ac6b-42dbdc4f808a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317200101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_rx_async_fifo_reset.1317200101
Directory /workspace/30.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/30.spi_device_rx_timeout.992330264
Short name T875
Test name
Test status
Simulation time 1392127827 ps
CPU time 5.71 seconds
Started Dec 31 01:10:32 PM PST 23
Finished Dec 31 01:10:45 PM PST 23
Peak memory 216752 kb
Host smart-2b6a9963-60bd-4620-a489-05267ef36155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992330264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_rx_timeout.992330264
Directory /workspace/30.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/30.spi_device_smoke.2074675411
Short name T638
Test name
Test status
Simulation time 66757854 ps
CPU time 1.12 seconds
Started Dec 31 01:10:16 PM PST 23
Finished Dec 31 01:10:21 PM PST 23
Peak memory 208136 kb
Host smart-beff66fb-1d33-445d-b806-b5e71140f6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074675411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_smoke.2074675411
Directory /workspace/30.spi_device_smoke/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2750374129
Short name T1031
Test name
Test status
Simulation time 739756672 ps
CPU time 13.15 seconds
Started Dec 31 01:10:21 PM PST 23
Finished Dec 31 01:10:43 PM PST 23
Peak memory 216984 kb
Host smart-c1e5f2e5-d7d4-4765-afb3-0418f506bd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750374129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2750374129
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3954112762
Short name T1235
Test name
Test status
Simulation time 1213095802 ps
CPU time 4.2 seconds
Started Dec 31 01:10:31 PM PST 23
Finished Dec 31 01:10:43 PM PST 23
Peak memory 216768 kb
Host smart-f9110497-71f2-4807-a406-54232d29bb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954112762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3954112762
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.4147675424
Short name T1256
Test name
Test status
Simulation time 46349216 ps
CPU time 0.85 seconds
Started Dec 31 01:10:32 PM PST 23
Finished Dec 31 01:10:39 PM PST 23
Peak memory 207244 kb
Host smart-282beb06-5443-40bf-bd62-b1c3d73141c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147675424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4147675424
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2866537745
Short name T1270
Test name
Test status
Simulation time 101176406 ps
CPU time 0.82 seconds
Started Dec 31 01:10:30 PM PST 23
Finished Dec 31 01:10:38 PM PST 23
Peak memory 206880 kb
Host smart-276d3d18-edce-41eb-8f53-b7819693f1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866537745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2866537745
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_tx_async_fifo_reset.3534299406
Short name T940
Test name
Test status
Simulation time 34431566 ps
CPU time 0.79 seconds
Started Dec 31 01:10:36 PM PST 23
Finished Dec 31 01:10:45 PM PST 23
Peak memory 208328 kb
Host smart-5c6108a6-6b81-4b47-8c91-72022817306e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534299406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tx_async_fifo_reset.3534299406
Directory /workspace/30.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/30.spi_device_txrx.3516821806
Short name T519
Test name
Test status
Simulation time 66280595751 ps
CPU time 287.44 seconds
Started Dec 31 01:10:18 PM PST 23
Finished Dec 31 01:15:13 PM PST 23
Peak memory 291916 kb
Host smart-c0c1bb8b-da2d-4537-ade8-662442ba1556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516821806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_txrx.3516821806
Directory /workspace/30.spi_device_txrx/latest

Test location /workspace/coverage/default/30.spi_device_upload.3242974252
Short name T1573
Test name
Test status
Simulation time 2424890233 ps
CPU time 9.91 seconds
Started Dec 31 01:10:52 PM PST 23
Finished Dec 31 01:11:03 PM PST 23
Peak memory 228768 kb
Host smart-a7f68c92-e1ca-4c6f-81c3-14033e91841b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242974252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3242974252
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_abort.1604889999
Short name T1346
Test name
Test status
Simulation time 41124449 ps
CPU time 0.74 seconds
Started Dec 31 01:10:51 PM PST 23
Finished Dec 31 01:10:54 PM PST 23
Peak memory 206652 kb
Host smart-22a38b46-6709-4e29-b304-6b4d0e150a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604889999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_abort.1604889999
Directory /workspace/31.spi_device_abort/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1844115366
Short name T868
Test name
Test status
Simulation time 63302828 ps
CPU time 0.73 seconds
Started Dec 31 01:11:12 PM PST 23
Finished Dec 31 01:11:13 PM PST 23
Peak memory 206400 kb
Host smart-528ddbfb-dbe0-43cf-8471-d4f77f5e4e84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844115366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1844115366
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_bit_transfer.1593755489
Short name T1283
Test name
Test status
Simulation time 273603009 ps
CPU time 2.89 seconds
Started Dec 31 01:10:51 PM PST 23
Finished Dec 31 01:10:56 PM PST 23
Peak memory 216848 kb
Host smart-f0465788-e77a-460b-b7fc-ce8138fa14b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593755489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_bit_transfer.1593755489
Directory /workspace/31.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/31.spi_device_byte_transfer.3587091884
Short name T1066
Test name
Test status
Simulation time 521754816 ps
CPU time 2.64 seconds
Started Dec 31 01:10:49 PM PST 23
Finished Dec 31 01:10:52 PM PST 23
Peak memory 216848 kb
Host smart-43702fde-a814-4d9a-b152-f2d9689cd410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587091884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_byte_transfer.3587091884
Directory /workspace/31.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3456938703
Short name T273
Test name
Test status
Simulation time 90226763 ps
CPU time 2.65 seconds
Started Dec 31 01:10:54 PM PST 23
Finished Dec 31 01:10:59 PM PST 23
Peak memory 219008 kb
Host smart-7dcec0a8-f664-4cc0-b2de-d303471e0f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456938703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3456938703
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1199444177
Short name T1364
Test name
Test status
Simulation time 19101586 ps
CPU time 0.77 seconds
Started Dec 31 01:10:51 PM PST 23
Finished Dec 31 01:10:53 PM PST 23
Peak memory 207588 kb
Host smart-a7f574d5-98e6-43e4-80d4-9503cb956ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199444177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1199444177
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_dummy_item_extra_dly.1561617832
Short name T846
Test name
Test status
Simulation time 13335479028 ps
CPU time 161.56 seconds
Started Dec 31 01:10:50 PM PST 23
Finished Dec 31 01:13:33 PM PST 23
Peak memory 250652 kb
Host smart-ed1e4875-6ba2-444a-940a-0251a0c98ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561617832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_dummy_item_extra_dly.1561617832
Directory /workspace/31.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/31.spi_device_extreme_fifo_size.2969656425
Short name T597
Test name
Test status
Simulation time 99549657186 ps
CPU time 851.94 seconds
Started Dec 31 01:10:51 PM PST 23
Finished Dec 31 01:25:05 PM PST 23
Peak memory 224928 kb
Host smart-385d2f1e-f978-4725-ae01-aa670338d2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969656425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_extreme_fifo_size.2969656425
Directory /workspace/31.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/31.spi_device_fifo_full.2580364184
Short name T1144
Test name
Test status
Simulation time 14657756372 ps
CPU time 283.08 seconds
Started Dec 31 01:10:34 PM PST 23
Finished Dec 31 01:15:27 PM PST 23
Peak memory 271852 kb
Host smart-bb0929f4-259a-4f8d-9bd3-8e49a0693449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580364184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_fifo_full.2580364184
Directory /workspace/31.spi_device_fifo_full/latest

Test location /workspace/coverage/default/31.spi_device_fifo_underflow_overflow.4171148774
Short name T184
Test name
Test status
Simulation time 264073626175 ps
CPU time 595.65 seconds
Started Dec 31 01:10:52 PM PST 23
Finished Dec 31 01:20:50 PM PST 23
Peak memory 420224 kb
Host smart-3f6eebc9-3acc-457c-83b7-2c33769a45c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171148774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_fifo_underflow_overf
low.4171148774
Directory /workspace/31.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3312700923
Short name T1381
Test name
Test status
Simulation time 27906988324 ps
CPU time 57.27 seconds
Started Dec 31 01:10:52 PM PST 23
Finished Dec 31 01:11:52 PM PST 23
Peak memory 251828 kb
Host smart-9c78b034-09c1-4d94-b599-e295e7b27598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312700923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3312700923
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2349653726
Short name T1081
Test name
Test status
Simulation time 1739073390 ps
CPU time 20.4 seconds
Started Dec 31 01:10:33 PM PST 23
Finished Dec 31 01:11:03 PM PST 23
Peak memory 234212 kb
Host smart-60f8db6d-33e5-42cb-8d33-81e2564e1697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349653726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2349653726
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.191403492
Short name T1242
Test name
Test status
Simulation time 5291464556 ps
CPU time 6.26 seconds
Started Dec 31 01:10:31 PM PST 23
Finished Dec 31 01:10:45 PM PST 23
Peak memory 238740 kb
Host smart-70fa0387-b696-4c55-9899-3c14bb87ceb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191403492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.191403492
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_intr.4134333152
Short name T844
Test name
Test status
Simulation time 195542280753 ps
CPU time 53.08 seconds
Started Dec 31 01:10:50 PM PST 23
Finished Dec 31 01:11:45 PM PST 23
Peak memory 240184 kb
Host smart-614a6463-c7fe-4718-89f2-277ab3249a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134333152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intr.4134333152
Directory /workspace/31.spi_device_intr/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1859891470
Short name T595
Test name
Test status
Simulation time 21353129791 ps
CPU time 18.23 seconds
Started Dec 31 01:10:51 PM PST 23
Finished Dec 31 01:11:11 PM PST 23
Peak memory 230332 kb
Host smart-f8bf46bc-7733-43de-b556-f3244f290ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859891470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1859891470
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.711641099
Short name T1666
Test name
Test status
Simulation time 11938043128 ps
CPU time 37.69 seconds
Started Dec 31 01:10:52 PM PST 23
Finished Dec 31 01:11:31 PM PST 23
Peak memory 226352 kb
Host smart-1218f73a-e974-43de-818a-8d6de12e161a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711641099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.711641099
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3386566538
Short name T777
Test name
Test status
Simulation time 117325070 ps
CPU time 3.85 seconds
Started Dec 31 01:10:52 PM PST 23
Finished Dec 31 01:10:58 PM PST 23
Peak memory 239524 kb
Host smart-1e355ff8-26ab-491d-90d8-a2e0402d60b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386566538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3386566538
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_perf.3958814174
Short name T924
Test name
Test status
Simulation time 125385573698 ps
CPU time 967.02 seconds
Started Dec 31 01:10:34 PM PST 23
Finished Dec 31 01:26:51 PM PST 23
Peak memory 257124 kb
Host smart-12d713e2-58a3-400b-bbc3-8c576ee98cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958814174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_perf.3958814174
Directory /workspace/31.spi_device_perf/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1493146528
Short name T1525
Test name
Test status
Simulation time 1003087966 ps
CPU time 4.01 seconds
Started Dec 31 01:10:51 PM PST 23
Finished Dec 31 01:10:56 PM PST 23
Peak memory 236004 kb
Host smart-2af71695-bd71-40d7-bc6f-ddc04af0955f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1493146528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1493146528
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_rx_async_fifo_reset.2622501180
Short name T665
Test name
Test status
Simulation time 43576833 ps
CPU time 0.94 seconds
Started Dec 31 01:10:55 PM PST 23
Finished Dec 31 01:10:59 PM PST 23
Peak memory 208492 kb
Host smart-ffe73c0e-a334-45c2-8802-215bc4e64459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622501180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_rx_async_fifo_reset.2622501180
Directory /workspace/31.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/31.spi_device_rx_timeout.3715271070
Short name T25
Test name
Test status
Simulation time 739089193 ps
CPU time 7.16 seconds
Started Dec 31 01:10:52 PM PST 23
Finished Dec 31 01:11:02 PM PST 23
Peak memory 216844 kb
Host smart-d1bc9421-51e3-496d-9fde-9bd559f2abaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715271070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_rx_timeout.3715271070
Directory /workspace/31.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/31.spi_device_smoke.3720469286
Short name T1302
Test name
Test status
Simulation time 32937233 ps
CPU time 1.18 seconds
Started Dec 31 01:10:54 PM PST 23
Finished Dec 31 01:10:58 PM PST 23
Peak memory 216868 kb
Host smart-c0e0a3fd-65fa-4146-a60c-0648495af6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720469286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_smoke.3720469286
Directory /workspace/31.spi_device_smoke/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3794493787
Short name T177
Test name
Test status
Simulation time 126424274002 ps
CPU time 615.96 seconds
Started Dec 31 01:10:54 PM PST 23
Finished Dec 31 01:21:13 PM PST 23
Peak memory 503004 kb
Host smart-535ea44e-561e-484b-912a-9d01787a06fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794493787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3794493787
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1556891774
Short name T332
Test name
Test status
Simulation time 2782604947 ps
CPU time 44.32 seconds
Started Dec 31 01:10:49 PM PST 23
Finished Dec 31 01:11:35 PM PST 23
Peak memory 217144 kb
Host smart-7f0a241d-6b95-4ff3-858d-760d4ae939df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556891774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1556891774
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1301764594
Short name T475
Test name
Test status
Simulation time 5702941427 ps
CPU time 8.64 seconds
Started Dec 31 01:10:33 PM PST 23
Finished Dec 31 01:10:50 PM PST 23
Peak memory 216820 kb
Host smart-35188675-a722-4f7f-b1b7-7e741b96b082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301764594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1301764594
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2074417401
Short name T1048
Test name
Test status
Simulation time 148090158 ps
CPU time 7.39 seconds
Started Dec 31 01:10:48 PM PST 23
Finished Dec 31 01:10:56 PM PST 23
Peak memory 216800 kb
Host smart-54a9ab52-844d-465d-9f73-51d22b53de52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074417401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2074417401
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.547156906
Short name T1717
Test name
Test status
Simulation time 85423925 ps
CPU time 0.78 seconds
Started Dec 31 01:11:13 PM PST 23
Finished Dec 31 01:11:15 PM PST 23
Peak memory 206928 kb
Host smart-64cfdc00-4f18-4e25-a9d5-cd1ee39aeaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547156906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.547156906
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_tx_async_fifo_reset.386820923
Short name T1201
Test name
Test status
Simulation time 70328460 ps
CPU time 0.82 seconds
Started Dec 31 01:10:55 PM PST 23
Finished Dec 31 01:10:59 PM PST 23
Peak memory 208372 kb
Host smart-d8dd193f-d2c0-452d-9d90-a061b1f15d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386820923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tx_async_fifo_reset.386820923
Directory /workspace/31.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/31.spi_device_txrx.673936563
Short name T1331
Test name
Test status
Simulation time 44717005819 ps
CPU time 416.68 seconds
Started Dec 31 01:10:49 PM PST 23
Finished Dec 31 01:17:47 PM PST 23
Peak memory 294000 kb
Host smart-68539b7f-c3c0-42cf-8b59-ecc1b575981c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673936563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_txrx.673936563
Directory /workspace/31.spi_device_txrx/latest

Test location /workspace/coverage/default/31.spi_device_upload.1902245482
Short name T1627
Test name
Test status
Simulation time 28693908666 ps
CPU time 22.29 seconds
Started Dec 31 01:10:53 PM PST 23
Finished Dec 31 01:11:18 PM PST 23
Peak memory 225100 kb
Host smart-0886fc87-b2de-4950-bb23-1e83725d8289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902245482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1902245482
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_abort.2048990085
Short name T1455
Test name
Test status
Simulation time 21621124 ps
CPU time 0.74 seconds
Started Dec 31 01:10:49 PM PST 23
Finished Dec 31 01:10:50 PM PST 23
Peak memory 206560 kb
Host smart-08b62327-5495-431b-8866-6e61875c4896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048990085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_abort.2048990085
Directory /workspace/32.spi_device_abort/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2221916309
Short name T1051
Test name
Test status
Simulation time 13110846 ps
CPU time 0.74 seconds
Started Dec 31 01:10:52 PM PST 23
Finished Dec 31 01:10:55 PM PST 23
Peak memory 206488 kb
Host smart-58019784-6618-43b3-9124-777436b1f07a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221916309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2221916309
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_bit_transfer.2458485571
Short name T1379
Test name
Test status
Simulation time 239796336 ps
CPU time 1.82 seconds
Started Dec 31 01:10:54 PM PST 23
Finished Dec 31 01:10:59 PM PST 23
Peak memory 216800 kb
Host smart-b2be3398-4a0e-422a-a2c2-9cd96296ab74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458485571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_bit_transfer.2458485571
Directory /workspace/32.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/32.spi_device_byte_transfer.4068243518
Short name T1112
Test name
Test status
Simulation time 107114340 ps
CPU time 2.72 seconds
Started Dec 31 01:10:51 PM PST 23
Finished Dec 31 01:10:56 PM PST 23
Peak memory 216748 kb
Host smart-ea7c5750-438a-4cb8-9114-2eb076cec09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068243518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_byte_transfer.4068243518
Directory /workspace/32.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1775910092
Short name T1537
Test name
Test status
Simulation time 2823463272 ps
CPU time 5.53 seconds
Started Dec 31 01:10:52 PM PST 23
Finished Dec 31 01:11:00 PM PST 23
Peak memory 220484 kb
Host smart-774b42c5-b12e-433c-af8a-6be1ca2f6edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775910092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1775910092
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.4201647158
Short name T575
Test name
Test status
Simulation time 45101703 ps
CPU time 0.81 seconds
Started Dec 31 01:10:53 PM PST 23
Finished Dec 31 01:10:57 PM PST 23
Peak memory 207540 kb
Host smart-4a278264-eb57-44ce-b5af-49faab85a1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201647158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.4201647158
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_dummy_item_extra_dly.1526555940
Short name T1149
Test name
Test status
Simulation time 25564902169 ps
CPU time 422.71 seconds
Started Dec 31 01:10:51 PM PST 23
Finished Dec 31 01:17:55 PM PST 23
Peak memory 252732 kb
Host smart-81860ef6-1265-4c6b-8f57-d530ed2ab8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526555940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_dummy_item_extra_dly.1526555940
Directory /workspace/32.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/32.spi_device_extreme_fifo_size.1509550936
Short name T1385
Test name
Test status
Simulation time 78796518485 ps
CPU time 843.33 seconds
Started Dec 31 01:10:51 PM PST 23
Finished Dec 31 01:24:56 PM PST 23
Peak memory 221112 kb
Host smart-5728c443-42f5-4944-83e9-28fd7d4d4e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509550936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_extreme_fifo_size.1509550936
Directory /workspace/32.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/32.spi_device_fifo_full.2941201107
Short name T1427
Test name
Test status
Simulation time 67546627463 ps
CPU time 703.91 seconds
Started Dec 31 01:11:13 PM PST 23
Finished Dec 31 01:22:58 PM PST 23
Peak memory 310136 kb
Host smart-cb83f468-1af9-46f5-bccf-bb059f2d5090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941201107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_fifo_full.2941201107
Directory /workspace/32.spi_device_fifo_full/latest

Test location /workspace/coverage/default/32.spi_device_fifo_underflow_overflow.4006955788
Short name T1673
Test name
Test status
Simulation time 62654988706 ps
CPU time 176.85 seconds
Started Dec 31 01:10:51 PM PST 23
Finished Dec 31 01:13:50 PM PST 23
Peak memory 347500 kb
Host smart-e60b55cc-8d64-4561-9bae-bbb305f84da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006955788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_fifo_underflow_overf
low.4006955788
Directory /workspace/32.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.4282552158
Short name T1566
Test name
Test status
Simulation time 53807908093 ps
CPU time 86.88 seconds
Started Dec 31 01:10:52 PM PST 23
Finished Dec 31 01:12:21 PM PST 23
Peak memory 252392 kb
Host smart-b82f5b3f-a744-4915-a73e-ec304f4a7076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282552158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.4282552158
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.613056204
Short name T30
Test name
Test status
Simulation time 42034753162 ps
CPU time 105.68 seconds
Started Dec 31 01:10:49 PM PST 23
Finished Dec 31 01:12:36 PM PST 23
Peak memory 249828 kb
Host smart-5b3b8ec0-b162-427d-b76f-7476d4cc8ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613056204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.613056204
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3669885312
Short name T307
Test name
Test status
Simulation time 15711182218 ps
CPU time 121.45 seconds
Started Dec 31 01:10:48 PM PST 23
Finished Dec 31 01:12:50 PM PST 23
Peak memory 268292 kb
Host smart-d2400184-cadf-4999-bcf6-8336269bd157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669885312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3669885312
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2146486950
Short name T1420
Test name
Test status
Simulation time 2681649535 ps
CPU time 10.23 seconds
Started Dec 31 01:10:54 PM PST 23
Finished Dec 31 01:11:08 PM PST 23
Peak memory 239128 kb
Host smart-fcef7156-8c89-4cc1-8e06-847f43a5177f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146486950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2146486950
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3824448972
Short name T654
Test name
Test status
Simulation time 5680604755 ps
CPU time 8.77 seconds
Started Dec 31 01:10:54 PM PST 23
Finished Dec 31 01:11:06 PM PST 23
Peak memory 240428 kb
Host smart-ebc05254-0e2a-41eb-bb8f-e2609647fc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824448972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3824448972
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_intr.2588501898
Short name T1778
Test name
Test status
Simulation time 5486398455 ps
CPU time 34.76 seconds
Started Dec 31 01:10:52 PM PST 23
Finished Dec 31 01:11:28 PM PST 23
Peak memory 224452 kb
Host smart-b87b9538-e2ab-4030-bd9a-9bb51294f8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588501898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intr.2588501898
Directory /workspace/32.spi_device_intr/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1327486541
Short name T1687
Test name
Test status
Simulation time 16831216272 ps
CPU time 14.87 seconds
Started Dec 31 01:10:56 PM PST 23
Finished Dec 31 01:11:13 PM PST 23
Peak memory 264644 kb
Host smart-f3e8a680-a8b8-4363-8b3e-22514564f946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327486541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1327486541
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3252765650
Short name T1266
Test name
Test status
Simulation time 1158132977 ps
CPU time 4.76 seconds
Started Dec 31 01:10:53 PM PST 23
Finished Dec 31 01:11:00 PM PST 23
Peak memory 218844 kb
Host smart-4b10b7c4-7ac2-40f2-ab46-9552ce7dd749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252765650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3252765650
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3009984698
Short name T1436
Test name
Test status
Simulation time 3890412741 ps
CPU time 6.96 seconds
Started Dec 31 01:10:53 PM PST 23
Finished Dec 31 01:11:04 PM PST 23
Peak memory 218932 kb
Host smart-ec941cfd-a37a-4582-92b4-ce96b2c66819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009984698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3009984698
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_perf.3108083911
Short name T757
Test name
Test status
Simulation time 10938497354 ps
CPU time 127.12 seconds
Started Dec 31 01:10:53 PM PST 23
Finished Dec 31 01:13:03 PM PST 23
Peak memory 273972 kb
Host smart-5b5fdf74-da91-47e1-99a2-87d6c6c6338a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108083911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_perf.3108083911
Directory /workspace/32.spi_device_perf/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2324981656
Short name T625
Test name
Test status
Simulation time 3802506734 ps
CPU time 6.47 seconds
Started Dec 31 01:10:50 PM PST 23
Finished Dec 31 01:10:58 PM PST 23
Peak memory 234784 kb
Host smart-80842f72-4919-4f1f-9f48-c599829169fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2324981656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2324981656
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_rx_async_fifo_reset.2861122763
Short name T1361
Test name
Test status
Simulation time 24184908 ps
CPU time 0.87 seconds
Started Dec 31 01:10:50 PM PST 23
Finished Dec 31 01:10:53 PM PST 23
Peak memory 208388 kb
Host smart-1a4ebd60-fcb5-4ad0-ae6f-afaf6bd64f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861122763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_rx_async_fifo_reset.2861122763
Directory /workspace/32.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/32.spi_device_rx_timeout.1397185414
Short name T1087
Test name
Test status
Simulation time 1041090838 ps
CPU time 5.48 seconds
Started Dec 31 01:10:55 PM PST 23
Finished Dec 31 01:11:04 PM PST 23
Peak memory 216820 kb
Host smart-7dfd725a-7873-436b-b93b-d570dec65bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397185414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_rx_timeout.1397185414
Directory /workspace/32.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/32.spi_device_smoke.1678437172
Short name T1543
Test name
Test status
Simulation time 81093646 ps
CPU time 1.19 seconds
Started Dec 31 01:11:13 PM PST 23
Finished Dec 31 01:11:16 PM PST 23
Peak memory 216752 kb
Host smart-62f13360-b0c3-4408-b4c1-166be30c96b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678437172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_smoke.1678437172
Directory /workspace/32.spi_device_smoke/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3724599870
Short name T1577
Test name
Test status
Simulation time 40561312176 ps
CPU time 561.55 seconds
Started Dec 31 01:10:50 PM PST 23
Finished Dec 31 01:20:13 PM PST 23
Peak memory 326704 kb
Host smart-f02b6455-bffb-4da8-8188-56c03f966dba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724599870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3724599870
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2103045089
Short name T96
Test name
Test status
Simulation time 4421787228 ps
CPU time 23.56 seconds
Started Dec 31 01:10:49 PM PST 23
Finished Dec 31 01:11:15 PM PST 23
Peak memory 216836 kb
Host smart-a98ac08d-4e6b-47d7-9704-93a758580617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103045089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2103045089
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.21613288
Short name T832
Test name
Test status
Simulation time 33816707849 ps
CPU time 20.58 seconds
Started Dec 31 01:10:56 PM PST 23
Finished Dec 31 01:11:19 PM PST 23
Peak memory 217152 kb
Host smart-9984cd43-c2b6-48ae-a20c-2e84f1204850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21613288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.21613288
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1503061549
Short name T888
Test name
Test status
Simulation time 111618463 ps
CPU time 1.09 seconds
Started Dec 31 01:10:55 PM PST 23
Finished Dec 31 01:10:59 PM PST 23
Peak memory 208324 kb
Host smart-8f173a6d-b6fb-463b-91b9-9d461e160c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503061549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1503061549
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.544149127
Short name T1277
Test name
Test status
Simulation time 200251101 ps
CPU time 1.09 seconds
Started Dec 31 01:10:53 PM PST 23
Finished Dec 31 01:10:56 PM PST 23
Peak memory 208028 kb
Host smart-522b51ad-1c76-44c9-af05-aed2e1470b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544149127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.544149127
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_tx_async_fifo_reset.2379918787
Short name T1649
Test name
Test status
Simulation time 57096544 ps
CPU time 0.81 seconds
Started Dec 31 01:10:52 PM PST 23
Finished Dec 31 01:10:55 PM PST 23
Peak memory 208420 kb
Host smart-0dee4ee7-128c-4308-a64a-64e89605e2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379918787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tx_async_fifo_reset.2379918787
Directory /workspace/32.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/32.spi_device_txrx.1967370743
Short name T572
Test name
Test status
Simulation time 84687192294 ps
CPU time 2148.27 seconds
Started Dec 31 01:10:52 PM PST 23
Finished Dec 31 01:46:42 PM PST 23
Peak memory 250764 kb
Host smart-b6df17e7-82b1-4e96-a96e-e1904c41386b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967370743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_txrx.1967370743
Directory /workspace/32.spi_device_txrx/latest

Test location /workspace/coverage/default/32.spi_device_upload.2341811639
Short name T265
Test name
Test status
Simulation time 2601751789 ps
CPU time 11.17 seconds
Started Dec 31 01:10:52 PM PST 23
Finished Dec 31 01:11:06 PM PST 23
Peak memory 234276 kb
Host smart-0a16c7a3-24d2-47aa-9328-76ddf29ba932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341811639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2341811639
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_abort.260751884
Short name T1534
Test name
Test status
Simulation time 40571855 ps
CPU time 0.74 seconds
Started Dec 31 01:10:49 PM PST 23
Finished Dec 31 01:10:52 PM PST 23
Peak memory 206588 kb
Host smart-3d78cbe4-6913-4e05-9d5f-c98eccf00224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260751884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_abort.260751884
Directory /workspace/33.spi_device_abort/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2123626180
Short name T1469
Test name
Test status
Simulation time 11843915 ps
CPU time 0.71 seconds
Started Dec 31 01:10:57 PM PST 23
Finished Dec 31 01:11:00 PM PST 23
Peak memory 206496 kb
Host smart-5cb70f56-6ad0-4fdb-8609-e127d413c5b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123626180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2123626180
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_bit_transfer.84312264
Short name T1033
Test name
Test status
Simulation time 308612216 ps
CPU time 3.35 seconds
Started Dec 31 01:10:47 PM PST 23
Finished Dec 31 01:10:52 PM PST 23
Peak memory 216588 kb
Host smart-da406549-c383-4aea-ae97-23aedc206917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84312264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_bit_transfer.84312264
Directory /workspace/33.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/33.spi_device_byte_transfer.1065583663
Short name T1710
Test name
Test status
Simulation time 1427361011 ps
CPU time 3.09 seconds
Started Dec 31 01:10:55 PM PST 23
Finished Dec 31 01:11:01 PM PST 23
Peak memory 216816 kb
Host smart-98bdc728-1c57-43f0-98ac-378694df72fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065583663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_byte_transfer.1065583663
Directory /workspace/33.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1947230623
Short name T290
Test name
Test status
Simulation time 58510361 ps
CPU time 2.89 seconds
Started Dec 31 01:10:58 PM PST 23
Finished Dec 31 01:11:03 PM PST 23
Peak memory 218980 kb
Host smart-89c87380-ce15-4e60-bd6b-1c35819bff7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947230623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1947230623
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3457478412
Short name T511
Test name
Test status
Simulation time 20532542 ps
CPU time 0.79 seconds
Started Dec 31 01:10:55 PM PST 23
Finished Dec 31 01:10:58 PM PST 23
Peak memory 207584 kb
Host smart-58b9b37f-848b-4c36-99be-3b0fad7beb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457478412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3457478412
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_dummy_item_extra_dly.2562038663
Short name T1756
Test name
Test status
Simulation time 144606038727 ps
CPU time 360.24 seconds
Started Dec 31 01:10:50 PM PST 23
Finished Dec 31 01:16:52 PM PST 23
Peak memory 283888 kb
Host smart-2db390a7-2a58-4115-9538-d2c55e35a182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562038663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_dummy_item_extra_dly.2562038663
Directory /workspace/33.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/33.spi_device_extreme_fifo_size.1143639596
Short name T1563
Test name
Test status
Simulation time 181360399880 ps
CPU time 1695.4 seconds
Started Dec 31 01:10:52 PM PST 23
Finished Dec 31 01:39:09 PM PST 23
Peak memory 225280 kb
Host smart-759820cd-c738-4529-b064-9d05487469f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143639596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_extreme_fifo_size.1143639596
Directory /workspace/33.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/33.spi_device_fifo_full.507952905
Short name T642
Test name
Test status
Simulation time 26274277171 ps
CPU time 168.02 seconds
Started Dec 31 01:10:55 PM PST 23
Finished Dec 31 01:13:46 PM PST 23
Peak memory 275208 kb
Host smart-c61b3b6e-61ff-4ae0-9793-97925d6a895a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507952905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_fifo_full.507952905
Directory /workspace/33.spi_device_fifo_full/latest

Test location /workspace/coverage/default/33.spi_device_fifo_underflow_overflow.4048172636
Short name T1610
Test name
Test status
Simulation time 135367595522 ps
CPU time 713.4 seconds
Started Dec 31 01:10:55 PM PST 23
Finished Dec 31 01:22:51 PM PST 23
Peak memory 522268 kb
Host smart-b3d0b695-f63c-4cc5-841a-1fc93e41194f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048172636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_fifo_underflow_overf
low.4048172636
Directory /workspace/33.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1430484308
Short name T815
Test name
Test status
Simulation time 1816282637 ps
CPU time 41.27 seconds
Started Dec 31 01:10:55 PM PST 23
Finished Dec 31 01:11:40 PM PST 23
Peak memory 251976 kb
Host smart-71b78b71-6c70-496d-86e4-bb1d5bb3fc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430484308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1430484308
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.4256734740
Short name T237
Test name
Test status
Simulation time 54008019942 ps
CPU time 74.92 seconds
Started Dec 31 01:10:49 PM PST 23
Finished Dec 31 01:12:05 PM PST 23
Peak memory 223748 kb
Host smart-c6ecdde6-1a0f-40ac-871c-cffcb66d88a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256734740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.4256734740
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1410020090
Short name T291
Test name
Test status
Simulation time 453963956 ps
CPU time 4.55 seconds
Started Dec 31 01:10:53 PM PST 23
Finished Dec 31 01:11:00 PM PST 23
Peak memory 238312 kb
Host smart-cc6b7ee1-75c5-4a43-a7ac-268e1ecf3cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410020090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1410020090
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_intr.1752465422
Short name T804
Test name
Test status
Simulation time 14563329852 ps
CPU time 42.12 seconds
Started Dec 31 01:10:50 PM PST 23
Finished Dec 31 01:11:34 PM PST 23
Peak memory 232648 kb
Host smart-81616aca-c13b-4eb6-8932-c136b6b5755f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752465422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intr.1752465422
Directory /workspace/33.spi_device_intr/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3906264454
Short name T1731
Test name
Test status
Simulation time 966835030 ps
CPU time 5.44 seconds
Started Dec 31 01:11:11 PM PST 23
Finished Dec 31 01:11:18 PM PST 23
Peak memory 220648 kb
Host smart-67c36af2-aa99-443e-b39e-a5db17a31baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906264454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3906264454
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3089256588
Short name T850
Test name
Test status
Simulation time 2804055829 ps
CPU time 6.09 seconds
Started Dec 31 01:10:54 PM PST 23
Finished Dec 31 01:11:03 PM PST 23
Peak memory 218736 kb
Host smart-543f6cc3-51d4-492b-8562-6a674013db7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089256588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3089256588
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2967370162
Short name T1313
Test name
Test status
Simulation time 5302837540 ps
CPU time 17.88 seconds
Started Dec 31 01:10:50 PM PST 23
Finished Dec 31 01:11:10 PM PST 23
Peak memory 238200 kb
Host smart-dc023524-93af-46e2-a6d0-d71c40c43ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967370162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2967370162
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_perf.2449842172
Short name T1554
Test name
Test status
Simulation time 18373415182 ps
CPU time 464.15 seconds
Started Dec 31 01:10:55 PM PST 23
Finished Dec 31 01:18:42 PM PST 23
Peak memory 257096 kb
Host smart-f49895de-745d-4971-9e22-22202f436165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449842172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_perf.2449842172
Directory /workspace/33.spi_device_perf/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1294187722
Short name T1152
Test name
Test status
Simulation time 1259463973 ps
CPU time 4.46 seconds
Started Dec 31 01:10:49 PM PST 23
Finished Dec 31 01:10:54 PM PST 23
Peak memory 219680 kb
Host smart-1cdf2faf-12ed-4046-87d6-d4a70ec54275
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1294187722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1294187722
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_rx_async_fifo_reset.3467425298
Short name T1243
Test name
Test status
Simulation time 35789862 ps
CPU time 0.92 seconds
Started Dec 31 01:10:49 PM PST 23
Finished Dec 31 01:10:51 PM PST 23
Peak memory 208388 kb
Host smart-0f7e5c31-8828-4164-9d4d-854b73b16c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467425298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_rx_async_fifo_reset.3467425298
Directory /workspace/33.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/33.spi_device_rx_timeout.652854452
Short name T1061
Test name
Test status
Simulation time 838101968 ps
CPU time 6.2 seconds
Started Dec 31 01:10:49 PM PST 23
Finished Dec 31 01:10:57 PM PST 23
Peak memory 216840 kb
Host smart-eabc68d8-0510-4a69-b24e-ae63514ce635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652854452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_rx_timeout.652854452
Directory /workspace/33.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/33.spi_device_smoke.551431123
Short name T526
Test name
Test status
Simulation time 31400297 ps
CPU time 1.1 seconds
Started Dec 31 01:10:52 PM PST 23
Finished Dec 31 01:10:55 PM PST 23
Peak memory 216812 kb
Host smart-48d2b948-a6f1-4158-bdfd-45dab82d3479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551431123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_smoke.551431123
Directory /workspace/33.spi_device_smoke/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2077523970
Short name T173
Test name
Test status
Simulation time 67979932704 ps
CPU time 718.48 seconds
Started Dec 31 01:11:11 PM PST 23
Finished Dec 31 01:23:10 PM PST 23
Peak memory 326000 kb
Host smart-75020894-3e87-4b64-b455-96beb83daac4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077523970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2077523970
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3159977248
Short name T1742
Test name
Test status
Simulation time 1115375252 ps
CPU time 16.15 seconds
Started Dec 31 01:10:54 PM PST 23
Finished Dec 31 01:11:13 PM PST 23
Peak memory 217244 kb
Host smart-62a8bfe6-be7c-4e38-ae86-bc7a86fb1f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159977248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3159977248
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.986733926
Short name T98
Test name
Test status
Simulation time 221564210 ps
CPU time 1.13 seconds
Started Dec 31 01:10:49 PM PST 23
Finished Dec 31 01:10:52 PM PST 23
Peak memory 207960 kb
Host smart-7da9809e-92d5-49fc-80e3-536dd65709c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986733926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.986733926
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2550606334
Short name T1448
Test name
Test status
Simulation time 344828524 ps
CPU time 1.05 seconds
Started Dec 31 01:11:13 PM PST 23
Finished Dec 31 01:11:15 PM PST 23
Peak memory 208048 kb
Host smart-af78ecea-c808-41ac-ba52-ff351782fe0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550606334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2550606334
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.241620567
Short name T1653
Test name
Test status
Simulation time 161911169 ps
CPU time 0.9 seconds
Started Dec 31 01:10:49 PM PST 23
Finished Dec 31 01:10:52 PM PST 23
Peak memory 206844 kb
Host smart-62d36bea-0570-4eed-a3ae-fe3edae95867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241620567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.241620567
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_tx_async_fifo_reset.3840453646
Short name T561
Test name
Test status
Simulation time 32103814 ps
CPU time 0.8 seconds
Started Dec 31 01:10:54 PM PST 23
Finished Dec 31 01:10:58 PM PST 23
Peak memory 208452 kb
Host smart-88af8c37-ac1c-454f-a098-541687053a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840453646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tx_async_fifo_reset.3840453646
Directory /workspace/33.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/33.spi_device_txrx.2174273224
Short name T1753
Test name
Test status
Simulation time 85383281205 ps
CPU time 126.03 seconds
Started Dec 31 01:10:51 PM PST 23
Finished Dec 31 01:12:59 PM PST 23
Peak memory 258404 kb
Host smart-7aafb84b-22b1-48b7-aa58-12ea4486c726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174273224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_txrx.2174273224
Directory /workspace/33.spi_device_txrx/latest

Test location /workspace/coverage/default/33.spi_device_upload.1432004316
Short name T267
Test name
Test status
Simulation time 17413258741 ps
CPU time 21.76 seconds
Started Dec 31 01:10:48 PM PST 23
Finished Dec 31 01:11:11 PM PST 23
Peak memory 237020 kb
Host smart-6eb595cf-b790-46c7-a510-0a66cf43a3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432004316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1432004316
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_abort.3970743738
Short name T893
Test name
Test status
Simulation time 15695427 ps
CPU time 0.75 seconds
Started Dec 31 01:10:53 PM PST 23
Finished Dec 31 01:10:57 PM PST 23
Peak memory 206640 kb
Host smart-5fa1879d-601f-4497-83be-315feeb744e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970743738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_abort.3970743738
Directory /workspace/34.spi_device_abort/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2344990766
Short name T1450
Test name
Test status
Simulation time 41711277 ps
CPU time 0.7 seconds
Started Dec 31 01:11:13 PM PST 23
Finished Dec 31 01:11:15 PM PST 23
Peak memory 206396 kb
Host smart-af1fd4cc-944f-4620-800b-ac2504897c43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344990766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2344990766
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_byte_transfer.2914769082
Short name T1186
Test name
Test status
Simulation time 172613993 ps
CPU time 2.94 seconds
Started Dec 31 01:11:17 PM PST 23
Finished Dec 31 01:11:24 PM PST 23
Peak memory 216828 kb
Host smart-a4dc1617-3fa4-4820-9813-866d7fa61f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914769082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_byte_transfer.2914769082
Directory /workspace/34.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2021213415
Short name T1210
Test name
Test status
Simulation time 491283043 ps
CPU time 4.43 seconds
Started Dec 31 01:10:49 PM PST 23
Finished Dec 31 01:10:54 PM PST 23
Peak memory 225028 kb
Host smart-4588170b-e3cd-4ebb-8123-3c3a42aea5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021213415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2021213415
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2341793287
Short name T1105
Test name
Test status
Simulation time 20047188 ps
CPU time 0.78 seconds
Started Dec 31 01:10:57 PM PST 23
Finished Dec 31 01:11:00 PM PST 23
Peak memory 207544 kb
Host smart-9a08bc26-fe72-44a4-bab3-acbdef3aa836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341793287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2341793287
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_dummy_item_extra_dly.3687050886
Short name T484
Test name
Test status
Simulation time 64042224325 ps
CPU time 857.81 seconds
Started Dec 31 01:10:57 PM PST 23
Finished Dec 31 01:25:17 PM PST 23
Peak memory 317328 kb
Host smart-0f199224-21b5-488e-be48-7af0d0451ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687050886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_dummy_item_extra_dly.3687050886
Directory /workspace/34.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/34.spi_device_extreme_fifo_size.3978595763
Short name T1390
Test name
Test status
Simulation time 45779080835 ps
CPU time 109.79 seconds
Started Dec 31 01:11:21 PM PST 23
Finished Dec 31 01:13:16 PM PST 23
Peak memory 220316 kb
Host smart-22147608-fe9d-4eaf-9da4-4c917228569a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978595763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_extreme_fifo_size.3978595763
Directory /workspace/34.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/34.spi_device_fifo_full.3742651947
Short name T1432
Test name
Test status
Simulation time 202390105402 ps
CPU time 949.42 seconds
Started Dec 31 01:10:58 PM PST 23
Finished Dec 31 01:26:49 PM PST 23
Peak memory 257668 kb
Host smart-39cff9d0-afbd-42f1-8f9a-9fc5d74a4ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742651947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_fifo_full.3742651947
Directory /workspace/34.spi_device_fifo_full/latest

Test location /workspace/coverage/default/34.spi_device_fifo_underflow_overflow.2147594753
Short name T988
Test name
Test status
Simulation time 225604509585 ps
CPU time 320.62 seconds
Started Dec 31 01:10:57 PM PST 23
Finished Dec 31 01:16:20 PM PST 23
Peak memory 330716 kb
Host smart-78950e0d-2612-461b-ace7-97cc0d8180ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147594753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_fifo_underflow_overf
low.2147594753
Directory /workspace/34.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.4276937126
Short name T6
Test name
Test status
Simulation time 48233870507 ps
CPU time 123.98 seconds
Started Dec 31 01:10:54 PM PST 23
Finished Dec 31 01:13:01 PM PST 23
Peak memory 274156 kb
Host smart-6ae5ea5a-87e1-400d-b2db-668a5f949c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276937126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.4276937126
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1382247282
Short name T632
Test name
Test status
Simulation time 17329807794 ps
CPU time 6.56 seconds
Started Dec 31 01:10:50 PM PST 23
Finished Dec 31 01:10:58 PM PST 23
Peak memory 219904 kb
Host smart-eb762e91-2a75-4ed0-88bd-0e8cf1ef47e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382247282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1382247282
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_intr.3727822879
Short name T1617
Test name
Test status
Simulation time 15755621680 ps
CPU time 14.32 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:37 PM PST 23
Peak memory 222680 kb
Host smart-84002c7b-1663-4386-ab35-7c0020105e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727822879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intr.3727822879
Directory /workspace/34.spi_device_intr/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.197216179
Short name T1679
Test name
Test status
Simulation time 31038299508 ps
CPU time 47.18 seconds
Started Dec 31 01:10:50 PM PST 23
Finished Dec 31 01:11:39 PM PST 23
Peak memory 233156 kb
Host smart-4596f98a-fe3d-492d-8ced-7478cf10bdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197216179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.197216179
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.268783282
Short name T1145
Test name
Test status
Simulation time 1635436371 ps
CPU time 7.76 seconds
Started Dec 31 01:10:51 PM PST 23
Finished Dec 31 01:11:01 PM PST 23
Peak memory 233200 kb
Host smart-ec2c2ec9-af10-479f-9ee7-e90d9fa8b187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268783282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.268783282
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1578588563
Short name T1289
Test name
Test status
Simulation time 22545923600 ps
CPU time 12.88 seconds
Started Dec 31 01:10:52 PM PST 23
Finished Dec 31 01:11:07 PM PST 23
Peak memory 221188 kb
Host smart-8e57fc86-4622-45cf-91bc-0cf05f0be2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578588563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1578588563
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_perf.3891968025
Short name T897
Test name
Test status
Simulation time 16696162344 ps
CPU time 1081.45 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:29:18 PM PST 23
Peak memory 249756 kb
Host smart-d5bae6dc-a6a2-45f6-93d0-f6e868847221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891968025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_perf.3891968025
Directory /workspace/34.spi_device_perf/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2395001578
Short name T1646
Test name
Test status
Simulation time 426151883 ps
CPU time 5.11 seconds
Started Dec 31 01:10:49 PM PST 23
Finished Dec 31 01:10:55 PM PST 23
Peak memory 234360 kb
Host smart-5025c0e4-9993-440b-b88d-2fb5aee24174
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2395001578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2395001578
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_rx_async_fifo_reset.1899245770
Short name T790
Test name
Test status
Simulation time 71373194 ps
CPU time 0.87 seconds
Started Dec 31 01:10:55 PM PST 23
Finished Dec 31 01:10:59 PM PST 23
Peak memory 208500 kb
Host smart-93ef19d6-a9e5-4d85-8fb2-1eb8dca88740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899245770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_rx_async_fifo_reset.1899245770
Directory /workspace/34.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/34.spi_device_rx_timeout.4096374026
Short name T105
Test name
Test status
Simulation time 470263938 ps
CPU time 5.2 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:11:24 PM PST 23
Peak memory 216880 kb
Host smart-21633e87-d07c-474f-a7e5-4f94862dce47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096374026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_rx_timeout.4096374026
Directory /workspace/34.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/34.spi_device_smoke.571758113
Short name T203
Test name
Test status
Simulation time 128072439 ps
CPU time 1.35 seconds
Started Dec 31 01:11:13 PM PST 23
Finished Dec 31 01:11:15 PM PST 23
Peak memory 216828 kb
Host smart-1d684c4c-a2db-41a4-b364-5ffee6f9cc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571758113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_smoke.571758113
Directory /workspace/34.spi_device_smoke/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.185525842
Short name T331
Test name
Test status
Simulation time 7972282362 ps
CPU time 28.94 seconds
Started Dec 31 01:10:58 PM PST 23
Finished Dec 31 01:11:29 PM PST 23
Peak memory 220776 kb
Host smart-1acf976e-d04a-478f-a81e-53abd447d956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185525842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.185525842
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2529150453
Short name T785
Test name
Test status
Simulation time 377152233 ps
CPU time 2.82 seconds
Started Dec 31 01:10:50 PM PST 23
Finished Dec 31 01:10:54 PM PST 23
Peak memory 216736 kb
Host smart-ebc1f8d5-0b60-490e-8123-67a51cb8fe5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529150453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2529150453
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.159566176
Short name T1088
Test name
Test status
Simulation time 798792078 ps
CPU time 3.5 seconds
Started Dec 31 01:10:49 PM PST 23
Finished Dec 31 01:10:54 PM PST 23
Peak memory 216768 kb
Host smart-2d9e84ee-5a9e-4750-8ce4-3a8e5b31f474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159566176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.159566176
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2024388034
Short name T1642
Test name
Test status
Simulation time 1075995919 ps
CPU time 1.17 seconds
Started Dec 31 01:10:49 PM PST 23
Finished Dec 31 01:10:52 PM PST 23
Peak memory 207972 kb
Host smart-949f4c0d-da47-4ecd-b968-13bc8aa28925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024388034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2024388034
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_tx_async_fifo_reset.1647568056
Short name T1392
Test name
Test status
Simulation time 57185354 ps
CPU time 0.77 seconds
Started Dec 31 01:11:13 PM PST 23
Finished Dec 31 01:11:15 PM PST 23
Peak memory 208444 kb
Host smart-4217d096-f365-4509-bc5e-b45e78df4932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647568056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tx_async_fifo_reset.1647568056
Directory /workspace/34.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/34.spi_device_txrx.2633452733
Short name T1757
Test name
Test status
Simulation time 234273038354 ps
CPU time 364.44 seconds
Started Dec 31 01:10:55 PM PST 23
Finished Dec 31 01:17:02 PM PST 23
Peak memory 295808 kb
Host smart-18f911d2-a70c-48d7-8e4b-ee7300cb3642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633452733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_txrx.2633452733
Directory /workspace/34.spi_device_txrx/latest

Test location /workspace/coverage/default/34.spi_device_upload.1786708910
Short name T1054
Test name
Test status
Simulation time 27505535248 ps
CPU time 23.68 seconds
Started Dec 31 01:10:54 PM PST 23
Finished Dec 31 01:11:20 PM PST 23
Peak memory 233256 kb
Host smart-e5f2923f-404b-45d9-a8e6-227c4e15b204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786708910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1786708910
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_abort.1984686029
Short name T660
Test name
Test status
Simulation time 65859617 ps
CPU time 0.76 seconds
Started Dec 31 01:11:22 PM PST 23
Finished Dec 31 01:11:28 PM PST 23
Peak memory 206608 kb
Host smart-0f048f35-fa58-42b6-9419-ac44473598fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984686029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_abort.1984686029
Directory /workspace/35.spi_device_abort/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1752635961
Short name T932
Test name
Test status
Simulation time 38916142 ps
CPU time 0.72 seconds
Started Dec 31 01:11:23 PM PST 23
Finished Dec 31 01:11:28 PM PST 23
Peak memory 206528 kb
Host smart-93edd2f9-3df3-4cc4-81e3-0a0315dd8841
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752635961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1752635961
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_bit_transfer.1738093537
Short name T510
Test name
Test status
Simulation time 1152188220 ps
CPU time 2.82 seconds
Started Dec 31 01:11:19 PM PST 23
Finished Dec 31 01:11:26 PM PST 23
Peak memory 216896 kb
Host smart-c2cabcaf-1c19-47db-bb8d-03f5081e7535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738093537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_bit_transfer.1738093537
Directory /workspace/35.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/35.spi_device_byte_transfer.1362507956
Short name T1253
Test name
Test status
Simulation time 317448055 ps
CPU time 2.99 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:11:19 PM PST 23
Peak memory 216868 kb
Host smart-3ae52c25-df64-4042-a1b7-6a81449efd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362507956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_byte_transfer.1362507956
Directory /workspace/35.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3259283697
Short name T1387
Test name
Test status
Simulation time 76751374 ps
CPU time 3.18 seconds
Started Dec 31 01:11:20 PM PST 23
Finished Dec 31 01:11:28 PM PST 23
Peak memory 238324 kb
Host smart-a743315f-9ebc-476b-a1d8-4df9bda7abb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259283697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3259283697
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3150560113
Short name T1664
Test name
Test status
Simulation time 280068896 ps
CPU time 0.78 seconds
Started Dec 31 01:11:17 PM PST 23
Finished Dec 31 01:11:21 PM PST 23
Peak memory 206576 kb
Host smart-13ade561-5194-4eea-ba56-afd9ed9e3d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150560113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3150560113
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_dummy_item_extra_dly.1909909335
Short name T715
Test name
Test status
Simulation time 146754407229 ps
CPU time 1546.63 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:37:05 PM PST 23
Peak memory 277224 kb
Host smart-e290d540-10a7-423b-9a5c-83e7512c708d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909909335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_dummy_item_extra_dly.1909909335
Directory /workspace/35.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/35.spi_device_extreme_fifo_size.3345912305
Short name T915
Test name
Test status
Simulation time 219683340071 ps
CPU time 779.79 seconds
Started Dec 31 01:10:55 PM PST 23
Finished Dec 31 01:23:58 PM PST 23
Peak memory 216948 kb
Host smart-7e369bf4-f2cc-4b2c-ab5a-59b58f2769aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345912305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_extreme_fifo_size.3345912305
Directory /workspace/35.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/35.spi_device_fifo_full.3702930347
Short name T1265
Test name
Test status
Simulation time 9340581527 ps
CPU time 195.85 seconds
Started Dec 31 01:10:55 PM PST 23
Finished Dec 31 01:14:14 PM PST 23
Peak memory 278808 kb
Host smart-fea6d1bc-29b1-4bfb-bd09-7a7337308f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702930347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_fifo_full.3702930347
Directory /workspace/35.spi_device_fifo_full/latest

Test location /workspace/coverage/default/35.spi_device_fifo_underflow_overflow.3398624996
Short name T182
Test name
Test status
Simulation time 278094862586 ps
CPU time 462.01 seconds
Started Dec 31 01:11:12 PM PST 23
Finished Dec 31 01:18:56 PM PST 23
Peak memory 343880 kb
Host smart-de225476-cabb-4d7c-b81a-12a9d38525d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398624996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_fifo_underflow_overf
low.3398624996
Directory /workspace/35.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3417392796
Short name T286
Test name
Test status
Simulation time 72539763673 ps
CPU time 198.09 seconds
Started Dec 31 01:11:23 PM PST 23
Finished Dec 31 01:14:45 PM PST 23
Peak memory 249768 kb
Host smart-6fca2dca-ad14-44f8-a098-a839454417e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417392796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3417392796
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2393114765
Short name T1001
Test name
Test status
Simulation time 1865461914 ps
CPU time 31.26 seconds
Started Dec 31 01:11:23 PM PST 23
Finished Dec 31 01:11:58 PM PST 23
Peak memory 240816 kb
Host smart-f62bf4ce-e965-44f9-ad2b-b15172249d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393114765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2393114765
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1853187941
Short name T1505
Test name
Test status
Simulation time 8042102696 ps
CPU time 9.79 seconds
Started Dec 31 01:11:21 PM PST 23
Finished Dec 31 01:11:36 PM PST 23
Peak memory 238596 kb
Host smart-3eb75f39-2ef3-47f1-8fe3-f5032d7f6b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853187941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1853187941
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_intr.789124566
Short name T764
Test name
Test status
Simulation time 24402097169 ps
CPU time 52.93 seconds
Started Dec 31 01:10:52 PM PST 23
Finished Dec 31 01:11:48 PM PST 23
Peak memory 240144 kb
Host smart-1dcbdfdc-89d7-4e6d-9f0c-b1f997187502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789124566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intr.789124566
Directory /workspace/35.spi_device_intr/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3148162382
Short name T288
Test name
Test status
Simulation time 10071780863 ps
CPU time 34.79 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:11:53 PM PST 23
Peak memory 255252 kb
Host smart-eab4b6bd-75a2-4270-9d90-785a0fa51d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148162382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3148162382
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1766041074
Short name T321
Test name
Test status
Simulation time 4288022111 ps
CPU time 7.08 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:29 PM PST 23
Peak memory 239852 kb
Host smart-1b0b10de-9750-4aab-9945-dedbe6318705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766041074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1766041074
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3897615215
Short name T1754
Test name
Test status
Simulation time 8100476022 ps
CPU time 12 seconds
Started Dec 31 01:11:19 PM PST 23
Finished Dec 31 01:11:36 PM PST 23
Peak memory 223312 kb
Host smart-9a6398e2-9d58-4b94-a289-91c086c282a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897615215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3897615215
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_perf.2884915442
Short name T1752
Test name
Test status
Simulation time 47925277581 ps
CPU time 2761.81 seconds
Started Dec 31 01:10:54 PM PST 23
Finished Dec 31 01:57:00 PM PST 23
Peak memory 299032 kb
Host smart-f5819640-4be0-4d0b-883f-ca53502777e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884915442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_perf.2884915442
Directory /workspace/35.spi_device_perf/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.4285565162
Short name T939
Test name
Test status
Simulation time 4874593606 ps
CPU time 6.4 seconds
Started Dec 31 01:11:38 PM PST 23
Finished Dec 31 01:11:45 PM PST 23
Peak memory 220852 kb
Host smart-83b9a030-0d60-4d16-8e13-770a5d959a43
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4285565162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.4285565162
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_rx_async_fifo_reset.3959233404
Short name T538
Test name
Test status
Simulation time 26218875 ps
CPU time 0.9 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:23 PM PST 23
Peak memory 208504 kb
Host smart-4b60d7d1-33e2-4ca0-be74-2273f0dadbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959233404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_rx_async_fifo_reset.3959233404
Directory /workspace/35.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/35.spi_device_rx_timeout.3372062034
Short name T928
Test name
Test status
Simulation time 1784133873 ps
CPU time 6.87 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:11:24 PM PST 23
Peak memory 216788 kb
Host smart-c03bedec-1ee1-4915-abd7-8b0219c7fc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372062034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_rx_timeout.3372062034
Directory /workspace/35.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/35.spi_device_smoke.4022687972
Short name T532
Test name
Test status
Simulation time 20007516 ps
CPU time 1.05 seconds
Started Dec 31 01:10:58 PM PST 23
Finished Dec 31 01:11:00 PM PST 23
Peak memory 216556 kb
Host smart-6ffc4aef-6551-4760-9d17-c39c82d1eaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022687972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_smoke.4022687972
Directory /workspace/35.spi_device_smoke/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3330656047
Short name T326
Test name
Test status
Simulation time 4245530999 ps
CPU time 33.78 seconds
Started Dec 31 01:11:13 PM PST 23
Finished Dec 31 01:11:49 PM PST 23
Peak memory 216808 kb
Host smart-e6276550-92b2-4749-b7c2-1e90bb32e712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330656047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3330656047
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.4254657298
Short name T835
Test name
Test status
Simulation time 151506700 ps
CPU time 1.15 seconds
Started Dec 31 01:10:57 PM PST 23
Finished Dec 31 01:11:00 PM PST 23
Peak memory 207940 kb
Host smart-e422de0d-4c97-4164-96eb-2114142d6b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254657298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.4254657298
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1849448159
Short name T1207
Test name
Test status
Simulation time 596336145 ps
CPU time 2.23 seconds
Started Dec 31 01:11:17 PM PST 23
Finished Dec 31 01:11:23 PM PST 23
Peak memory 216780 kb
Host smart-963e46f7-5eb2-4c26-ad0e-277b2f9d2c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849448159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1849448159
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2064055283
Short name T637
Test name
Test status
Simulation time 1271882544 ps
CPU time 1.02 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:23 PM PST 23
Peak memory 207936 kb
Host smart-801ceb8e-13cf-45c6-98a0-f454606c512d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064055283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2064055283
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_tx_async_fifo_reset.949205750
Short name T1359
Test name
Test status
Simulation time 16336652 ps
CPU time 0.8 seconds
Started Dec 31 01:11:19 PM PST 23
Finished Dec 31 01:11:24 PM PST 23
Peak memory 208468 kb
Host smart-b475e2fa-9cd4-4ff6-82b0-a07a067e59fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949205750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tx_async_fifo_reset.949205750
Directory /workspace/35.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/35.spi_device_txrx.1815089965
Short name T807
Test name
Test status
Simulation time 75918739331 ps
CPU time 421 seconds
Started Dec 31 01:10:50 PM PST 23
Finished Dec 31 01:17:53 PM PST 23
Peak memory 282684 kb
Host smart-e562c50b-1e0c-497d-b388-88336e83f6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815089965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_txrx.1815089965
Directory /workspace/35.spi_device_txrx/latest

Test location /workspace/coverage/default/35.spi_device_upload.2238964971
Short name T52
Test name
Test status
Simulation time 1148765211 ps
CPU time 5.95 seconds
Started Dec 31 01:11:20 PM PST 23
Finished Dec 31 01:11:31 PM PST 23
Peak memory 225024 kb
Host smart-2ae09f5e-b5a5-49b1-b76a-f426c9c86a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238964971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2238964971
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_abort.998451218
Short name T53
Test name
Test status
Simulation time 54755345 ps
CPU time 0.75 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:11:17 PM PST 23
Peak memory 206444 kb
Host smart-7f687e83-bc2b-4c98-983d-3293a9cc4a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998451218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_abort.998451218
Directory /workspace/36.spi_device_abort/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1639468713
Short name T476
Test name
Test status
Simulation time 28971885 ps
CPU time 0.69 seconds
Started Dec 31 01:11:19 PM PST 23
Finished Dec 31 01:11:24 PM PST 23
Peak memory 206520 kb
Host smart-3e9b53dd-3bff-4cac-b4f2-55d34a508c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639468713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1639468713
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_bit_transfer.40481257
Short name T894
Test name
Test status
Simulation time 178052162 ps
CPU time 2.19 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:11:18 PM PST 23
Peak memory 216820 kb
Host smart-971b659a-04d3-4fe9-89d1-aa246a43d960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40481257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_bit_transfer.40481257
Directory /workspace/36.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/36.spi_device_byte_transfer.2677076010
Short name T787
Test name
Test status
Simulation time 68565122 ps
CPU time 2.47 seconds
Started Dec 31 01:11:46 PM PST 23
Finished Dec 31 01:11:49 PM PST 23
Peak memory 216912 kb
Host smart-021ff76c-5d5c-4434-be53-a0f22bf50fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677076010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_byte_transfer.2677076010
Directory /workspace/36.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.376044659
Short name T872
Test name
Test status
Simulation time 868604889 ps
CPU time 4.81 seconds
Started Dec 31 01:10:57 PM PST 23
Finished Dec 31 01:11:04 PM PST 23
Peak memory 218720 kb
Host smart-782213e7-89b7-4cd4-bf0d-3f6544c2c96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376044659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.376044659
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1585907231
Short name T445
Test name
Test status
Simulation time 13744542 ps
CPU time 0.78 seconds
Started Dec 31 01:11:36 PM PST 23
Finished Dec 31 01:11:37 PM PST 23
Peak memory 207580 kb
Host smart-45a1f3bf-65b8-4067-b9bc-93885475c547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585907231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1585907231
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_dummy_item_extra_dly.166641316
Short name T727
Test name
Test status
Simulation time 82619424429 ps
CPU time 201.81 seconds
Started Dec 31 01:11:42 PM PST 23
Finished Dec 31 01:15:05 PM PST 23
Peak memory 290324 kb
Host smart-059d31b4-3f70-43fa-9314-55e908420063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166641316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_dummy_item_extra_dly.166641316
Directory /workspace/36.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/36.spi_device_extreme_fifo_size.2833704174
Short name T1034
Test name
Test status
Simulation time 109449457038 ps
CPU time 2379.66 seconds
Started Dec 31 01:11:36 PM PST 23
Finished Dec 31 01:51:17 PM PST 23
Peak memory 220060 kb
Host smart-76423203-44b4-4c4f-bc62-cea714f04936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833704174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_extreme_fifo_size.2833704174
Directory /workspace/36.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/36.spi_device_fifo_full.1066661825
Short name T1314
Test name
Test status
Simulation time 98472672374 ps
CPU time 461.9 seconds
Started Dec 31 01:11:39 PM PST 23
Finished Dec 31 01:19:21 PM PST 23
Peak memory 304284 kb
Host smart-6917ae67-1df4-46bf-bc31-37da14405791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066661825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_fifo_full.1066661825
Directory /workspace/36.spi_device_fifo_full/latest

Test location /workspace/coverage/default/36.spi_device_fifo_underflow_overflow.2712722993
Short name T1605
Test name
Test status
Simulation time 205374585028 ps
CPU time 1022.73 seconds
Started Dec 31 01:11:40 PM PST 23
Finished Dec 31 01:28:45 PM PST 23
Peak memory 637136 kb
Host smart-4327da87-105e-4579-8e79-8e86df0380fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712722993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_fifo_underflow_overf
low.2712722993
Directory /workspace/36.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1567931944
Short name T242
Test name
Test status
Simulation time 68206648343 ps
CPU time 465.93 seconds
Started Dec 31 01:11:21 PM PST 23
Finished Dec 31 01:19:12 PM PST 23
Peak memory 261028 kb
Host smart-56fdf187-dafb-4b81-b567-7d7a6e563d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567931944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1567931944
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3309867757
Short name T1495
Test name
Test status
Simulation time 42084858277 ps
CPU time 168.02 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:14:04 PM PST 23
Peak memory 251856 kb
Host smart-c5d33b39-6eba-4ab0-bab9-f1d829c01f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309867757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3309867757
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.420437639
Short name T694
Test name
Test status
Simulation time 59288525604 ps
CPU time 76.14 seconds
Started Dec 31 01:10:57 PM PST 23
Finished Dec 31 01:12:15 PM PST 23
Peak memory 250668 kb
Host smart-dab99d49-05a3-4b1b-afb7-22ca0275a13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420437639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.420437639
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1498747359
Short name T1374
Test name
Test status
Simulation time 530891797 ps
CPU time 6.24 seconds
Started Dec 31 01:11:12 PM PST 23
Finished Dec 31 01:11:20 PM PST 23
Peak memory 219120 kb
Host smart-611f1472-74fb-4f2e-ad82-fdf40bed44bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498747359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1498747359
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_intr.386375445
Short name T81
Test name
Test status
Simulation time 28156675323 ps
CPU time 55.71 seconds
Started Dec 31 01:12:06 PM PST 23
Finished Dec 31 01:13:03 PM PST 23
Peak memory 240772 kb
Host smart-c3ec5d1d-8546-4204-b821-ef18c6998844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386375445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intr.386375445
Directory /workspace/36.spi_device_intr/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2737739792
Short name T1161
Test name
Test status
Simulation time 1345269991 ps
CPU time 6.85 seconds
Started Dec 31 01:10:55 PM PST 23
Finished Dec 31 01:11:05 PM PST 23
Peak memory 238176 kb
Host smart-acb30f57-4334-4362-abc0-c71686bef6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737739792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2737739792
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2360053895
Short name T1786
Test name
Test status
Simulation time 55629381186 ps
CPU time 40.15 seconds
Started Dec 31 01:11:17 PM PST 23
Finished Dec 31 01:12:01 PM PST 23
Peak memory 218856 kb
Host smart-5ccdaa44-adf3-4609-b020-bda2afa58f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360053895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2360053895
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.62416413
Short name T250
Test name
Test status
Simulation time 1940313442 ps
CPU time 11.38 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:33 PM PST 23
Peak memory 231108 kb
Host smart-72b16be7-c13e-491e-a2ea-c90f119da263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62416413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.62416413
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_perf.3265917331
Short name T1585
Test name
Test status
Simulation time 32030051279 ps
CPU time 1947.38 seconds
Started Dec 31 01:11:44 PM PST 23
Finished Dec 31 01:44:13 PM PST 23
Peak memory 270248 kb
Host smart-ae0c02f5-b0c0-4163-83c0-c43d0aa1816d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265917331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_perf.3265917331
Directory /workspace/36.spi_device_perf/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2509982201
Short name T1184
Test name
Test status
Simulation time 1820106728 ps
CPU time 7.66 seconds
Started Dec 31 01:10:56 PM PST 23
Finished Dec 31 01:11:06 PM PST 23
Peak memory 236592 kb
Host smart-d22e41e8-fda3-4745-acf1-05068e40950a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2509982201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2509982201
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_rx_async_fifo_reset.4191069100
Short name T1671
Test name
Test status
Simulation time 131723820 ps
CPU time 0.89 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:11:20 PM PST 23
Peak memory 208424 kb
Host smart-0938904a-c056-4ec9-9464-3a1b2463ae40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191069100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_rx_async_fifo_reset.4191069100
Directory /workspace/36.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/36.spi_device_rx_timeout.2434711612
Short name T950
Test name
Test status
Simulation time 3270719231 ps
CPU time 6.6 seconds
Started Dec 31 01:12:06 PM PST 23
Finished Dec 31 01:12:15 PM PST 23
Peak memory 216804 kb
Host smart-8ef7f77a-adeb-4149-aede-11a668c70747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434711612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_rx_timeout.2434711612
Directory /workspace/36.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/36.spi_device_smoke.2447380640
Short name T1638
Test name
Test status
Simulation time 128297205 ps
CPU time 1.02 seconds
Started Dec 31 01:11:24 PM PST 23
Finished Dec 31 01:11:29 PM PST 23
Peak memory 208288 kb
Host smart-68e07f10-8400-48a6-8a7c-a1964be91469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447380640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_smoke.2447380640
Directory /workspace/36.spi_device_smoke/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2538600458
Short name T644
Test name
Test status
Simulation time 14384701248 ps
CPU time 24.19 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:11:41 PM PST 23
Peak memory 216848 kb
Host smart-175f64a7-2e56-41bf-b77e-3b02adee2993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538600458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2538600458
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2687240960
Short name T997
Test name
Test status
Simulation time 2737349199 ps
CPU time 8.71 seconds
Started Dec 31 01:11:57 PM PST 23
Finished Dec 31 01:12:07 PM PST 23
Peak memory 216868 kb
Host smart-c808afc2-fbcf-4008-85e1-7842b664ec78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687240960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2687240960
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.713841329
Short name T730
Test name
Test status
Simulation time 94758470 ps
CPU time 1.07 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:11:20 PM PST 23
Peak memory 208288 kb
Host smart-861bc70f-08b9-466f-855f-c47592a74ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713841329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.713841329
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1135456128
Short name T1488
Test name
Test status
Simulation time 261382285 ps
CPU time 0.98 seconds
Started Dec 31 01:11:19 PM PST 23
Finished Dec 31 01:11:24 PM PST 23
Peak memory 206916 kb
Host smart-82bdd616-960e-4afe-b42f-327e08f3ba32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135456128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1135456128
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_tx_async_fifo_reset.1045123098
Short name T1762
Test name
Test status
Simulation time 18093293 ps
CPU time 0.77 seconds
Started Dec 31 01:10:55 PM PST 23
Finished Dec 31 01:10:59 PM PST 23
Peak memory 208412 kb
Host smart-1c994c3e-de64-435d-b9ae-41f4ad9d85c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045123098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tx_async_fifo_reset.1045123098
Directory /workspace/36.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/36.spi_device_txrx.2473477013
Short name T898
Test name
Test status
Simulation time 45803079801 ps
CPU time 332.41 seconds
Started Dec 31 01:11:56 PM PST 23
Finished Dec 31 01:17:30 PM PST 23
Peak memory 282516 kb
Host smart-dfcf0da6-aee3-49da-b27b-c79e26ac1730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473477013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_txrx.2473477013
Directory /workspace/36.spi_device_txrx/latest

Test location /workspace/coverage/default/36.spi_device_upload.1733550064
Short name T838
Test name
Test status
Simulation time 581163753 ps
CPU time 12.3 seconds
Started Dec 31 01:11:13 PM PST 23
Finished Dec 31 01:11:27 PM PST 23
Peak memory 249044 kb
Host smart-1aa14781-7972-40f5-89b3-b773685a61f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733550064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1733550064
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_abort.396965898
Short name T1499
Test name
Test status
Simulation time 50813018 ps
CPU time 0.74 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:11:19 PM PST 23
Peak memory 206628 kb
Host smart-ea9db739-9cb9-48e8-8704-8556799a3f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396965898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_abort.396965898
Directory /workspace/37.spi_device_abort/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2116740806
Short name T580
Test name
Test status
Simulation time 15488479 ps
CPU time 0.71 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:11:18 PM PST 23
Peak memory 206516 kb
Host smart-e7fe3aea-f004-4179-abef-a81a392d6c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116740806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2116740806
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_bit_transfer.4107014502
Short name T679
Test name
Test status
Simulation time 464739287 ps
CPU time 1.92 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:11:19 PM PST 23
Peak memory 216856 kb
Host smart-3df73d5d-2f53-4e80-b36e-0705a3c98de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107014502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_bit_transfer.4107014502
Directory /workspace/37.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/37.spi_device_byte_transfer.3513600949
Short name T1191
Test name
Test status
Simulation time 2025580621 ps
CPU time 3.5 seconds
Started Dec 31 01:11:20 PM PST 23
Finished Dec 31 01:11:28 PM PST 23
Peak memory 216804 kb
Host smart-1f031b9e-52ae-4f4d-be1e-8df853af3f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513600949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_byte_transfer.3513600949
Directory /workspace/37.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1587853443
Short name T1122
Test name
Test status
Simulation time 2184642627 ps
CPU time 4 seconds
Started Dec 31 01:11:20 PM PST 23
Finished Dec 31 01:11:29 PM PST 23
Peak memory 219568 kb
Host smart-e01e7d79-bd0d-4aa6-a11f-0da5b706f0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587853443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1587853443
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3129374426
Short name T1524
Test name
Test status
Simulation time 119665430 ps
CPU time 0.78 seconds
Started Dec 31 01:11:17 PM PST 23
Finished Dec 31 01:11:22 PM PST 23
Peak memory 207540 kb
Host smart-d574fd85-d591-4c2b-a424-7c7c19b518ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129374426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3129374426
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_dummy_item_extra_dly.3932097254
Short name T1639
Test name
Test status
Simulation time 72921159447 ps
CPU time 509.43 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:19:46 PM PST 23
Peak memory 296008 kb
Host smart-05880e5c-d2cf-46a6-b8fa-a26d1b7d1be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932097254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_dummy_item_extra_dly.3932097254
Directory /workspace/37.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/37.spi_device_extreme_fifo_size.2892705775
Short name T951
Test name
Test status
Simulation time 77813156090 ps
CPU time 521.98 seconds
Started Dec 31 01:11:17 PM PST 23
Finished Dec 31 01:20:02 PM PST 23
Peak memory 218952 kb
Host smart-aac895a1-ee50-41c4-adc9-37bb4d4e181a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892705775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_extreme_fifo_size.2892705775
Directory /workspace/37.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/37.spi_device_fifo_full.1227384285
Short name T1397
Test name
Test status
Simulation time 97690812953 ps
CPU time 297.34 seconds
Started Dec 31 01:11:17 PM PST 23
Finished Dec 31 01:16:18 PM PST 23
Peak memory 283720 kb
Host smart-2286f679-530e-4bf8-974f-7ebdca90e5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227384285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_fifo_full.1227384285
Directory /workspace/37.spi_device_fifo_full/latest

Test location /workspace/coverage/default/37.spi_device_fifo_underflow_overflow.3346264367
Short name T86
Test name
Test status
Simulation time 177468920116 ps
CPU time 2972.22 seconds
Started Dec 31 01:11:19 PM PST 23
Finished Dec 31 02:00:56 PM PST 23
Peak memory 981596 kb
Host smart-30709287-5de0-4ffb-b7c8-e65c85528c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346264367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_fifo_underflow_overf
low.3346264367
Directory /workspace/37.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.704253521
Short name T297
Test name
Test status
Simulation time 94704558185 ps
CPU time 450.04 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:18:52 PM PST 23
Peak memory 257816 kb
Host smart-e96140ee-a3bf-4119-9900-a18c923edb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704253521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.704253521
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.4173116287
Short name T303
Test name
Test status
Simulation time 65378414676 ps
CPU time 305.13 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:16:28 PM PST 23
Peak memory 254496 kb
Host smart-a38ebb65-04dc-4e06-aecd-f0727972fe21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173116287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.4173116287
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.452505822
Short name T1373
Test name
Test status
Simulation time 130810060045 ps
CPU time 362.17 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:17:19 PM PST 23
Peak memory 257928 kb
Host smart-89e3ae31-a5a6-4a89-ac86-dda7271bba47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452505822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.452505822
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3828345243
Short name T1300
Test name
Test status
Simulation time 8390808106 ps
CPU time 36.45 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:11:53 PM PST 23
Peak memory 265968 kb
Host smart-dfec62c0-54f5-4342-8083-c4cc18cec088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828345243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3828345243
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.461013625
Short name T222
Test name
Test status
Simulation time 11223206553 ps
CPU time 10.3 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:33 PM PST 23
Peak memory 237636 kb
Host smart-6ff96768-8a83-4716-b691-e6f7884b075d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461013625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.461013625
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_intr.789394785
Short name T765
Test name
Test status
Simulation time 8382358619 ps
CPU time 31.81 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:53 PM PST 23
Peak memory 225260 kb
Host smart-f7905cc8-140f-4671-a361-710ec73f588d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789394785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intr.789394785
Directory /workspace/37.spi_device_intr/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.4045773282
Short name T1569
Test name
Test status
Simulation time 8284825978 ps
CPU time 10.68 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:11:27 PM PST 23
Peak memory 234832 kb
Host smart-6fc6fd12-d73c-45d4-95c8-9c27a2bb1f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045773282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.4045773282
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1842218475
Short name T211
Test name
Test status
Simulation time 332887665 ps
CPU time 6.93 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:11:23 PM PST 23
Peak memory 249584 kb
Host smart-254e2bb6-a551-4a17-9490-e63645f5a2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842218475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1842218475
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2380064576
Short name T783
Test name
Test status
Simulation time 11554240674 ps
CPU time 22.16 seconds
Started Dec 31 01:11:19 PM PST 23
Finished Dec 31 01:11:45 PM PST 23
Peak memory 233884 kb
Host smart-cc7bdf59-a8ee-4672-ae91-9421fb81464b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380064576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2380064576
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_perf.3125172211
Short name T257
Test name
Test status
Simulation time 69095428118 ps
CPU time 1250.24 seconds
Started Dec 31 01:11:17 PM PST 23
Finished Dec 31 01:32:10 PM PST 23
Peak memory 273020 kb
Host smart-f3984eb8-7c34-4631-af90-24396402b38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125172211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_perf.3125172211
Directory /workspace/37.spi_device_perf/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3578359275
Short name T157
Test name
Test status
Simulation time 98088280 ps
CPU time 4.18 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:26 PM PST 23
Peak memory 234516 kb
Host smart-2f6ee063-72ba-4273-8ee0-ec6f0a4917c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3578359275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3578359275
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_rx_async_fifo_reset.1318114758
Short name T1082
Test name
Test status
Simulation time 22256797 ps
CPU time 0.87 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:11:17 PM PST 23
Peak memory 208520 kb
Host smart-dd207614-db07-417d-8fe9-c47963cb4393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318114758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_rx_async_fifo_reset.1318114758
Directory /workspace/37.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/37.spi_device_rx_timeout.3508906656
Short name T1141
Test name
Test status
Simulation time 586842570 ps
CPU time 5.93 seconds
Started Dec 31 01:11:20 PM PST 23
Finished Dec 31 01:11:31 PM PST 23
Peak memory 216816 kb
Host smart-c774f6df-d3fa-4c45-a70e-8f9ed98ddb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508906656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_rx_timeout.3508906656
Directory /workspace/37.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/37.spi_device_smoke.2578474655
Short name T1711
Test name
Test status
Simulation time 129934201 ps
CPU time 1.08 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:24 PM PST 23
Peak memory 208312 kb
Host smart-499614fb-b13c-459b-a50f-16e720c7b953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578474655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_smoke.2578474655
Directory /workspace/37.spi_device_smoke/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2644378212
Short name T1197
Test name
Test status
Simulation time 4790460293 ps
CPU time 44.36 seconds
Started Dec 31 01:11:20 PM PST 23
Finished Dec 31 01:12:09 PM PST 23
Peak memory 217088 kb
Host smart-738d551a-4124-4a05-bb25-e14aded4d7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644378212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2644378212
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2912948988
Short name T493
Test name
Test status
Simulation time 1490199694 ps
CPU time 7.83 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:11:25 PM PST 23
Peak memory 216828 kb
Host smart-73087cab-21af-45dd-8794-a108c3b7dbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912948988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2912948988
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.611996993
Short name T333
Test name
Test status
Simulation time 166028685 ps
CPU time 1.67 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:24 PM PST 23
Peak memory 216796 kb
Host smart-a774f0f9-470c-4e85-a1fa-203bb38ba1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611996993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.611996993
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.4213818216
Short name T1316
Test name
Test status
Simulation time 70659172 ps
CPU time 0.81 seconds
Started Dec 31 01:11:34 PM PST 23
Finished Dec 31 01:11:35 PM PST 23
Peak memory 206920 kb
Host smart-57a768ca-2a14-4bf0-b4f7-15ad619205ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213818216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.4213818216
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_tx_async_fifo_reset.1766195795
Short name T849
Test name
Test status
Simulation time 16428133 ps
CPU time 0.78 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:11:19 PM PST 23
Peak memory 208476 kb
Host smart-76c907bb-917c-49f3-a1b7-f0a0ec0810f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766195795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tx_async_fifo_reset.1766195795
Directory /workspace/37.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/37.spi_device_txrx.2787536600
Short name T41
Test name
Test status
Simulation time 86769201207 ps
CPU time 485.73 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:19:23 PM PST 23
Peak memory 249772 kb
Host smart-0b2f4a51-8532-4a84-851d-81d554882b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787536600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_txrx.2787536600
Directory /workspace/37.spi_device_txrx/latest

Test location /workspace/coverage/default/37.spi_device_upload.451693903
Short name T1140
Test name
Test status
Simulation time 8003038025 ps
CPU time 25.36 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:11:43 PM PST 23
Peak memory 219732 kb
Host smart-7be7c7d7-a152-4d98-bb77-cbef5d0d1ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451693903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.451693903
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_abort.4040039419
Short name T927
Test name
Test status
Simulation time 14537943 ps
CPU time 0.78 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:11:19 PM PST 23
Peak memory 206600 kb
Host smart-0918b8e8-7d6e-40e3-b29f-3d2fb368222f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040039419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_abort.4040039419
Directory /workspace/38.spi_device_abort/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.221583096
Short name T1729
Test name
Test status
Simulation time 18713386 ps
CPU time 0.75 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:23 PM PST 23
Peak memory 206528 kb
Host smart-696bf643-c027-49c8-abb0-e0eb17e2904e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221583096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.221583096
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_bit_transfer.2891863940
Short name T769
Test name
Test status
Simulation time 926986317 ps
CPU time 2.56 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:26 PM PST 23
Peak memory 216716 kb
Host smart-e389b2ef-e366-4d9f-9f58-770c0d38f4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891863940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_bit_transfer.2891863940
Directory /workspace/38.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/38.spi_device_byte_transfer.643551458
Short name T1272
Test name
Test status
Simulation time 236174204 ps
CPU time 2.28 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:25 PM PST 23
Peak memory 216856 kb
Host smart-048985d2-a315-4f7a-9074-cf0f7fb63415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643551458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_byte_transfer.643551458
Directory /workspace/38.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3337322881
Short name T271
Test name
Test status
Simulation time 2844544112 ps
CPU time 5.83 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:28 PM PST 23
Peak memory 241492 kb
Host smart-bd721099-2c5c-4b06-84d8-a8624d6f30d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337322881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3337322881
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2714159007
Short name T601
Test name
Test status
Simulation time 130984658 ps
CPU time 0.75 seconds
Started Dec 31 01:11:17 PM PST 23
Finished Dec 31 01:11:21 PM PST 23
Peak memory 207628 kb
Host smart-b5861271-8f33-48ae-8803-af20c9070f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714159007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2714159007
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_dummy_item_extra_dly.1293304224
Short name T648
Test name
Test status
Simulation time 82210657342 ps
CPU time 220.38 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:15:02 PM PST 23
Peak memory 249780 kb
Host smart-81afbe1b-aad6-4eb7-8f74-7d7191102fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293304224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_dummy_item_extra_dly.1293304224
Directory /workspace/38.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/38.spi_device_extreme_fifo_size.4126954675
Short name T1063
Test name
Test status
Simulation time 4528839902 ps
CPU time 35.73 seconds
Started Dec 31 01:11:19 PM PST 23
Finished Dec 31 01:12:00 PM PST 23
Peak memory 235448 kb
Host smart-3198a9dd-b425-4a7b-b8bf-a105c39eb944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126954675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_extreme_fifo_size.4126954675
Directory /workspace/38.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/38.spi_device_fifo_full.1360277675
Short name T744
Test name
Test status
Simulation time 38092403572 ps
CPU time 1095.88 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:29:35 PM PST 23
Peak memory 264448 kb
Host smart-5c85015d-6556-45ea-a7b4-4c97a5cab064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360277675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_fifo_full.1360277675
Directory /workspace/38.spi_device_fifo_full/latest

Test location /workspace/coverage/default/38.spi_device_fifo_underflow_overflow.2799325080
Short name T693
Test name
Test status
Simulation time 76409610186 ps
CPU time 398.89 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:17:56 PM PST 23
Peak memory 379704 kb
Host smart-dbc1653e-e874-4846-8bc4-4684ac78df3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799325080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_fifo_underflow_overf
low.2799325080
Directory /workspace/38.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2402892294
Short name T193
Test name
Test status
Simulation time 39566997351 ps
CPU time 311.12 seconds
Started Dec 31 01:11:20 PM PST 23
Finished Dec 31 01:16:36 PM PST 23
Peak memory 251988 kb
Host smart-5ee1d94e-bf9a-4f6b-962e-44ffa33ccd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402892294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2402892294
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3377367947
Short name T248
Test name
Test status
Simulation time 174748010131 ps
CPU time 317.71 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:16:40 PM PST 23
Peak memory 266248 kb
Host smart-1c35d8b2-f3c7-46c0-9b55-055aced9a3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377367947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3377367947
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.4174268392
Short name T82
Test name
Test status
Simulation time 1764251013 ps
CPU time 14.04 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:11:33 PM PST 23
Peak memory 238792 kb
Host smart-2f51e415-c1c0-479b-b418-4512668a6084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174268392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4174268392
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2380519243
Short name T233
Test name
Test status
Simulation time 161533728 ps
CPU time 5.4 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:28 PM PST 23
Peak memory 240480 kb
Host smart-6d3f9960-4dc9-40a9-905d-3c61b1da6aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380519243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2380519243
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_intr.139980463
Short name T1626
Test name
Test status
Simulation time 31435646669 ps
CPU time 34.5 seconds
Started Dec 31 01:11:14 PM PST 23
Finished Dec 31 01:11:50 PM PST 23
Peak memory 241084 kb
Host smart-1bf8f7dd-e092-49d7-8fb9-0aadf1fd842c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139980463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intr.139980463
Directory /workspace/38.spi_device_intr/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.528811322
Short name T218
Test name
Test status
Simulation time 1244711219 ps
CPU time 10.32 seconds
Started Dec 31 01:11:21 PM PST 23
Finished Dec 31 01:11:36 PM PST 23
Peak memory 247572 kb
Host smart-129f2d4a-bb6e-410f-9eff-63d49e28bc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528811322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.528811322
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3549193204
Short name T285
Test name
Test status
Simulation time 11176949011 ps
CPU time 30.16 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:11:48 PM PST 23
Peak memory 233316 kb
Host smart-db86adde-1afc-4424-bcba-15095549b478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549193204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3549193204
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3794767838
Short name T566
Test name
Test status
Simulation time 1002669960 ps
CPU time 3.96 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:27 PM PST 23
Peak memory 239284 kb
Host smart-d6812850-c88b-4b86-a0c1-3ef674e08fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794767838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3794767838
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_perf.2496902094
Short name T1252
Test name
Test status
Simulation time 41996253881 ps
CPU time 716.3 seconds
Started Dec 31 01:11:19 PM PST 23
Finished Dec 31 01:23:20 PM PST 23
Peak memory 264188 kb
Host smart-af28e7e2-749d-4e43-b10b-011572967261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496902094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_perf.2496902094
Directory /workspace/38.spi_device_perf/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1841927967
Short name T1472
Test name
Test status
Simulation time 378367055 ps
CPU time 4.43 seconds
Started Dec 31 01:11:17 PM PST 23
Finished Dec 31 01:11:24 PM PST 23
Peak memory 237656 kb
Host smart-4a27647c-5f7f-4406-8acb-4c510d80af51
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1841927967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1841927967
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_rx_async_fifo_reset.3743694257
Short name T1746
Test name
Test status
Simulation time 24607982 ps
CPU time 0.89 seconds
Started Dec 31 01:11:14 PM PST 23
Finished Dec 31 01:11:17 PM PST 23
Peak memory 208432 kb
Host smart-2d976ffc-6b08-4892-abc5-c4efb9f329b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743694257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_rx_async_fifo_reset.3743694257
Directory /workspace/38.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/38.spi_device_rx_timeout.200614023
Short name T1016
Test name
Test status
Simulation time 1231686073 ps
CPU time 5.12 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:11:21 PM PST 23
Peak memory 216800 kb
Host smart-22d5df50-be35-4712-aada-b9d3ce67d04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200614023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_rx_timeout.200614023
Directory /workspace/38.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/38.spi_device_smoke.2638624620
Short name T680
Test name
Test status
Simulation time 97480661 ps
CPU time 1.04 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:11:19 PM PST 23
Peak memory 216492 kb
Host smart-35b48b58-b1c3-4b30-b6a9-a55e1e6a0cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638624620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_smoke.2638624620
Directory /workspace/38.spi_device_smoke/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1409990800
Short name T1422
Test name
Test status
Simulation time 7564974934 ps
CPU time 13.58 seconds
Started Dec 31 01:11:14 PM PST 23
Finished Dec 31 01:11:29 PM PST 23
Peak memory 217000 kb
Host smart-aba89efa-a306-4c2c-92a3-45cefd91842d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409990800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1409990800
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.352216596
Short name T1630
Test name
Test status
Simulation time 1932909763 ps
CPU time 1.8 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:11:18 PM PST 23
Peak memory 208424 kb
Host smart-c6349206-6252-4b74-a44e-bb4da7aa9ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352216596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.352216596
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.4016828853
Short name T1433
Test name
Test status
Simulation time 70068853 ps
CPU time 1.49 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:11:20 PM PST 23
Peak memory 216864 kb
Host smart-d58d7638-953d-41f3-bb37-da9455ee624b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016828853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4016828853
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.918669110
Short name T1697
Test name
Test status
Simulation time 153846483 ps
CPU time 0.97 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:11:19 PM PST 23
Peak memory 208260 kb
Host smart-36074c49-057f-46ed-8d7c-923dfb45715c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918669110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.918669110
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_tx_async_fifo_reset.98591305
Short name T49
Test name
Test status
Simulation time 14729742 ps
CPU time 0.78 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:23 PM PST 23
Peak memory 208388 kb
Host smart-b9a6703b-1cc6-4059-aaae-8118cbc81a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98591305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tx_async_fifo_reset.98591305
Directory /workspace/38.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/38.spi_device_txrx.376013237
Short name T981
Test name
Test status
Simulation time 87985388161 ps
CPU time 190.08 seconds
Started Dec 31 01:11:19 PM PST 23
Finished Dec 31 01:14:33 PM PST 23
Peak memory 256652 kb
Host smart-4bbe063b-403b-461f-9c0e-32b80b2a822e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376013237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_txrx.376013237
Directory /workspace/38.spi_device_txrx/latest

Test location /workspace/coverage/default/38.spi_device_upload.3636351077
Short name T1636
Test name
Test status
Simulation time 1076897522 ps
CPU time 9.28 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:11:28 PM PST 23
Peak memory 245600 kb
Host smart-854d0a24-34cc-459d-8478-1d2c1defdd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636351077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3636351077
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_abort.4109886325
Short name T63
Test name
Test status
Simulation time 17726037 ps
CPU time 0.77 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:23 PM PST 23
Peak memory 206648 kb
Host smart-c7d89cab-4bb6-4bed-9c49-21e07c65ffec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109886325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_abort.4109886325
Directory /workspace/39.spi_device_abort/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1884646405
Short name T454
Test name
Test status
Simulation time 13642553 ps
CPU time 0.77 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:26 PM PST 23
Peak memory 206532 kb
Host smart-1ea576a7-8d49-4acf-bc15-ce8ca093858b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884646405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1884646405
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_bit_transfer.2271379930
Short name T1096
Test name
Test status
Simulation time 1544383915 ps
CPU time 2.23 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:25 PM PST 23
Peak memory 216828 kb
Host smart-17b97ffe-7a60-4e72-87f0-8e04df03a4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271379930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_bit_transfer.2271379930
Directory /workspace/39.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/39.spi_device_byte_transfer.546132472
Short name T1182
Test name
Test status
Simulation time 97271328 ps
CPU time 2.84 seconds
Started Dec 31 01:11:19 PM PST 23
Finished Dec 31 01:11:26 PM PST 23
Peak memory 216816 kb
Host smart-3754d718-c4eb-4d5d-979c-0764421e7a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546132472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_byte_transfer.546132472
Directory /workspace/39.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.376774088
Short name T278
Test name
Test status
Simulation time 117826712 ps
CPU time 3.93 seconds
Started Dec 31 01:11:57 PM PST 23
Finished Dec 31 01:12:02 PM PST 23
Peak memory 220628 kb
Host smart-9b864f70-fea0-4abc-a12e-d40aaa231c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376774088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.376774088
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3078690097
Short name T909
Test name
Test status
Simulation time 22222938 ps
CPU time 0.78 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:23 PM PST 23
Peak memory 207628 kb
Host smart-a1bd97ed-cb78-434a-a5db-b5d7b7dd2b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078690097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3078690097
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_dummy_item_extra_dly.3581710718
Short name T669
Test name
Test status
Simulation time 50999455597 ps
CPU time 901.34 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:26:21 PM PST 23
Peak memory 303520 kb
Host smart-6ffa1de4-63a3-41fb-bd76-7dd46817eebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581710718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_dummy_item_extra_dly.3581710718
Directory /workspace/39.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/39.spi_device_extreme_fifo_size.209081435
Short name T1218
Test name
Test status
Simulation time 6710334686 ps
CPU time 63.13 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 224988 kb
Host smart-3224578e-8e39-444b-8ede-78d2c6979499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209081435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_extreme_fifo_size.209081435
Directory /workspace/39.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/39.spi_device_fifo_full.1904214881
Short name T552
Test name
Test status
Simulation time 112518663038 ps
CPU time 388.02 seconds
Started Dec 31 01:11:19 PM PST 23
Finished Dec 31 01:17:51 PM PST 23
Peak memory 251832 kb
Host smart-ec20a8dd-e7ce-4d80-912d-6213b7de49fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904214881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_fifo_full.1904214881
Directory /workspace/39.spi_device_fifo_full/latest

Test location /workspace/coverage/default/39.spi_device_fifo_underflow_overflow.614963166
Short name T42
Test name
Test status
Simulation time 282670820392 ps
CPU time 505.37 seconds
Started Dec 31 01:11:19 PM PST 23
Finished Dec 31 01:19:49 PM PST 23
Peak memory 360400 kb
Host smart-767846f6-9ce9-4c8d-88e3-4b2455bf760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614963166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_fifo_underflow_overfl
ow.614963166
Directory /workspace/39.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.4253881410
Short name T282
Test name
Test status
Simulation time 7802164038 ps
CPU time 76.96 seconds
Started Dec 31 01:11:22 PM PST 23
Finished Dec 31 01:12:44 PM PST 23
Peak memory 252556 kb
Host smart-9f57ad25-5276-4183-ac00-cef3571aee3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253881410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.4253881410
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2927598121
Short name T736
Test name
Test status
Simulation time 5337611850 ps
CPU time 31.23 seconds
Started Dec 31 01:11:38 PM PST 23
Finished Dec 31 01:12:10 PM PST 23
Peak memory 235900 kb
Host smart-237ddb48-8daf-4cfc-b205-2994934e3a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927598121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2927598121
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3934287660
Short name T15
Test name
Test status
Simulation time 6652907373 ps
CPU time 49.62 seconds
Started Dec 31 01:11:42 PM PST 23
Finished Dec 31 01:12:33 PM PST 23
Peak memory 241520 kb
Host smart-bf52ac77-d929-499b-849b-ed6f601a8dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934287660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3934287660
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.4240365115
Short name T1614
Test name
Test status
Simulation time 2485197811 ps
CPU time 19.92 seconds
Started Dec 31 01:11:25 PM PST 23
Finished Dec 31 01:11:48 PM PST 23
Peak memory 251856 kb
Host smart-4f884b4d-7658-4499-838f-0c67b5f6cef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240365115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.4240365115
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.662780137
Short name T277
Test name
Test status
Simulation time 3274588813 ps
CPU time 6.99 seconds
Started Dec 31 01:11:23 PM PST 23
Finished Dec 31 01:11:34 PM PST 23
Peak memory 225100 kb
Host smart-36da47a5-0170-4f49-99b9-1922ecafafbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662780137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.662780137
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_intr.4180360426
Short name T963
Test name
Test status
Simulation time 32253201329 ps
CPU time 36.84 seconds
Started Dec 31 01:11:17 PM PST 23
Finished Dec 31 01:11:58 PM PST 23
Peak memory 225204 kb
Host smart-f4d1ed8f-1696-4f70-9582-e632d801dc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180360426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intr.4180360426
Directory /workspace/39.spi_device_intr/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.713419080
Short name T1098
Test name
Test status
Simulation time 9080025929 ps
CPU time 18.46 seconds
Started Dec 31 01:11:38 PM PST 23
Finished Dec 31 01:11:57 PM PST 23
Peak memory 249784 kb
Host smart-bd758a11-d6dd-42ef-b712-957bbe2e5a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713419080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.713419080
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.787818801
Short name T920
Test name
Test status
Simulation time 5539760826 ps
CPU time 11.55 seconds
Started Dec 31 01:11:24 PM PST 23
Finished Dec 31 01:11:39 PM PST 23
Peak memory 239496 kb
Host smart-1e2d8321-aad0-443c-a2cb-fe6c7847e2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787818801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.787818801
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1888197129
Short name T1310
Test name
Test status
Simulation time 58835052875 ps
CPU time 41.66 seconds
Started Dec 31 01:11:21 PM PST 23
Finished Dec 31 01:12:08 PM PST 23
Peak memory 255148 kb
Host smart-d067affe-760a-4a11-9674-749ff491f37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888197129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1888197129
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_perf.3626520126
Short name T1575
Test name
Test status
Simulation time 113219976885 ps
CPU time 614.04 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:21:31 PM PST 23
Peak memory 262496 kb
Host smart-53b7633a-49e0-47c9-a08a-72e09b441898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626520126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_perf.3626520126
Directory /workspace/39.spi_device_perf/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2952711443
Short name T1171
Test name
Test status
Simulation time 1308162355 ps
CPU time 3.89 seconds
Started Dec 31 01:11:38 PM PST 23
Finished Dec 31 01:11:42 PM PST 23
Peak memory 218500 kb
Host smart-d09660cb-11b3-4386-a004-2b24ecbab613
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2952711443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2952711443
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_rx_async_fifo_reset.429256349
Short name T119
Test name
Test status
Simulation time 104446208 ps
CPU time 0.86 seconds
Started Dec 31 01:11:24 PM PST 23
Finished Dec 31 01:11:28 PM PST 23
Peak memory 208480 kb
Host smart-73fc714f-9cc3-4da2-8e05-da03f66941c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429256349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_rx_async_fifo_reset.429256349
Directory /workspace/39.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/39.spi_device_rx_timeout.825354859
Short name T524
Test name
Test status
Simulation time 464999271 ps
CPU time 5.5 seconds
Started Dec 31 01:11:20 PM PST 23
Finished Dec 31 01:11:30 PM PST 23
Peak memory 216752 kb
Host smart-7119c70f-99af-476c-af31-49a3476d0d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825354859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_rx_timeout.825354859
Directory /workspace/39.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/39.spi_device_smoke.3483382055
Short name T1146
Test name
Test status
Simulation time 80244439 ps
CPU time 1.01 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:24 PM PST 23
Peak memory 208052 kb
Host smart-f86ceaac-f963-48b0-989e-8fccfd61000d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483382055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_smoke.3483382055
Directory /workspace/39.spi_device_smoke/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3837637980
Short name T1400
Test name
Test status
Simulation time 11955610274 ps
CPU time 166.21 seconds
Started Dec 31 01:11:20 PM PST 23
Finished Dec 31 01:14:12 PM PST 23
Peak memory 216776 kb
Host smart-fe1a53ed-1188-4de6-a3a5-17b68361bd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837637980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3837637980
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3622496350
Short name T703
Test name
Test status
Simulation time 1414136595 ps
CPU time 10.66 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:34 PM PST 23
Peak memory 217908 kb
Host smart-36dcbdc3-5b3c-499e-b1fd-a5b4da170721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622496350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3622496350
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3173927809
Short name T1576
Test name
Test status
Simulation time 43719973 ps
CPU time 1.42 seconds
Started Dec 31 01:11:19 PM PST 23
Finished Dec 31 01:11:25 PM PST 23
Peak memory 216724 kb
Host smart-7317c7bd-2b81-4450-8f71-5bdc23088a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173927809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3173927809
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.211665832
Short name T1012
Test name
Test status
Simulation time 72517588 ps
CPU time 0.91 seconds
Started Dec 31 01:11:20 PM PST 23
Finished Dec 31 01:11:25 PM PST 23
Peak memory 206924 kb
Host smart-a8776f80-e4d2-4cc2-8377-55f8b67e6c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211665832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.211665832
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_tx_async_fifo_reset.3417071474
Short name T1598
Test name
Test status
Simulation time 24297332 ps
CPU time 0.79 seconds
Started Dec 31 01:11:20 PM PST 23
Finished Dec 31 01:11:26 PM PST 23
Peak memory 208416 kb
Host smart-857a15b7-4aa3-4d19-8aae-4a73c72bcc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417071474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tx_async_fifo_reset.3417071474
Directory /workspace/39.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/39.spi_device_txrx.1801948998
Short name T1170
Test name
Test status
Simulation time 55785854024 ps
CPU time 1323.17 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:33:22 PM PST 23
Peak memory 266556 kb
Host smart-46a1bee7-af9b-4c17-9fe1-d597fa9f7539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801948998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_txrx.1801948998
Directory /workspace/39.spi_device_txrx/latest

Test location /workspace/coverage/default/39.spi_device_upload.1361747429
Short name T268
Test name
Test status
Simulation time 995335159 ps
CPU time 9.99 seconds
Started Dec 31 01:11:22 PM PST 23
Finished Dec 31 01:11:37 PM PST 23
Peak memory 234684 kb
Host smart-a912a895-bc71-4009-af2a-131001fcc214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361747429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1361747429
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_abort.3934768440
Short name T1090
Test name
Test status
Simulation time 27651685 ps
CPU time 0.74 seconds
Started Dec 31 01:08:04 PM PST 23
Finished Dec 31 01:08:06 PM PST 23
Peak memory 206600 kb
Host smart-f6f151b1-b19d-4d4b-9419-19539cf35ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934768440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_abort.3934768440
Directory /workspace/4.spi_device_abort/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3102776213
Short name T1386
Test name
Test status
Simulation time 61176438 ps
CPU time 0.68 seconds
Started Dec 31 01:08:04 PM PST 23
Finished Dec 31 01:08:07 PM PST 23
Peak memory 206448 kb
Host smart-1429ee3d-a56a-40f8-a1e3-73744609075b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102776213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
102776213
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_bit_transfer.1847254827
Short name T860
Test name
Test status
Simulation time 95447087 ps
CPU time 2.13 seconds
Started Dec 31 01:08:14 PM PST 23
Finished Dec 31 01:08:17 PM PST 23
Peak memory 216552 kb
Host smart-fabb0acd-0286-4388-bacf-7147521be43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847254827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_bit_transfer.1847254827
Directory /workspace/4.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/4.spi_device_byte_transfer.2907275923
Short name T1702
Test name
Test status
Simulation time 301738703 ps
CPU time 3.48 seconds
Started Dec 31 01:08:56 PM PST 23
Finished Dec 31 01:09:07 PM PST 23
Peak memory 216780 kb
Host smart-9ee33d1c-da66-4858-a514-2dd5e0e8d457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907275923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_byte_transfer.2907275923
Directory /workspace/4.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2580794438
Short name T1542
Test name
Test status
Simulation time 10827933694 ps
CPU time 7.05 seconds
Started Dec 31 01:08:05 PM PST 23
Finished Dec 31 01:08:15 PM PST 23
Peak memory 220780 kb
Host smart-3dde8c03-a009-44ad-8a45-c17ccd77d172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580794438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2580794438
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.583251080
Short name T103
Test name
Test status
Simulation time 13353900 ps
CPU time 0.75 seconds
Started Dec 31 01:08:58 PM PST 23
Finished Dec 31 01:09:06 PM PST 23
Peak memory 206240 kb
Host smart-40897e69-da77-485f-a874-204a38988758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583251080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.583251080
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_dummy_item_extra_dly.1573315412
Short name T1551
Test name
Test status
Simulation time 52766333981 ps
CPU time 234.35 seconds
Started Dec 31 01:09:12 PM PST 23
Finished Dec 31 01:13:09 PM PST 23
Peak memory 233240 kb
Host smart-227e6772-44bf-4616-a0cc-09e7eaec923a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573315412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_dummy_item_extra_dly.1573315412
Directory /workspace/4.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/4.spi_device_extreme_fifo_size.3570952584
Short name T1555
Test name
Test status
Simulation time 157550545609 ps
CPU time 3385.02 seconds
Started Dec 31 01:08:54 PM PST 23
Finished Dec 31 02:05:25 PM PST 23
Peak memory 225176 kb
Host smart-a2c2e4d7-cc0b-441c-9384-c4bea54f4003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570952584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_extreme_fifo_size.3570952584
Directory /workspace/4.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/4.spi_device_fifo_full.3705419510
Short name T1599
Test name
Test status
Simulation time 41296807701 ps
CPU time 686.28 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:20:25 PM PST 23
Peak memory 270764 kb
Host smart-48f6852a-dea4-4a0a-93ea-b626e9e2d98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705419510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_fifo_full.3705419510
Directory /workspace/4.spi_device_fifo_full/latest

Test location /workspace/coverage/default/4.spi_device_fifo_underflow_overflow.2342592945
Short name T937
Test name
Test status
Simulation time 54560051581 ps
CPU time 311.3 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:14:06 PM PST 23
Peak memory 342108 kb
Host smart-94dc7d1c-2a93-4205-aa6c-1fb5549480b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342592945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_fifo_underflow_overfl
ow.2342592945
Directory /workspace/4.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1335961224
Short name T1763
Test name
Test status
Simulation time 2272031417 ps
CPU time 38.45 seconds
Started Dec 31 01:07:58 PM PST 23
Finished Dec 31 01:08:38 PM PST 23
Peak memory 253672 kb
Host smart-9f25de17-4e9a-461a-84dc-84943a6014b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335961224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1335961224
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2339976937
Short name T1258
Test name
Test status
Simulation time 23968058187 ps
CPU time 130.4 seconds
Started Dec 31 01:07:59 PM PST 23
Finished Dec 31 01:10:10 PM PST 23
Peak memory 265452 kb
Host smart-b00a9b63-5475-42ca-a006-74c65f17b556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339976937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2339976937
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2481340564
Short name T323
Test name
Test status
Simulation time 8426033558 ps
CPU time 27.57 seconds
Started Dec 31 01:07:59 PM PST 23
Finished Dec 31 01:08:28 PM PST 23
Peak memory 252372 kb
Host smart-600325fc-cd66-454f-b233-47d836c79949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481340564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2481340564
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1703462419
Short name T1382
Test name
Test status
Simulation time 7279667351 ps
CPU time 10.92 seconds
Started Dec 31 01:08:02 PM PST 23
Finished Dec 31 01:08:14 PM PST 23
Peak memory 239384 kb
Host smart-bc0ffcf1-42fb-4782-8b5f-51fc84097a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703462419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1703462419
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_intr.2120956902
Short name T1067
Test name
Test status
Simulation time 3598253417 ps
CPU time 28.76 seconds
Started Dec 31 01:08:59 PM PST 23
Finished Dec 31 01:09:36 PM PST 23
Peak memory 239452 kb
Host smart-e2791582-bedf-48b1-9526-3d75a08722ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120956902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intr.2120956902
Directory /workspace/4.spi_device_intr/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.810094524
Short name T1414
Test name
Test status
Simulation time 554885117 ps
CPU time 10.95 seconds
Started Dec 31 01:08:24 PM PST 23
Finished Dec 31 01:08:36 PM PST 23
Peak memory 248904 kb
Host smart-c49afb1e-d2a0-46d1-b9ea-9c333b1e9d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810094524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.810094524
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3075570259
Short name T1512
Test name
Test status
Simulation time 111002198 ps
CPU time 1.09 seconds
Started Dec 31 01:08:58 PM PST 23
Finished Dec 31 01:09:07 PM PST 23
Peak memory 218828 kb
Host smart-50e1ed5b-20e2-4141-bdba-b1cf14c916ac
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075570259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3075570259
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2729316221
Short name T243
Test name
Test status
Simulation time 13018317321 ps
CPU time 13.91 seconds
Started Dec 31 01:08:12 PM PST 23
Finished Dec 31 01:08:27 PM PST 23
Peak memory 225152 kb
Host smart-c5adf78a-9d87-485e-a8a8-63f27920194a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729316221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2729316221
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.623933960
Short name T1607
Test name
Test status
Simulation time 79135794030 ps
CPU time 39.4 seconds
Started Dec 31 01:08:25 PM PST 23
Finished Dec 31 01:09:06 PM PST 23
Peak memory 253776 kb
Host smart-9cedb441-7427-4347-b559-2cab78479a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623933960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.623933960
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_perf.3074104384
Short name T1708
Test name
Test status
Simulation time 179779298088 ps
CPU time 2845.56 seconds
Started Dec 31 01:08:58 PM PST 23
Finished Dec 31 01:56:31 PM PST 23
Peak memory 306664 kb
Host smart-cf39c8cc-550f-4a91-9349-e1257b36ad9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074104384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_perf.3074104384
Directory /workspace/4.spi_device_perf/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.1100637843
Short name T1724
Test name
Test status
Simulation time 18056832 ps
CPU time 0.76 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:08:58 PM PST 23
Peak memory 216736 kb
Host smart-89ca746c-6b92-410d-93a5-7f44a02ed0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100637843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.1100637843
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.551181503
Short name T873
Test name
Test status
Simulation time 6115570644 ps
CPU time 4.15 seconds
Started Dec 31 01:08:03 PM PST 23
Finished Dec 31 01:08:09 PM PST 23
Peak memory 220760 kb
Host smart-0ba89c0f-b812-464a-8d1a-78888e58d933
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=551181503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.551181503
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_rx_async_fifo_reset.3544204582
Short name T748
Test name
Test status
Simulation time 44635055 ps
CPU time 0.86 seconds
Started Dec 31 01:07:58 PM PST 23
Finished Dec 31 01:07:59 PM PST 23
Peak memory 208500 kb
Host smart-a63eb101-d311-4a0a-97de-25be380286d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544204582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_rx_async_fifo_reset.3544204582
Directory /workspace/4.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/4.spi_device_rx_timeout.341664686
Short name T1628
Test name
Test status
Simulation time 839536642 ps
CPU time 6.62 seconds
Started Dec 31 01:09:00 PM PST 23
Finished Dec 31 01:09:15 PM PST 23
Peak memory 216776 kb
Host smart-86814a80-8d58-42e3-8f2f-e1e3c6852f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341664686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_rx_timeout.341664686
Directory /workspace/4.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1426858494
Short name T77
Test name
Test status
Simulation time 222239095 ps
CPU time 1.07 seconds
Started Dec 31 01:08:03 PM PST 23
Finished Dec 31 01:08:06 PM PST 23
Peak memory 238028 kb
Host smart-ae682fb3-8354-44ed-a7b0-2a850a6685f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426858494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1426858494
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_smoke.443801156
Short name T1246
Test name
Test status
Simulation time 19188181 ps
CPU time 0.92 seconds
Started Dec 31 01:08:57 PM PST 23
Finished Dec 31 01:09:05 PM PST 23
Peak memory 207788 kb
Host smart-c8a193a7-2aae-4772-8b1f-0ecbf0111c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443801156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_smoke.443801156
Directory /workspace/4.spi_device_smoke/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.420029401
Short name T327
Test name
Test status
Simulation time 1186337491 ps
CPU time 17.96 seconds
Started Dec 31 01:09:15 PM PST 23
Finished Dec 31 01:09:35 PM PST 23
Peak memory 217128 kb
Host smart-5c688e7c-123d-40de-9777-e011cb48c537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420029401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.420029401
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1499532950
Short name T1774
Test name
Test status
Simulation time 23149454731 ps
CPU time 34.41 seconds
Started Dec 31 01:09:02 PM PST 23
Finished Dec 31 01:09:44 PM PST 23
Peak memory 216920 kb
Host smart-039d9d0f-8a3d-47c3-9cd5-62f022ae3df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499532950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1499532950
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1291365937
Short name T1335
Test name
Test status
Simulation time 10648220 ps
CPU time 0.75 seconds
Started Dec 31 01:08:10 PM PST 23
Finished Dec 31 01:08:12 PM PST 23
Peak memory 206904 kb
Host smart-3aa667f2-3481-4292-9193-3906f84b5d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291365937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1291365937
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3883961155
Short name T902
Test name
Test status
Simulation time 57334002 ps
CPU time 0.74 seconds
Started Dec 31 01:07:59 PM PST 23
Finished Dec 31 01:08:01 PM PST 23
Peak memory 206916 kb
Host smart-05a02e7d-72f7-4b16-98b3-b2e3cea0eaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883961155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3883961155
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_tx_async_fifo_reset.1608228047
Short name T1484
Test name
Test status
Simulation time 20173561 ps
CPU time 0.8 seconds
Started Dec 31 01:08:24 PM PST 23
Finished Dec 31 01:08:26 PM PST 23
Peak memory 208464 kb
Host smart-0a553163-e9a2-4db6-b8b3-a4db9e317841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608228047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tx_async_fifo_reset.1608228047
Directory /workspace/4.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/4.spi_device_txrx.524840879
Short name T1522
Test name
Test status
Simulation time 22414907118 ps
CPU time 209.89 seconds
Started Dec 31 01:08:56 PM PST 23
Finished Dec 31 01:12:32 PM PST 23
Peak memory 277404 kb
Host smart-6e7fed09-b885-4c9c-b676-579dd2b06fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524840879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_txrx.524840879
Directory /workspace/4.spi_device_txrx/latest

Test location /workspace/coverage/default/4.spi_device_upload.1775238857
Short name T1045
Test name
Test status
Simulation time 540095101 ps
CPU time 9.43 seconds
Started Dec 31 01:08:27 PM PST 23
Finished Dec 31 01:08:38 PM PST 23
Peak memory 241084 kb
Host smart-2b4c82dd-2022-4686-8383-4a97d751927e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775238857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1775238857
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_abort.3577516989
Short name T1439
Test name
Test status
Simulation time 21706964 ps
CPU time 0.74 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:22 PM PST 23
Peak memory 206536 kb
Host smart-3275bf16-448c-41f5-a2d1-7434c0d28817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577516989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_abort.3577516989
Directory /workspace/40.spi_device_abort/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.729497106
Short name T706
Test name
Test status
Simulation time 47420954 ps
CPU time 0.71 seconds
Started Dec 31 01:11:25 PM PST 23
Finished Dec 31 01:11:28 PM PST 23
Peak memory 206520 kb
Host smart-ceb65aaa-62a8-42cf-9e84-b07efed4993b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729497106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.729497106
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_bit_transfer.3675491373
Short name T477
Test name
Test status
Simulation time 344693038 ps
CPU time 2.23 seconds
Started Dec 31 01:11:19 PM PST 23
Finished Dec 31 01:11:25 PM PST 23
Peak memory 216856 kb
Host smart-79e2caa8-1c91-4d29-9fe7-320ae0f3051b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675491373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_bit_transfer.3675491373
Directory /workspace/40.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/40.spi_device_byte_transfer.4046565965
Short name T828
Test name
Test status
Simulation time 382711378 ps
CPU time 3.18 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:11:23 PM PST 23
Peak memory 216736 kb
Host smart-200e8c7c-69d9-4c54-a8f2-1ea64af05d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046565965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_byte_transfer.4046565965
Directory /workspace/40.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1076326922
Short name T1204
Test name
Test status
Simulation time 506619708 ps
CPU time 3.13 seconds
Started Dec 31 01:11:17 PM PST 23
Finished Dec 31 01:11:24 PM PST 23
Peak memory 225088 kb
Host smart-83d09b17-b952-4ed6-b072-756babf0511f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076326922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1076326922
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2987970039
Short name T798
Test name
Test status
Simulation time 57659938 ps
CPU time 0.77 seconds
Started Dec 31 01:11:17 PM PST 23
Finished Dec 31 01:11:21 PM PST 23
Peak memory 207588 kb
Host smart-4b2f2b11-18ec-4de1-83c4-c8d6acd3d73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987970039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2987970039
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_dummy_item_extra_dly.4111985007
Short name T1327
Test name
Test status
Simulation time 67307873107 ps
CPU time 182.33 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:14:25 PM PST 23
Peak memory 270468 kb
Host smart-fb8830cd-7d34-4a23-a82d-007950305984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111985007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_dummy_item_extra_dly.4111985007
Directory /workspace/40.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/40.spi_device_extreme_fifo_size.1402069723
Short name T619
Test name
Test status
Simulation time 85620639447 ps
CPU time 1186.11 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:31:08 PM PST 23
Peak memory 220788 kb
Host smart-be16535a-2d1b-4564-9c25-2cf71307fd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402069723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_extreme_fifo_size.1402069723
Directory /workspace/40.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/40.spi_device_fifo_full.3140300728
Short name T1515
Test name
Test status
Simulation time 85680007884 ps
CPU time 2514.65 seconds
Started Dec 31 01:11:54 PM PST 23
Finished Dec 31 01:53:50 PM PST 23
Peak memory 295432 kb
Host smart-369e438d-acec-4977-8ebf-55c07832a603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140300728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_fifo_full.3140300728
Directory /workspace/40.spi_device_fifo_full/latest

Test location /workspace/coverage/default/40.spi_device_fifo_underflow_overflow.2872875595
Short name T766
Test name
Test status
Simulation time 94951591424 ps
CPU time 212.51 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:14:55 PM PST 23
Peak memory 402256 kb
Host smart-2278dbbb-d244-4587-9c4c-fcc6dd83909d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872875595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_fifo_underflow_overf
low.2872875595
Directory /workspace/40.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3156371744
Short name T786
Test name
Test status
Simulation time 11101979485 ps
CPU time 64.52 seconds
Started Dec 31 01:11:17 PM PST 23
Finished Dec 31 01:12:26 PM PST 23
Peak memory 250952 kb
Host smart-fa7c0d3d-6f81-4337-b6f8-1a6c9b95e0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156371744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3156371744
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3368750123
Short name T1223
Test name
Test status
Simulation time 18834646897 ps
CPU time 23.24 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:11:40 PM PST 23
Peak memory 244120 kb
Host smart-94d740c0-289f-485a-aecd-e1b6b230ce10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368750123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3368750123
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4011192488
Short name T1075
Test name
Test status
Simulation time 5118391321 ps
CPU time 8.16 seconds
Started Dec 31 01:11:20 PM PST 23
Finished Dec 31 01:11:33 PM PST 23
Peak memory 238284 kb
Host smart-98c911ea-66c8-4148-8c8a-8bc0d7aaa893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011192488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4011192488
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_intr.2641904842
Short name T1764
Test name
Test status
Simulation time 8420136486 ps
CPU time 47.77 seconds
Started Dec 31 01:11:17 PM PST 23
Finished Dec 31 01:12:08 PM PST 23
Peak memory 238716 kb
Host smart-32dc3eed-1951-45b1-b983-05ed97cbb6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641904842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intr.2641904842
Directory /workspace/40.spi_device_intr/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3980973647
Short name T1749
Test name
Test status
Simulation time 906839253 ps
CPU time 5.85 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:28 PM PST 23
Peak memory 241420 kb
Host smart-3c3103ed-9e05-407e-99d0-0ce9710e5c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980973647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3980973647
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1298922909
Short name T1138
Test name
Test status
Simulation time 564424022 ps
CPU time 8.33 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:31 PM PST 23
Peak memory 247632 kb
Host smart-f9668e01-fafc-44b9-b00a-828122f484a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298922909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1298922909
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3598998322
Short name T1209
Test name
Test status
Simulation time 194837440 ps
CPU time 4.59 seconds
Started Dec 31 01:11:19 PM PST 23
Finished Dec 31 01:11:28 PM PST 23
Peak memory 241444 kb
Host smart-faf50988-1fe5-48b0-acfd-9f0aee6f4285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598998322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3598998322
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_perf.2767590600
Short name T833
Test name
Test status
Simulation time 69622955519 ps
CPU time 473.9 seconds
Started Dec 31 01:11:19 PM PST 23
Finished Dec 31 01:19:17 PM PST 23
Peak memory 249800 kb
Host smart-b5195aa0-4a33-463b-8d32-c48d759c9746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767590600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_perf.2767590600
Directory /workspace/40.spi_device_perf/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1523999500
Short name T802
Test name
Test status
Simulation time 7283474034 ps
CPU time 5.49 seconds
Started Dec 31 01:11:20 PM PST 23
Finished Dec 31 01:11:31 PM PST 23
Peak memory 219032 kb
Host smart-cf6ed61a-21a6-4570-90c9-1dd37cbb7964
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1523999500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1523999500
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_rx_async_fifo_reset.602020252
Short name T793
Test name
Test status
Simulation time 38726487 ps
CPU time 0.86 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:11:18 PM PST 23
Peak memory 208504 kb
Host smart-0f799fbf-7bb7-4403-b7a0-aae2aaf52c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602020252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_rx_async_fifo_reset.602020252
Directory /workspace/40.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/40.spi_device_rx_timeout.3740746140
Short name T1399
Test name
Test status
Simulation time 2632230685 ps
CPU time 6.21 seconds
Started Dec 31 01:11:17 PM PST 23
Finished Dec 31 01:11:27 PM PST 23
Peak memory 216844 kb
Host smart-90593cb7-58ad-414d-81cf-7f5ea66d5f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740746140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_rx_timeout.3740746140
Directory /workspace/40.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/40.spi_device_smoke.1188399785
Short name T622
Test name
Test status
Simulation time 256597058 ps
CPU time 1.31 seconds
Started Dec 31 01:11:40 PM PST 23
Finished Dec 31 01:11:42 PM PST 23
Peak memory 216784 kb
Host smart-29bf73c3-1cee-4e08-a1d6-9f9189336e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188399785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_smoke.1188399785
Directory /workspace/40.spi_device_smoke/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.399538504
Short name T1221
Test name
Test status
Simulation time 119989112397 ps
CPU time 44.41 seconds
Started Dec 31 01:11:21 PM PST 23
Finished Dec 31 01:12:11 PM PST 23
Peak memory 217000 kb
Host smart-8b3d391f-f321-4649-97d8-e6c65b25ee17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399538504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.399538504
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2508096973
Short name T857
Test name
Test status
Simulation time 3173515544 ps
CPU time 12.93 seconds
Started Dec 31 01:11:20 PM PST 23
Finished Dec 31 01:11:38 PM PST 23
Peak memory 216828 kb
Host smart-70e96f6f-3aef-489e-a0ed-18e2e3be84e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508096973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2508096973
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1885846979
Short name T1173
Test name
Test status
Simulation time 18248379 ps
CPU time 1 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:11:20 PM PST 23
Peak memory 207932 kb
Host smart-8fc02c7e-e4c0-41a7-8b8c-6e63e3871590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885846979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1885846979
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3090661366
Short name T90
Test name
Test status
Simulation time 28894559 ps
CPU time 0.82 seconds
Started Dec 31 01:11:18 PM PST 23
Finished Dec 31 01:11:23 PM PST 23
Peak memory 206836 kb
Host smart-3d029298-3a29-490a-9419-928fcdf9a03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090661366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3090661366
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_tx_async_fifo_reset.764658880
Short name T1220
Test name
Test status
Simulation time 16805920 ps
CPU time 0.78 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:11:19 PM PST 23
Peak memory 208300 kb
Host smart-3f04b497-99b8-4d9f-9a76-848b0b60179e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764658880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tx_async_fifo_reset.764658880
Directory /workspace/40.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/40.spi_device_txrx.1178667104
Short name T523
Test name
Test status
Simulation time 117847330831 ps
CPU time 280.89 seconds
Started Dec 31 01:12:13 PM PST 23
Finished Dec 31 01:16:55 PM PST 23
Peak memory 282708 kb
Host smart-709c58d2-5c7f-470d-8045-ad5ae812c57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178667104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_txrx.1178667104
Directory /workspace/40.spi_device_txrx/latest

Test location /workspace/coverage/default/40.spi_device_upload.2383473347
Short name T1165
Test name
Test status
Simulation time 1285596148 ps
CPU time 10.37 seconds
Started Dec 31 01:11:25 PM PST 23
Finished Dec 31 01:11:38 PM PST 23
Peak memory 239408 kb
Host smart-dbccba5f-2772-44d3-96ed-26ad0f678ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383473347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2383473347
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_abort.2605194098
Short name T1011
Test name
Test status
Simulation time 49865200 ps
CPU time 0.77 seconds
Started Dec 31 01:11:43 PM PST 23
Finished Dec 31 01:11:45 PM PST 23
Peak memory 206652 kb
Host smart-608354cd-2cf5-4c69-b044-4b5a038ca1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605194098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_abort.2605194098
Directory /workspace/41.spi_device_abort/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3772227065
Short name T1231
Test name
Test status
Simulation time 33549014 ps
CPU time 0.71 seconds
Started Dec 31 01:11:44 PM PST 23
Finished Dec 31 01:11:46 PM PST 23
Peak memory 206448 kb
Host smart-afeaeea4-4aea-41b0-a02d-69adf769dbf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772227065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3772227065
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_bit_transfer.3346169066
Short name T1443
Test name
Test status
Simulation time 214136642 ps
CPU time 2.59 seconds
Started Dec 31 01:11:43 PM PST 23
Finished Dec 31 01:11:47 PM PST 23
Peak memory 216808 kb
Host smart-247b15c1-0c8d-4cf1-ac88-8d878b4554a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346169066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_bit_transfer.3346169066
Directory /workspace/41.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/41.spi_device_byte_transfer.1895219303
Short name T821
Test name
Test status
Simulation time 297944350 ps
CPU time 3.72 seconds
Started Dec 31 01:11:57 PM PST 23
Finished Dec 31 01:12:02 PM PST 23
Peak memory 216860 kb
Host smart-c0ecb5b3-5fa0-48db-b544-657702034e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895219303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_byte_transfer.1895219303
Directory /workspace/41.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2235547021
Short name T1657
Test name
Test status
Simulation time 1113731749 ps
CPU time 5.28 seconds
Started Dec 31 01:12:12 PM PST 23
Finished Dec 31 01:12:19 PM PST 23
Peak memory 218764 kb
Host smart-dd1ba84b-fdbb-4ae5-b044-a49620ffad13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235547021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2235547021
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1226504463
Short name T458
Test name
Test status
Simulation time 16041498 ps
CPU time 0.77 seconds
Started Dec 31 01:11:25 PM PST 23
Finished Dec 31 01:11:29 PM PST 23
Peak memory 206580 kb
Host smart-7d1e50fe-b4aa-41f9-adc3-0cda44613f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226504463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1226504463
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_dummy_item_extra_dly.506857193
Short name T818
Test name
Test status
Simulation time 144650824371 ps
CPU time 244.14 seconds
Started Dec 31 01:11:23 PM PST 23
Finished Dec 31 01:15:31 PM PST 23
Peak memory 287688 kb
Host smart-75292dfb-39eb-4ada-a777-4b3f8ff7ae3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506857193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_dummy_item_extra_dly.506857193
Directory /workspace/41.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/41.spi_device_extreme_fifo_size.3865248413
Short name T1662
Test name
Test status
Simulation time 248597650953 ps
CPU time 1032.24 seconds
Started Dec 31 01:11:23 PM PST 23
Finished Dec 31 01:28:39 PM PST 23
Peak memory 225136 kb
Host smart-9ba2fb91-317f-472d-8a56-292212744a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865248413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_extreme_fifo_size.3865248413
Directory /workspace/41.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/41.spi_device_fifo_full.2699127663
Short name T450
Test name
Test status
Simulation time 30798606790 ps
CPU time 707.59 seconds
Started Dec 31 01:11:16 PM PST 23
Finished Dec 31 01:23:07 PM PST 23
Peak memory 299872 kb
Host smart-22b78e39-2745-4cf1-9fa5-2dbb20dca97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699127663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_fifo_full.2699127663
Directory /workspace/41.spi_device_fifo_full/latest

Test location /workspace/coverage/default/41.spi_device_fifo_underflow_overflow.732883373
Short name T551
Test name
Test status
Simulation time 528444336078 ps
CPU time 869.47 seconds
Started Dec 31 01:11:23 PM PST 23
Finished Dec 31 01:25:57 PM PST 23
Peak memory 633172 kb
Host smart-e074c3b2-3b54-469c-8c8c-295ee0047e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732883373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_fifo_underflow_overfl
ow.732883373
Directory /workspace/41.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.4096328500
Short name T1541
Test name
Test status
Simulation time 16242492108 ps
CPU time 38.72 seconds
Started Dec 31 01:12:05 PM PST 23
Finished Dec 31 01:12:45 PM PST 23
Peak memory 249728 kb
Host smart-2fe82fe8-f66f-4efa-a869-31c5d67747e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096328500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.4096328500
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.4620773
Short name T1713
Test name
Test status
Simulation time 361439951009 ps
CPU time 639.27 seconds
Started Dec 31 01:11:42 PM PST 23
Finished Dec 31 01:22:22 PM PST 23
Peak memory 273580 kb
Host smart-cc2e1c1e-589e-43e6-a4f0-0c51ef7b4a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4620773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.4620773
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3196368272
Short name T1078
Test name
Test status
Simulation time 5877968470 ps
CPU time 71 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:13:30 PM PST 23
Peak memory 249692 kb
Host smart-1211368a-4df9-4bbb-bb22-72ee2a9c2086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196368272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3196368272
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1639256696
Short name T1029
Test name
Test status
Simulation time 1900125721 ps
CPU time 8.76 seconds
Started Dec 31 01:11:43 PM PST 23
Finished Dec 31 01:11:53 PM PST 23
Peak memory 241372 kb
Host smart-d0b00e79-c29f-4607-97cf-2f2ef78a5c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639256696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1639256696
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_intr.692400394
Short name T87
Test name
Test status
Simulation time 101830512233 ps
CPU time 73.27 seconds
Started Dec 31 01:11:25 PM PST 23
Finished Dec 31 01:12:41 PM PST 23
Peak memory 240796 kb
Host smart-f37fa01e-14f2-49af-90a4-58f37418f2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692400394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intr.692400394
Directory /workspace/41.spi_device_intr/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2743920609
Short name T605
Test name
Test status
Simulation time 5260766594 ps
CPU time 16.8 seconds
Started Dec 31 01:11:36 PM PST 23
Finished Dec 31 01:11:53 PM PST 23
Peak memory 254864 kb
Host smart-deefe1bc-61aa-4d3d-938e-73b4e54273a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743920609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2743920609
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1157912956
Short name T251
Test name
Test status
Simulation time 608806560 ps
CPU time 10.52 seconds
Started Dec 31 01:11:55 PM PST 23
Finished Dec 31 01:12:06 PM PST 23
Peak memory 228016 kb
Host smart-3efbad22-c668-4cb4-9716-1c9e399bbf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157912956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1157912956
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2487077855
Short name T259
Test name
Test status
Simulation time 233653299 ps
CPU time 3.43 seconds
Started Dec 31 01:11:42 PM PST 23
Finished Dec 31 01:11:47 PM PST 23
Peak memory 234360 kb
Host smart-59bc117b-fd5a-46c7-9d31-1a57895819b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487077855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2487077855
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_perf.975949085
Short name T851
Test name
Test status
Simulation time 96389530769 ps
CPU time 1674 seconds
Started Dec 31 01:11:20 PM PST 23
Finished Dec 31 01:39:20 PM PST 23
Peak memory 263988 kb
Host smart-df0b65dd-75e9-416d-ba90-949ac19adc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975949085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_perf.975949085
Directory /workspace/41.spi_device_perf/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3809936179
Short name T1111
Test name
Test status
Simulation time 95864156 ps
CPU time 4.3 seconds
Started Dec 31 01:11:42 PM PST 23
Finished Dec 31 01:11:47 PM PST 23
Peak memory 236032 kb
Host smart-f9f03ad1-bb7b-4457-b72d-f7a3594f1822
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3809936179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3809936179
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_rx_async_fifo_reset.1229747278
Short name T758
Test name
Test status
Simulation time 57143747 ps
CPU time 0.87 seconds
Started Dec 31 01:11:42 PM PST 23
Finished Dec 31 01:11:45 PM PST 23
Peak memory 208504 kb
Host smart-2497a54d-a45b-45d4-9bf8-5e3534b8547e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229747278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_rx_async_fifo_reset.1229747278
Directory /workspace/41.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/41.spi_device_rx_timeout.812266186
Short name T1410
Test name
Test status
Simulation time 1091840034 ps
CPU time 4.72 seconds
Started Dec 31 01:11:54 PM PST 23
Finished Dec 31 01:11:59 PM PST 23
Peak memory 216768 kb
Host smart-1d40bab3-4cbc-40aa-8965-00937ed959ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812266186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_rx_timeout.812266186
Directory /workspace/41.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/41.spi_device_smoke.4008351151
Short name T1593
Test name
Test status
Simulation time 38749414 ps
CPU time 1.09 seconds
Started Dec 31 01:11:15 PM PST 23
Finished Dec 31 01:11:18 PM PST 23
Peak memory 216452 kb
Host smart-7bf39ceb-1724-4c8b-a64b-bbb12dd64e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008351151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_smoke.4008351151
Directory /workspace/41.spi_device_smoke/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.661629323
Short name T1401
Test name
Test status
Simulation time 22853599859 ps
CPU time 43.15 seconds
Started Dec 31 01:11:42 PM PST 23
Finished Dec 31 01:12:26 PM PST 23
Peak memory 220368 kb
Host smart-bb066459-56ad-4fa6-8ab3-1e88e1302b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661629323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.661629323
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3362553221
Short name T1225
Test name
Test status
Simulation time 33299821962 ps
CPU time 21.89 seconds
Started Dec 31 01:12:07 PM PST 23
Finished Dec 31 01:12:31 PM PST 23
Peak memory 216876 kb
Host smart-95bf32bc-8f51-49ff-9c17-aa972cfd635b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362553221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3362553221
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3832973864
Short name T633
Test name
Test status
Simulation time 39277242 ps
CPU time 1.97 seconds
Started Dec 31 01:11:44 PM PST 23
Finished Dec 31 01:11:47 PM PST 23
Peak memory 216792 kb
Host smart-de8c6e1f-21bc-4570-a04c-23e2fc5b4d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832973864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3832973864
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2493347432
Short name T1714
Test name
Test status
Simulation time 216673799 ps
CPU time 1.05 seconds
Started Dec 31 01:11:56 PM PST 23
Finished Dec 31 01:11:58 PM PST 23
Peak memory 208016 kb
Host smart-37f6f97e-45c9-4d72-8bb3-35e664a84a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493347432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2493347432
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_tx_async_fifo_reset.335901448
Short name T1343
Test name
Test status
Simulation time 19466683 ps
CPU time 0.77 seconds
Started Dec 31 01:12:03 PM PST 23
Finished Dec 31 01:12:04 PM PST 23
Peak memory 208352 kb
Host smart-ca17d988-1c7c-4e0f-8a39-cc4cf48338a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335901448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tx_async_fifo_reset.335901448
Directory /workspace/41.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/41.spi_device_txrx.1773686753
Short name T179
Test name
Test status
Simulation time 71651693808 ps
CPU time 191.02 seconds
Started Dec 31 01:11:19 PM PST 23
Finished Dec 31 01:14:35 PM PST 23
Peak memory 284628 kb
Host smart-47dfd2f2-2696-4b51-9402-10826616c05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773686753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_txrx.1773686753
Directory /workspace/41.spi_device_txrx/latest

Test location /workspace/coverage/default/41.spi_device_upload.1184278895
Short name T1311
Test name
Test status
Simulation time 6591862993 ps
CPU time 9.58 seconds
Started Dec 31 01:11:41 PM PST 23
Finished Dec 31 01:11:52 PM PST 23
Peak memory 228628 kb
Host smart-44cdf0e0-c189-405d-a828-ff90fa8f2b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184278895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1184278895
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_abort.4053879721
Short name T1417
Test name
Test status
Simulation time 48058024 ps
CPU time 0.76 seconds
Started Dec 31 01:12:05 PM PST 23
Finished Dec 31 01:12:07 PM PST 23
Peak memory 206652 kb
Host smart-f4a3892c-73d6-4887-a3d7-fb1c7c2451e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053879721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_abort.4053879721
Directory /workspace/42.spi_device_abort/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.4132055093
Short name T1089
Test name
Test status
Simulation time 14907671 ps
CPU time 0.76 seconds
Started Dec 31 01:12:03 PM PST 23
Finished Dec 31 01:12:04 PM PST 23
Peak memory 206452 kb
Host smart-7ee99c47-771c-42f4-ba3f-b54f8738861f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132055093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
4132055093
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_bit_transfer.747119304
Short name T1312
Test name
Test status
Simulation time 113316851 ps
CPU time 2.44 seconds
Started Dec 31 01:12:04 PM PST 23
Finished Dec 31 01:12:08 PM PST 23
Peak memory 216800 kb
Host smart-22196d83-491b-4969-afa6-3b2a68e89d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747119304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_bit_transfer.747119304
Directory /workspace/42.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/42.spi_device_byte_transfer.3426114896
Short name T607
Test name
Test status
Simulation time 329597952 ps
CPU time 2.95 seconds
Started Dec 31 01:11:42 PM PST 23
Finished Dec 31 01:11:47 PM PST 23
Peak memory 216820 kb
Host smart-37f8421d-597e-43d1-ae89-732a712a8bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426114896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_byte_transfer.3426114896
Directory /workspace/42.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3094518444
Short name T1426
Test name
Test status
Simulation time 7423194749 ps
CPU time 8.15 seconds
Started Dec 31 01:11:42 PM PST 23
Finished Dec 31 01:11:52 PM PST 23
Peak memory 241612 kb
Host smart-1c7770d7-3a54-46a7-9fe8-c553008314d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094518444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3094518444
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1887768451
Short name T949
Test name
Test status
Simulation time 24920589 ps
CPU time 0.81 seconds
Started Dec 31 01:11:41 PM PST 23
Finished Dec 31 01:11:43 PM PST 23
Peak memory 207632 kb
Host smart-260862c7-0480-4eab-8814-6b31917cc7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887768451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1887768451
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_dummy_item_extra_dly.2371366632
Short name T1500
Test name
Test status
Simulation time 147986789926 ps
CPU time 566.31 seconds
Started Dec 31 01:12:06 PM PST 23
Finished Dec 31 01:21:34 PM PST 23
Peak memory 321844 kb
Host smart-aa448dbe-f55f-4bfa-927f-1bc6e391b750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371366632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_dummy_item_extra_dly.2371366632
Directory /workspace/42.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/42.spi_device_extreme_fifo_size.1428402595
Short name T946
Test name
Test status
Simulation time 76981055547 ps
CPU time 1326.05 seconds
Started Dec 31 01:11:41 PM PST 23
Finished Dec 31 01:33:49 PM PST 23
Peak memory 221064 kb
Host smart-1758f8f9-92d2-40ae-b5ef-56b490bb18eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428402595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_extreme_fifo_size.1428402595
Directory /workspace/42.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/42.spi_device_fifo_full.1024310774
Short name T1052
Test name
Test status
Simulation time 42866542105 ps
CPU time 358.59 seconds
Started Dec 31 01:11:41 PM PST 23
Finished Dec 31 01:17:40 PM PST 23
Peak memory 260244 kb
Host smart-3c79d49c-49b5-41a4-8eac-7a1c25fb6a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024310774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_fifo_full.1024310774
Directory /workspace/42.spi_device_fifo_full/latest

Test location /workspace/coverage/default/42.spi_device_fifo_underflow_overflow.486655588
Short name T1206
Test name
Test status
Simulation time 209327586703 ps
CPU time 540.78 seconds
Started Dec 31 01:12:12 PM PST 23
Finished Dec 31 01:21:13 PM PST 23
Peak memory 515516 kb
Host smart-cbd46968-49af-4f70-9889-205ad0973b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486655588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_fifo_underflow_overfl
ow.486655588
Directory /workspace/42.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2722124607
Short name T1552
Test name
Test status
Simulation time 9178821336 ps
CPU time 98.73 seconds
Started Dec 31 01:12:16 PM PST 23
Finished Dec 31 01:13:58 PM PST 23
Peak memory 273056 kb
Host smart-f7326876-84bd-47f2-ba11-08150471801d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722124607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2722124607
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1512631344
Short name T994
Test name
Test status
Simulation time 6788859975 ps
CPU time 99.49 seconds
Started Dec 31 01:11:40 PM PST 23
Finished Dec 31 01:13:21 PM PST 23
Peak memory 255776 kb
Host smart-323bda97-2f6a-4034-98d2-56337575353b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512631344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1512631344
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1815325574
Short name T753
Test name
Test status
Simulation time 6937706329 ps
CPU time 88.2 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:13:47 PM PST 23
Peak memory 223860 kb
Host smart-f62584a3-ce55-46e4-b17a-e65659c2751b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815325574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1815325574
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1335720135
Short name T878
Test name
Test status
Simulation time 15889370461 ps
CPU time 27.99 seconds
Started Dec 31 01:11:42 PM PST 23
Finished Dec 31 01:12:11 PM PST 23
Peak memory 249192 kb
Host smart-c77d3b7d-252e-48c1-810b-014dfeb74cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335720135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1335720135
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1042898915
Short name T1741
Test name
Test status
Simulation time 3525516824 ps
CPU time 7.12 seconds
Started Dec 31 01:12:05 PM PST 23
Finished Dec 31 01:12:13 PM PST 23
Peak memory 220784 kb
Host smart-b0a02111-a4d5-4330-8710-1cb371ed12cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042898915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1042898915
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_intr.475431989
Short name T557
Test name
Test status
Simulation time 11179220763 ps
CPU time 52.22 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:13:08 PM PST 23
Peak memory 233384 kb
Host smart-98deb9be-8dcf-4f54-a17b-e2f77c40bbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475431989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intr.475431989
Directory /workspace/42.spi_device_intr/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2242392476
Short name T1074
Test name
Test status
Simulation time 1365478373 ps
CPU time 16.69 seconds
Started Dec 31 01:12:07 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 234852 kb
Host smart-2f477eae-8575-47ef-8da3-dadefd9f8859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242392476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2242392476
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3689967509
Short name T1652
Test name
Test status
Simulation time 250225942 ps
CPU time 3.03 seconds
Started Dec 31 01:12:08 PM PST 23
Finished Dec 31 01:12:13 PM PST 23
Peak memory 234380 kb
Host smart-6591cdbc-00bd-44ac-b254-45960ec53db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689967509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3689967509
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.806751588
Short name T1179
Test name
Test status
Simulation time 80747511 ps
CPU time 3.32 seconds
Started Dec 31 01:11:56 PM PST 23
Finished Dec 31 01:12:00 PM PST 23
Peak memory 239268 kb
Host smart-691bce9a-47ae-48c9-b7d9-fd2789b8ab33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806751588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.806751588
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_perf.744912636
Short name T1735
Test name
Test status
Simulation time 27033663129 ps
CPU time 565.08 seconds
Started Dec 31 01:11:54 PM PST 23
Finished Dec 31 01:21:20 PM PST 23
Peak memory 257928 kb
Host smart-bfc6c36f-9ff9-4306-bf50-5fe273aa40cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744912636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_perf.744912636
Directory /workspace/42.spi_device_perf/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1107056364
Short name T1518
Test name
Test status
Simulation time 181470771 ps
CPU time 3.31 seconds
Started Dec 31 01:11:56 PM PST 23
Finished Dec 31 01:12:01 PM PST 23
Peak memory 220320 kb
Host smart-204d5db6-a937-4a12-91a3-0a3a4ec33fcf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1107056364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1107056364
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_rx_async_fifo_reset.982693200
Short name T1483
Test name
Test status
Simulation time 79445493 ps
CPU time 0.91 seconds
Started Dec 31 01:12:06 PM PST 23
Finished Dec 31 01:12:08 PM PST 23
Peak memory 208492 kb
Host smart-6422dfd6-46fb-405c-94ae-05201fb87e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982693200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_rx_async_fifo_reset.982693200
Directory /workspace/42.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/42.spi_device_rx_timeout.3364831202
Short name T1158
Test name
Test status
Simulation time 2285847248 ps
CPU time 6.06 seconds
Started Dec 31 01:11:42 PM PST 23
Finished Dec 31 01:11:49 PM PST 23
Peak memory 216848 kb
Host smart-1caaa565-aa94-422a-8631-6d55a8f0b615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364831202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_rx_timeout.3364831202
Directory /workspace/42.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/42.spi_device_smoke.447830995
Short name T916
Test name
Test status
Simulation time 20841620 ps
CPU time 0.95 seconds
Started Dec 31 01:11:38 PM PST 23
Finished Dec 31 01:11:40 PM PST 23
Peak memory 207928 kb
Host smart-b7e26c2a-3676-4860-b33f-85f86c24d49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447830995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_smoke.447830995
Directory /workspace/42.spi_device_smoke/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.547807828
Short name T1267
Test name
Test status
Simulation time 250949013804 ps
CPU time 1412.92 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:35:50 PM PST 23
Peak memory 495876 kb
Host smart-b49e7bf5-aa1d-47b4-8e67-c1002f12aa1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547807828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.547807828
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2535208926
Short name T1580
Test name
Test status
Simulation time 12542521739 ps
CPU time 86.84 seconds
Started Dec 31 01:11:43 PM PST 23
Finished Dec 31 01:13:11 PM PST 23
Peak memory 216880 kb
Host smart-6ac0697d-74e8-4fa7-82bc-a06c4c9cbe58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535208926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2535208926
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1964491811
Short name T986
Test name
Test status
Simulation time 1371093959 ps
CPU time 9.48 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 216844 kb
Host smart-645c8653-c5fb-4f32-9b9f-ef36c8fa4f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964491811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1964491811
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3275508009
Short name T1293
Test name
Test status
Simulation time 18874878 ps
CPU time 1.04 seconds
Started Dec 31 01:12:05 PM PST 23
Finished Dec 31 01:12:07 PM PST 23
Peak memory 208092 kb
Host smart-37da50e0-989c-4097-82fa-4cf952104fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275508009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3275508009
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.461243783
Short name T788
Test name
Test status
Simulation time 37784651 ps
CPU time 0.88 seconds
Started Dec 31 01:11:55 PM PST 23
Finished Dec 31 01:11:57 PM PST 23
Peak memory 206900 kb
Host smart-8d39bc6d-0bb4-498f-96a9-f560e8f7d836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461243783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.461243783
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_tx_async_fifo_reset.2431047455
Short name T839
Test name
Test status
Simulation time 26035163 ps
CPU time 0.77 seconds
Started Dec 31 01:12:07 PM PST 23
Finished Dec 31 01:12:10 PM PST 23
Peak memory 208460 kb
Host smart-ef77bca4-ffc0-43ac-8bdb-d8d111664acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431047455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tx_async_fifo_reset.2431047455
Directory /workspace/42.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/42.spi_device_txrx.674539998
Short name T650
Test name
Test status
Simulation time 39771521198 ps
CPU time 123.4 seconds
Started Dec 31 01:11:43 PM PST 23
Finished Dec 31 01:13:48 PM PST 23
Peak memory 282184 kb
Host smart-297dd51b-7e6b-48d8-bf3b-abb9d5d7508c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674539998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_txrx.674539998
Directory /workspace/42.spi_device_txrx/latest

Test location /workspace/coverage/default/42.spi_device_upload.2601796685
Short name T1728
Test name
Test status
Simulation time 3112799399 ps
CPU time 12.21 seconds
Started Dec 31 01:11:41 PM PST 23
Finished Dec 31 01:11:54 PM PST 23
Peak memory 228388 kb
Host smart-82c876f3-4724-490c-ac42-7907cff3f126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601796685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2601796685
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_abort.3578985266
Short name T907
Test name
Test status
Simulation time 15905746 ps
CPU time 0.75 seconds
Started Dec 31 01:11:56 PM PST 23
Finished Dec 31 01:11:58 PM PST 23
Peak memory 206568 kb
Host smart-31a56240-9dfa-44c1-86a1-65c927764ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578985266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_abort.3578985266
Directory /workspace/43.spi_device_abort/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.908601475
Short name T1453
Test name
Test status
Simulation time 33574936 ps
CPU time 0.72 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:12:19 PM PST 23
Peak memory 206416 kb
Host smart-3f1ec627-e7ab-40dd-895b-dcdd060a47a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908601475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.908601475
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_bit_transfer.4258556776
Short name T1062
Test name
Test status
Simulation time 106320081 ps
CPU time 2.34 seconds
Started Dec 31 01:11:42 PM PST 23
Finished Dec 31 01:11:46 PM PST 23
Peak memory 216836 kb
Host smart-2eab9a30-76fe-48ba-aed5-c08e822f8d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258556776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_bit_transfer.4258556776
Directory /workspace/43.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/43.spi_device_byte_transfer.956832490
Short name T525
Test name
Test status
Simulation time 259030884 ps
CPU time 3.17 seconds
Started Dec 31 01:11:44 PM PST 23
Finished Dec 31 01:11:48 PM PST 23
Peak memory 216740 kb
Host smart-a31953e1-a964-459b-a408-8e569090a0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956832490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_byte_transfer.956832490
Directory /workspace/43.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1676728754
Short name T92
Test name
Test status
Simulation time 305133370 ps
CPU time 3.19 seconds
Started Dec 31 01:11:57 PM PST 23
Finished Dec 31 01:12:01 PM PST 23
Peak memory 225040 kb
Host smart-9368da05-e0e2-4c93-a1bd-595c1776d8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676728754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1676728754
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.400321902
Short name T806
Test name
Test status
Simulation time 40162955 ps
CPU time 0.78 seconds
Started Dec 31 01:12:08 PM PST 23
Finished Dec 31 01:12:10 PM PST 23
Peak memory 207604 kb
Host smart-df62e757-1b02-45af-b4f8-60e6398a8368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400321902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.400321902
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_dummy_item_extra_dly.2094541742
Short name T1164
Test name
Test status
Simulation time 155053114773 ps
CPU time 163.18 seconds
Started Dec 31 01:12:07 PM PST 23
Finished Dec 31 01:14:52 PM PST 23
Peak memory 265840 kb
Host smart-de222e14-eac4-447a-86a2-e6a7d1a6cb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094541742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_dummy_item_extra_dly.2094541742
Directory /workspace/43.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/43.spi_device_extreme_fifo_size.3144687827
Short name T1589
Test name
Test status
Simulation time 4448280730 ps
CPU time 38.4 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:12:57 PM PST 23
Peak memory 225016 kb
Host smart-b300365a-d7d0-4287-937f-fa07de1b4dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144687827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_extreme_fifo_size.3144687827
Directory /workspace/43.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/43.spi_device_fifo_full.3879497292
Short name T1317
Test name
Test status
Simulation time 29996097612 ps
CPU time 1449.09 seconds
Started Dec 31 01:11:42 PM PST 23
Finished Dec 31 01:35:53 PM PST 23
Peak memory 276412 kb
Host smart-169a9eb3-6564-4d10-b210-9b1f300b9627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879497292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_fifo_full.3879497292
Directory /workspace/43.spi_device_fifo_full/latest

Test location /workspace/coverage/default/43.spi_device_fifo_underflow_overflow.2291098774
Short name T1234
Test name
Test status
Simulation time 184344736464 ps
CPU time 848.45 seconds
Started Dec 31 01:11:56 PM PST 23
Finished Dec 31 01:26:06 PM PST 23
Peak memory 521176 kb
Host smart-c46b18de-47ad-452c-b63c-1ce383e96356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291098774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_fifo_underflow_overf
low.2291098774
Directory /workspace/43.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.191931531
Short name T314
Test name
Test status
Simulation time 234300205213 ps
CPU time 302.4 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:17:20 PM PST 23
Peak memory 265764 kb
Host smart-0fb167e7-db61-465e-8653-9810bb0ef615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191931531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.191931531
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.666437968
Short name T1489
Test name
Test status
Simulation time 6749834105 ps
CPU time 88.16 seconds
Started Dec 31 01:11:56 PM PST 23
Finished Dec 31 01:13:25 PM PST 23
Peak memory 249752 kb
Host smart-cf889e7b-b2de-498b-8b29-0118c667ee2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666437968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.666437968
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2329950702
Short name T1547
Test name
Test status
Simulation time 48783016249 ps
CPU time 179.78 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:15:25 PM PST 23
Peak memory 266300 kb
Host smart-7ff2f9e6-cd6a-456d-ba3c-e9f666c552e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329950702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2329950702
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.923178598
Short name T987
Test name
Test status
Simulation time 29255870786 ps
CPU time 25.42 seconds
Started Dec 31 01:11:45 PM PST 23
Finished Dec 31 01:12:11 PM PST 23
Peak memory 234356 kb
Host smart-772dce07-f364-484f-b008-a37ba4bf3c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923178598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.923178598
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2121125451
Short name T1581
Test name
Test status
Simulation time 5257199827 ps
CPU time 15.4 seconds
Started Dec 31 01:12:16 PM PST 23
Finished Dec 31 01:12:36 PM PST 23
Peak memory 240120 kb
Host smart-57a64f8d-dbc6-4408-a943-c1b7ab001f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121125451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2121125451
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_intr.1563555972
Short name T1093
Test name
Test status
Simulation time 3827142756 ps
CPU time 21.23 seconds
Started Dec 31 01:11:54 PM PST 23
Finished Dec 31 01:12:16 PM PST 23
Peak memory 221636 kb
Host smart-1d663ed8-17e2-4543-983b-5f6d6277e0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563555972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intr.1563555972
Directory /workspace/43.spi_device_intr/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2636259437
Short name T1099
Test name
Test status
Simulation time 102374890811 ps
CPU time 42.49 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:13:01 PM PST 23
Peak memory 246660 kb
Host smart-f574dfc4-df70-4fb8-8bea-cb1378f9b0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636259437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2636259437
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.603841402
Short name T1689
Test name
Test status
Simulation time 4116547727 ps
CPU time 9.99 seconds
Started Dec 31 01:11:55 PM PST 23
Finished Dec 31 01:12:05 PM PST 23
Peak memory 233360 kb
Host smart-2b8f712b-8a90-4891-bb6d-0f50e845136f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603841402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.603841402
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.4119087285
Short name T12
Test name
Test status
Simulation time 69428191473 ps
CPU time 30.4 seconds
Started Dec 31 01:11:44 PM PST 23
Finished Dec 31 01:12:16 PM PST 23
Peak memory 227756 kb
Host smart-96b0e525-2e53-456e-bf3b-7431236499de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119087285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.4119087285
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_perf.1945423747
Short name T801
Test name
Test status
Simulation time 47276497768 ps
CPU time 619.75 seconds
Started Dec 31 01:12:05 PM PST 23
Finished Dec 31 01:22:26 PM PST 23
Peak memory 284644 kb
Host smart-486b3b19-c4bc-4fe4-96b7-aa3e2f1fe7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945423747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_perf.1945423747
Directory /workspace/43.spi_device_perf/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.215922691
Short name T960
Test name
Test status
Simulation time 1194357446 ps
CPU time 6.76 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 236428 kb
Host smart-4eb2510d-a653-41c9-87ce-5f3dbd65d594
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=215922691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.215922691
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_rx_async_fifo_reset.3919233259
Short name T774
Test name
Test status
Simulation time 77489327 ps
CPU time 0.9 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:12:19 PM PST 23
Peak memory 208488 kb
Host smart-624c1b95-91cf-4c7c-8eba-f574efe578e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919233259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_rx_async_fifo_reset.3919233259
Directory /workspace/43.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/43.spi_device_rx_timeout.1236204371
Short name T1604
Test name
Test status
Simulation time 2222473131 ps
CPU time 5.88 seconds
Started Dec 31 01:12:07 PM PST 23
Finished Dec 31 01:12:14 PM PST 23
Peak memory 216788 kb
Host smart-df092a13-4274-43da-9aa9-dd73fd176271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236204371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_rx_timeout.1236204371
Directory /workspace/43.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/43.spi_device_smoke.480099092
Short name T972
Test name
Test status
Simulation time 79768074 ps
CPU time 1.14 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:12:20 PM PST 23
Peak memory 216516 kb
Host smart-37046b8d-74c7-4186-8e4c-c1d8c3fc4787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480099092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_smoke.480099092
Directory /workspace/43.spi_device_smoke/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2542244793
Short name T1060
Test name
Test status
Simulation time 2439831148 ps
CPU time 34.17 seconds
Started Dec 31 01:11:55 PM PST 23
Finished Dec 31 01:12:30 PM PST 23
Peak memory 221780 kb
Host smart-ccea8142-94e8-4866-b50f-77dffeaddab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542244793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2542244793
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1615215771
Short name T947
Test name
Test status
Simulation time 399467919 ps
CPU time 3.33 seconds
Started Dec 31 01:11:57 PM PST 23
Finished Dec 31 01:12:01 PM PST 23
Peak memory 216664 kb
Host smart-806fcc67-ee2d-4426-994c-b275f53a1804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615215771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1615215771
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3350291676
Short name T1333
Test name
Test status
Simulation time 126891394 ps
CPU time 2.29 seconds
Started Dec 31 01:11:44 PM PST 23
Finished Dec 31 01:11:48 PM PST 23
Peak memory 216828 kb
Host smart-d0b378d9-5330-4980-9af5-5cf38f7082d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350291676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3350291676
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3249172182
Short name T1497
Test name
Test status
Simulation time 20689195 ps
CPU time 0.72 seconds
Started Dec 31 01:12:16 PM PST 23
Finished Dec 31 01:12:21 PM PST 23
Peak memory 206700 kb
Host smart-f2bc076e-afa8-4c2f-a402-dfa9e098165a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249172182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3249172182
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_tx_async_fifo_reset.3259500698
Short name T1229
Test name
Test status
Simulation time 13243858 ps
CPU time 0.76 seconds
Started Dec 31 01:11:42 PM PST 23
Finished Dec 31 01:11:44 PM PST 23
Peak memory 208456 kb
Host smart-c2e33489-bbdc-48e4-8da6-dc10072cf1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259500698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tx_async_fifo_reset.3259500698
Directory /workspace/43.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/43.spi_device_txrx.628569406
Short name T1704
Test name
Test status
Simulation time 80344283053 ps
CPU time 276.25 seconds
Started Dec 31 01:11:56 PM PST 23
Finished Dec 31 01:16:34 PM PST 23
Peak memory 303348 kb
Host smart-a4151b3e-45e0-48c5-9030-89e04856ba25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628569406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_txrx.628569406
Directory /workspace/43.spi_device_txrx/latest

Test location /workspace/coverage/default/43.spi_device_upload.1114648743
Short name T1019
Test name
Test status
Simulation time 2313749951 ps
CPU time 10.05 seconds
Started Dec 31 01:11:54 PM PST 23
Finished Dec 31 01:12:05 PM PST 23
Peak memory 245428 kb
Host smart-dbef6551-8cd9-43da-9597-709f9e764a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114648743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1114648743
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_abort.390947777
Short name T1603
Test name
Test status
Simulation time 40702884 ps
CPU time 0.75 seconds
Started Dec 31 01:11:56 PM PST 23
Finished Dec 31 01:11:58 PM PST 23
Peak memory 206624 kb
Host smart-0a548fd3-5095-44c9-ad81-5222b73ca5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390947777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_abort.390947777
Directory /workspace/44.spi_device_abort/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3139175969
Short name T527
Test name
Test status
Simulation time 23029341 ps
CPU time 0.71 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:12:18 PM PST 23
Peak memory 206488 kb
Host smart-ec204913-4683-4e81-9944-c89875e83d4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139175969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3139175969
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_bit_transfer.3496349344
Short name T1065
Test name
Test status
Simulation time 66068009 ps
CPU time 2.18 seconds
Started Dec 31 01:11:57 PM PST 23
Finished Dec 31 01:12:00 PM PST 23
Peak memory 216712 kb
Host smart-8685699f-170a-41b1-99c0-1b37b123ba13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496349344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_bit_transfer.3496349344
Directory /workspace/44.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/44.spi_device_byte_transfer.3714772447
Short name T556
Test name
Test status
Simulation time 222895915 ps
CPU time 4.15 seconds
Started Dec 31 01:11:41 PM PST 23
Finished Dec 31 01:11:47 PM PST 23
Peak memory 216816 kb
Host smart-0b4832c6-8a82-4b5f-9b1d-09a05b8890a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714772447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_byte_transfer.3714772447
Directory /workspace/44.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3226651409
Short name T24
Test name
Test status
Simulation time 987823276 ps
CPU time 6.45 seconds
Started Dec 31 01:11:55 PM PST 23
Finished Dec 31 01:12:03 PM PST 23
Peak memory 238364 kb
Host smart-68cb2451-374f-41e9-acd4-1a06e70b2b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226651409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3226651409
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1202211489
Short name T467
Test name
Test status
Simulation time 42267237 ps
CPU time 0.82 seconds
Started Dec 31 01:12:04 PM PST 23
Finished Dec 31 01:12:05 PM PST 23
Peak memory 207636 kb
Host smart-9bb2cabb-3039-40dc-bb3f-fe5456a23b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202211489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1202211489
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_dummy_item_extra_dly.295442679
Short name T457
Test name
Test status
Simulation time 78769700804 ps
CPU time 210.93 seconds
Started Dec 31 01:12:16 PM PST 23
Finished Dec 31 01:15:51 PM PST 23
Peak memory 299036 kb
Host smart-be78047e-d6bd-4077-918e-14471b33740a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295442679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_dummy_item_extra_dly.295442679
Directory /workspace/44.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/44.spi_device_extreme_fifo_size.331001583
Short name T974
Test name
Test status
Simulation time 523484383226 ps
CPU time 1448.32 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:36:35 PM PST 23
Peak memory 217300 kb
Host smart-f0289a61-e6ca-4cdd-bffb-2bb7bcba456c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331001583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_extreme_fifo_size.331001583
Directory /workspace/44.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/44.spi_device_fifo_full.3028628872
Short name T1539
Test name
Test status
Simulation time 144194440533 ps
CPU time 612.72 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:22:29 PM PST 23
Peak memory 248808 kb
Host smart-9801408e-4635-4769-8c56-f80165c671ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028628872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_fifo_full.3028628872
Directory /workspace/44.spi_device_fifo_full/latest

Test location /workspace/coverage/default/44.spi_device_fifo_underflow_overflow.2365701066
Short name T1208
Test name
Test status
Simulation time 103085490365 ps
CPU time 243.64 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:16:31 PM PST 23
Peak memory 406560 kb
Host smart-abf4600b-7ee5-44a1-a27c-3560a7dd8e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365701066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_fifo_underflow_overf
low.2365701066
Directory /workspace/44.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2201189235
Short name T1321
Test name
Test status
Simulation time 50696481190 ps
CPU time 90.2 seconds
Started Dec 31 01:11:56 PM PST 23
Finished Dec 31 01:13:27 PM PST 23
Peak memory 238248 kb
Host smart-0f322cea-c905-4db0-84cb-f5f78477b645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201189235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2201189235
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3356865209
Short name T223
Test name
Test status
Simulation time 17029929499 ps
CPU time 131.31 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:14:28 PM PST 23
Peak memory 236704 kb
Host smart-91ec6adf-116c-43c7-9f9e-e83f8bfd3e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356865209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3356865209
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1350568704
Short name T1643
Test name
Test status
Simulation time 8125437150 ps
CPU time 17.63 seconds
Started Dec 31 01:12:04 PM PST 23
Finished Dec 31 01:12:22 PM PST 23
Peak memory 235392 kb
Host smart-4e13859a-e80b-48f6-82ea-297e6b5cd8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350568704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1350568704
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.4131186137
Short name T610
Test name
Test status
Simulation time 436354026 ps
CPU time 5.2 seconds
Started Dec 31 01:11:40 PM PST 23
Finished Dec 31 01:11:47 PM PST 23
Peak memory 238216 kb
Host smart-34c643a4-16c3-400a-9efc-37cffe702280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131186137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.4131186137
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_intr.3802775481
Short name T150
Test name
Test status
Simulation time 21421832846 ps
CPU time 56 seconds
Started Dec 31 01:12:23 PM PST 23
Finished Dec 31 01:13:25 PM PST 23
Peak memory 236280 kb
Host smart-0531bb14-272f-498b-95af-f07fe10951a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802775481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intr.3802775481
Directory /workspace/44.spi_device_intr/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.4172595900
Short name T451
Test name
Test status
Simulation time 514961464 ps
CPU time 6.71 seconds
Started Dec 31 01:12:12 PM PST 23
Finished Dec 31 01:12:19 PM PST 23
Peak memory 226908 kb
Host smart-47ced924-d05a-4412-90d5-272393863ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172595900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.4172595900
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.700781371
Short name T21
Test name
Test status
Simulation time 1397105268 ps
CPU time 6.4 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:12:22 PM PST 23
Peak memory 219576 kb
Host smart-058f1eac-aa08-4fd5-84c7-ed0aafd21c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700781371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.700781371
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2376985100
Short name T711
Test name
Test status
Simulation time 2377434498 ps
CPU time 10.93 seconds
Started Dec 31 01:11:56 PM PST 23
Finished Dec 31 01:12:07 PM PST 23
Peak memory 233352 kb
Host smart-584d64d7-4c64-43f7-8147-0850e5c2578f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376985100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2376985100
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_perf.963506243
Short name T1586
Test name
Test status
Simulation time 490953559596 ps
CPU time 2554.85 seconds
Started Dec 31 01:12:23 PM PST 23
Finished Dec 31 01:55:05 PM PST 23
Peak memory 249720 kb
Host smart-0814fab2-58b8-4449-bba9-d6cef9e9182e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963506243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_perf.963506243
Directory /workspace/44.spi_device_perf/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.343119456
Short name T1244
Test name
Test status
Simulation time 802429300 ps
CPU time 5.76 seconds
Started Dec 31 01:11:56 PM PST 23
Finished Dec 31 01:12:03 PM PST 23
Peak memory 234196 kb
Host smart-7534b0d8-762e-4a4a-bfc0-6146a36654f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=343119456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.343119456
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_rx_async_fifo_reset.965062046
Short name T677
Test name
Test status
Simulation time 78254140 ps
CPU time 0.86 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:12:16 PM PST 23
Peak memory 208376 kb
Host smart-d035000d-3b98-4acf-bc07-96761090ebce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965062046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_rx_async_fifo_reset.965062046
Directory /workspace/44.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/44.spi_device_rx_timeout.3918012740
Short name T104
Test name
Test status
Simulation time 2715084777 ps
CPU time 5.88 seconds
Started Dec 31 01:11:44 PM PST 23
Finished Dec 31 01:11:51 PM PST 23
Peak memory 216964 kb
Host smart-0f91ed7f-3498-4f8f-b70f-0a74822090e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918012740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_rx_timeout.3918012740
Directory /workspace/44.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/44.spi_device_smoke.2247878681
Short name T1619
Test name
Test status
Simulation time 41462092 ps
CPU time 1.07 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:26 PM PST 23
Peak memory 208404 kb
Host smart-d09348b8-5575-4487-8e5b-92ec3b175e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247878681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_smoke.2247878681
Directory /workspace/44.spi_device_smoke/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.619633653
Short name T990
Test name
Test status
Simulation time 3011849476 ps
CPU time 39.17 seconds
Started Dec 31 01:11:44 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 222492 kb
Host smart-9cec5d1f-1603-43ed-8faa-47542eb22d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619633653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.619633653
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2125669791
Short name T1180
Test name
Test status
Simulation time 2782377162 ps
CPU time 15.33 seconds
Started Dec 31 01:11:43 PM PST 23
Finished Dec 31 01:12:00 PM PST 23
Peak memory 216928 kb
Host smart-f9bd48a4-99c2-4e05-8832-e9638faf8111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125669791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2125669791
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.4200165085
Short name T1371
Test name
Test status
Simulation time 370820434 ps
CPU time 1.95 seconds
Started Dec 31 01:11:41 PM PST 23
Finished Dec 31 01:11:44 PM PST 23
Peak memory 216824 kb
Host smart-62aa808e-20f3-4ec9-b745-dd654037a2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200165085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.4200165085
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3929283560
Short name T734
Test name
Test status
Simulation time 226687989 ps
CPU time 0.85 seconds
Started Dec 31 01:12:07 PM PST 23
Finished Dec 31 01:12:10 PM PST 23
Peak memory 206860 kb
Host smart-a8b60d18-54d7-44d1-8434-91a43abe47f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929283560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3929283560
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_tx_async_fifo_reset.613625017
Short name T837
Test name
Test status
Simulation time 39426369 ps
CPU time 0.79 seconds
Started Dec 31 01:11:42 PM PST 23
Finished Dec 31 01:11:44 PM PST 23
Peak memory 208436 kb
Host smart-ef0759a9-3bb2-463d-b738-66630a13062d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613625017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tx_async_fifo_reset.613625017
Directory /workspace/44.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/44.spi_device_txrx.1403611686
Short name T1304
Test name
Test status
Simulation time 18784401384 ps
CPU time 404.14 seconds
Started Dec 31 01:12:16 PM PST 23
Finished Dec 31 01:19:04 PM PST 23
Peak memory 236444 kb
Host smart-b4469373-803b-4827-8922-032912a0c4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403611686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_txrx.1403611686
Directory /workspace/44.spi_device_txrx/latest

Test location /workspace/coverage/default/44.spi_device_upload.273445437
Short name T1315
Test name
Test status
Simulation time 10664008584 ps
CPU time 16.02 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:12:34 PM PST 23
Peak memory 230572 kb
Host smart-126e31eb-0a3c-4ff7-901a-49de1051bde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273445437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.273445437
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_abort.3831113547
Short name T1516
Test name
Test status
Simulation time 41886302 ps
CPU time 0.83 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:12:17 PM PST 23
Peak memory 206568 kb
Host smart-a282f110-8187-4e02-a1b0-4239af6f0db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831113547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_abort.3831113547
Directory /workspace/45.spi_device_abort/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.4150975696
Short name T591
Test name
Test status
Simulation time 12180795 ps
CPU time 0.69 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:12:18 PM PST 23
Peak memory 206448 kb
Host smart-a70fac1c-eccd-455f-8e2c-b62d8fb40f34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150975696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4150975696
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_bit_transfer.2649024418
Short name T535
Test name
Test status
Simulation time 75665191 ps
CPU time 1.96 seconds
Started Dec 31 01:11:56 PM PST 23
Finished Dec 31 01:11:59 PM PST 23
Peak memory 216740 kb
Host smart-be273d7f-ed3f-4a82-a014-9df471ad64f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649024418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_bit_transfer.2649024418
Directory /workspace/45.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/45.spi_device_byte_transfer.2638804253
Short name T1739
Test name
Test status
Simulation time 519542460 ps
CPU time 3.13 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:12:20 PM PST 23
Peak memory 216764 kb
Host smart-d923bed7-9ce9-43d5-bad5-6890006206b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638804253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_byte_transfer.2638804253
Directory /workspace/45.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2497990610
Short name T1360
Test name
Test status
Simulation time 171870241 ps
CPU time 3.72 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:12:22 PM PST 23
Peak memory 238132 kb
Host smart-35b04012-cf1d-4886-a2cd-d3e764223ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497990610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2497990610
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1913772054
Short name T1732
Test name
Test status
Simulation time 13954403 ps
CPU time 0.79 seconds
Started Dec 31 01:11:43 PM PST 23
Finished Dec 31 01:11:45 PM PST 23
Peak memory 207580 kb
Host smart-71af78db-b0a2-467e-beaf-5308760cf164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913772054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1913772054
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_dummy_item_extra_dly.3116134108
Short name T1532
Test name
Test status
Simulation time 61003435588 ps
CPU time 588.37 seconds
Started Dec 31 01:11:40 PM PST 23
Finished Dec 31 01:21:30 PM PST 23
Peak memory 249468 kb
Host smart-13597b33-47d0-480e-ac33-035d527cbf47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116134108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_dummy_item_extra_dly.3116134108
Directory /workspace/45.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/45.spi_device_extreme_fifo_size.2351181857
Short name T1281
Test name
Test status
Simulation time 57523527190 ps
CPU time 793.51 seconds
Started Dec 31 01:11:55 PM PST 23
Finished Dec 31 01:25:09 PM PST 23
Peak memory 218980 kb
Host smart-19a00aeb-05ac-4679-8068-94d7d4fa53ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351181857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_extreme_fifo_size.2351181857
Directory /workspace/45.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/45.spi_device_fifo_full.116895459
Short name T1487
Test name
Test status
Simulation time 156585602108 ps
CPU time 2214.82 seconds
Started Dec 31 01:12:13 PM PST 23
Finished Dec 31 01:49:10 PM PST 23
Peak memory 285468 kb
Host smart-0a5ec630-245b-4cc5-8ae1-c94c5abdf980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116895459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_fifo_full.116895459
Directory /workspace/45.spi_device_fifo_full/latest

Test location /workspace/coverage/default/45.spi_device_fifo_underflow_overflow.3189895601
Short name T1319
Test name
Test status
Simulation time 53394615623 ps
CPU time 260.2 seconds
Started Dec 31 01:12:13 PM PST 23
Finished Dec 31 01:16:35 PM PST 23
Peak memory 306844 kb
Host smart-f684c13d-6be0-4038-9f71-dc860b41283a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189895601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_fifo_underflow_overf
low.3189895601
Directory /workspace/45.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1369173437
Short name T309
Test name
Test status
Simulation time 162833291960 ps
CPU time 200 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:15:37 PM PST 23
Peak memory 247612 kb
Host smart-271744d2-2ab4-4216-9a33-1418771970bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369173437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1369173437
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3329568676
Short name T941
Test name
Test status
Simulation time 2350974889 ps
CPU time 20.52 seconds
Started Dec 31 01:12:05 PM PST 23
Finished Dec 31 01:12:26 PM PST 23
Peak memory 241544 kb
Host smart-c246560c-a063-45c3-addc-a236ab8be8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329568676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3329568676
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3023840515
Short name T318
Test name
Test status
Simulation time 7316733073 ps
CPU time 139.85 seconds
Started Dec 31 01:12:05 PM PST 23
Finished Dec 31 01:14:26 PM PST 23
Peak memory 267680 kb
Host smart-0d675885-ea4c-462d-b0c4-907a95fd5a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023840515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3023840515
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1094806196
Short name T686
Test name
Test status
Simulation time 642898608 ps
CPU time 6.03 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 219016 kb
Host smart-b141b48f-a4ca-4001-8b8a-4a32c8d49115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094806196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1094806196
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_intr.4268639859
Short name T1128
Test name
Test status
Simulation time 4296456650 ps
CPU time 18.08 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:12:36 PM PST 23
Peak memory 218128 kb
Host smart-88f579c8-35b5-4f61-88c0-a79694baf11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268639859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intr.4268639859
Directory /workspace/45.spi_device_intr/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2980751296
Short name T1527
Test name
Test status
Simulation time 7175958547 ps
CPU time 28.86 seconds
Started Dec 31 01:12:17 PM PST 23
Finished Dec 31 01:12:50 PM PST 23
Peak memory 257708 kb
Host smart-2065e3fd-14fd-4c0a-9a2a-dd3d78a06b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980751296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2980751296
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1554213589
Short name T204
Test name
Test status
Simulation time 17342800207 ps
CPU time 16.66 seconds
Started Dec 31 01:11:43 PM PST 23
Finished Dec 31 01:12:01 PM PST 23
Peak memory 237548 kb
Host smart-e936d89b-da0e-4124-bc0d-a7d6e244c132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554213589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1554213589
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2585605726
Short name T1278
Test name
Test status
Simulation time 613677771 ps
CPU time 6.05 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:12:23 PM PST 23
Peak memory 239944 kb
Host smart-61d68366-9cc3-4157-9062-f4f26af47080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585605726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2585605726
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_perf.3470644566
Short name T1558
Test name
Test status
Simulation time 33779397135 ps
CPU time 849.67 seconds
Started Dec 31 01:11:55 PM PST 23
Finished Dec 31 01:26:06 PM PST 23
Peak memory 273552 kb
Host smart-9ef82530-8143-403c-bbaf-261230431df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470644566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_perf.3470644566
Directory /workspace/45.spi_device_perf/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2817082181
Short name T1722
Test name
Test status
Simulation time 975383201 ps
CPU time 4.33 seconds
Started Dec 31 01:12:08 PM PST 23
Finished Dec 31 01:12:14 PM PST 23
Peak memory 234128 kb
Host smart-c9421d9d-e022-4092-97aa-c8314edb344a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2817082181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2817082181
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_rx_async_fifo_reset.4213361870
Short name T917
Test name
Test status
Simulation time 27266756 ps
CPU time 0.86 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:24 PM PST 23
Peak memory 208464 kb
Host smart-c40abeae-612d-427b-85b4-03aa972a206d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213361870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_rx_async_fifo_reset.4213361870
Directory /workspace/45.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/45.spi_device_rx_timeout.2042490532
Short name T1198
Test name
Test status
Simulation time 1782079938 ps
CPU time 7.04 seconds
Started Dec 31 01:11:55 PM PST 23
Finished Dec 31 01:12:02 PM PST 23
Peak memory 216728 kb
Host smart-383e1aaa-7a42-4c34-9426-725db82d1ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042490532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_rx_timeout.2042490532
Directory /workspace/45.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/45.spi_device_smoke.575944156
Short name T661
Test name
Test status
Simulation time 47684528 ps
CPU time 0.86 seconds
Started Dec 31 01:11:55 PM PST 23
Finished Dec 31 01:11:56 PM PST 23
Peak memory 207860 kb
Host smart-e86033ea-e5fd-42d8-9ac0-ef521bfc6fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575944156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_smoke.575944156
Directory /workspace/45.spi_device_smoke/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.113042350
Short name T16
Test name
Test status
Simulation time 30262695766 ps
CPU time 606.23 seconds
Started Dec 31 01:12:05 PM PST 23
Finished Dec 31 01:22:13 PM PST 23
Peak memory 332572 kb
Host smart-bba73f18-5098-4794-a714-52d0e9b0c760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113042350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.113042350
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3191937644
Short name T13
Test name
Test status
Simulation time 9200088609 ps
CPU time 11.13 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:35 PM PST 23
Peak memory 217212 kb
Host smart-3143f0a7-40d5-46ce-b5c5-a27539f8d789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191937644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3191937644
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2496649427
Short name T1043
Test name
Test status
Simulation time 7226639543 ps
CPU time 6.43 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:12:34 PM PST 23
Peak memory 216844 kb
Host smart-fc42d9f6-8804-4550-b6af-a65e3b670011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496649427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2496649427
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3966723370
Short name T822
Test name
Test status
Simulation time 98434639 ps
CPU time 1.09 seconds
Started Dec 31 01:12:05 PM PST 23
Finished Dec 31 01:12:07 PM PST 23
Peak memory 208332 kb
Host smart-a5e1df28-31e8-456d-a4e7-3d790ef8e0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966723370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3966723370
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.339632356
Short name T908
Test name
Test status
Simulation time 183602698 ps
CPU time 0.95 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:12:18 PM PST 23
Peak memory 207068 kb
Host smart-cbca13a9-e116-4025-b547-ac04f36a75e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339632356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.339632356
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_tx_async_fifo_reset.1073291176
Short name T37
Test name
Test status
Simulation time 88513057 ps
CPU time 0.77 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 208452 kb
Host smart-618c0caa-4a92-4c9d-9ac2-a4e974948cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073291176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tx_async_fifo_reset.1073291176
Directory /workspace/45.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/45.spi_device_txrx.793110827
Short name T494
Test name
Test status
Simulation time 255352768100 ps
CPU time 537.28 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:21:14 PM PST 23
Peak memory 281860 kb
Host smart-0c8af163-8d71-403e-b81b-554f81c6bb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793110827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_txrx.793110827
Directory /workspace/45.spi_device_txrx/latest

Test location /workspace/coverage/default/45.spi_device_upload.2819628511
Short name T1591
Test name
Test status
Simulation time 190088139 ps
CPU time 3.88 seconds
Started Dec 31 01:12:16 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 218952 kb
Host smart-9bc51930-d785-48d1-8499-872f650fe56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819628511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2819628511
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_abort.86815902
Short name T1166
Test name
Test status
Simulation time 23956020 ps
CPU time 0.79 seconds
Started Dec 31 01:12:23 PM PST 23
Finished Dec 31 01:12:30 PM PST 23
Peak memory 206560 kb
Host smart-38aab504-2932-41cc-9d41-dbca22e6cb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86815902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_abort.86815902
Directory /workspace/46.spi_device_abort/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3544858005
Short name T501
Test name
Test status
Simulation time 65111536 ps
CPU time 0.71 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:24 PM PST 23
Peak memory 206424 kb
Host smart-f4c98939-4b95-4f0b-92b6-35db558f7a1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544858005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3544858005
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_bit_transfer.3559061798
Short name T948
Test name
Test status
Simulation time 190413166 ps
CPU time 1.89 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:27 PM PST 23
Peak memory 216828 kb
Host smart-dfbffce7-551b-4114-9b9b-fb62a3b7909a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559061798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_bit_transfer.3559061798
Directory /workspace/46.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/46.spi_device_byte_transfer.2652250875
Short name T1167
Test name
Test status
Simulation time 415045707 ps
CPU time 2.52 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 216820 kb
Host smart-360da22f-9e25-487b-ae5a-b8a85076d523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652250875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_byte_transfer.2652250875
Directory /workspace/46.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3524551451
Short name T262
Test name
Test status
Simulation time 9518014618 ps
CPU time 7.17 seconds
Started Dec 31 01:12:13 PM PST 23
Finished Dec 31 01:12:21 PM PST 23
Peak memory 221624 kb
Host smart-fad6a019-3eb8-4f06-b46c-32ba1775462d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524551451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3524551451
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3299023099
Short name T499
Test name
Test status
Simulation time 20470319 ps
CPU time 0.76 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:27 PM PST 23
Peak memory 206804 kb
Host smart-dc2ff6f6-3661-4bea-86b5-050564e0ac63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299023099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3299023099
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_dummy_item_extra_dly.4048431495
Short name T448
Test name
Test status
Simulation time 321954944322 ps
CPU time 502.6 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:20:40 PM PST 23
Peak memory 241432 kb
Host smart-11719f1c-7f34-4972-88dd-b34a0b0cc573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048431495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_dummy_item_extra_dly.4048431495
Directory /workspace/46.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/46.spi_device_extreme_fifo_size.1220393520
Short name T1579
Test name
Test status
Simulation time 15939160216 ps
CPU time 33.65 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:12:51 PM PST 23
Peak memory 220036 kb
Host smart-e1827577-7bb9-4893-a97c-ea123772d419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220393520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_extreme_fifo_size.1220393520
Directory /workspace/46.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/46.spi_device_fifo_full.2025695794
Short name T564
Test name
Test status
Simulation time 42135701007 ps
CPU time 2505.74 seconds
Started Dec 31 01:12:17 PM PST 23
Finished Dec 31 01:54:07 PM PST 23
Peak memory 270976 kb
Host smart-68729c65-0a5d-4089-9d7e-2ad7d2963115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025695794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_fifo_full.2025695794
Directory /workspace/46.spi_device_fifo_full/latest

Test location /workspace/coverage/default/46.spi_device_fifo_underflow_overflow.177340153
Short name T658
Test name
Test status
Simulation time 317241321450 ps
CPU time 950.81 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:28:18 PM PST 23
Peak memory 565588 kb
Host smart-1b681272-997a-4144-96ed-615770149626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177340153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_fifo_underflow_overfl
ow.177340153
Directory /workspace/46.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2117121943
Short name T175
Test name
Test status
Simulation time 4476586114 ps
CPU time 61.49 seconds
Started Dec 31 01:12:13 PM PST 23
Finished Dec 31 01:13:16 PM PST 23
Peak memory 267620 kb
Host smart-8e098bf3-7fad-4ced-897b-3b725ed6862c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117121943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2117121943
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1721967708
Short name T1596
Test name
Test status
Simulation time 23035839197 ps
CPU time 197.97 seconds
Started Dec 31 01:12:06 PM PST 23
Finished Dec 31 01:15:26 PM PST 23
Peak memory 257888 kb
Host smart-140d26fe-12a0-4761-a6eb-dffcd8f294e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721967708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1721967708
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3747179125
Short name T1294
Test name
Test status
Simulation time 43874348692 ps
CPU time 302.71 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 01:17:25 PM PST 23
Peak memory 254856 kb
Host smart-2c2c2501-fbe0-4e2d-9dfd-dbafa220cb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747179125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3747179125
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3817286551
Short name T559
Test name
Test status
Simulation time 8645802613 ps
CPU time 17.82 seconds
Started Dec 31 01:12:07 PM PST 23
Finished Dec 31 01:12:27 PM PST 23
Peak memory 255588 kb
Host smart-3d2480df-01ec-4cca-b88a-0f0dfb7d0e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817286551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3817286551
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2262226428
Short name T1674
Test name
Test status
Simulation time 3987998408 ps
CPU time 13.3 seconds
Started Dec 31 01:12:31 PM PST 23
Finished Dec 31 01:12:49 PM PST 23
Peak memory 225056 kb
Host smart-36b979ae-749c-4659-bf14-255a1d0e4208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262226428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2262226428
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_intr.373019172
Short name T1136
Test name
Test status
Simulation time 6318526158 ps
CPU time 29.86 seconds
Started Dec 31 01:12:13 PM PST 23
Finished Dec 31 01:12:45 PM PST 23
Peak memory 225176 kb
Host smart-50cc9c17-eab4-460c-becc-c90373571846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373019172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intr.373019172
Directory /workspace/46.spi_device_intr/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1096008805
Short name T10
Test name
Test status
Simulation time 794482874 ps
CPU time 10.33 seconds
Started Dec 31 01:12:22 PM PST 23
Finished Dec 31 01:12:39 PM PST 23
Peak memory 248256 kb
Host smart-24448668-8dea-4e10-9851-3127bd7c9b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096008805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1096008805
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1255230654
Short name T1670
Test name
Test status
Simulation time 8267192263 ps
CPU time 24.07 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:12:55 PM PST 23
Peak memory 225600 kb
Host smart-5581a8ba-665d-4956-99e3-1f2e637b20b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255230654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1255230654
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2302428456
Short name T824
Test name
Test status
Simulation time 5045221825 ps
CPU time 4.35 seconds
Started Dec 31 01:12:25 PM PST 23
Finished Dec 31 01:12:36 PM PST 23
Peak memory 218652 kb
Host smart-e1814de1-d47f-40c3-a0eb-0895ccda0187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302428456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2302428456
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_perf.2259418093
Short name T1307
Test name
Test status
Simulation time 20494958538 ps
CPU time 436.67 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:19:48 PM PST 23
Peak memory 284584 kb
Host smart-069d254e-3b66-4134-bea6-999d9590156c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259418093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_perf.2259418093
Directory /workspace/46.spi_device_perf/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2595639368
Short name T28
Test name
Test status
Simulation time 603331073 ps
CPU time 5.87 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 01:12:28 PM PST 23
Peak memory 234264 kb
Host smart-4e36c8ed-066b-407f-9790-5cbf57116c24
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2595639368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2595639368
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_rx_async_fifo_reset.3520241363
Short name T1352
Test name
Test status
Simulation time 116887611 ps
CPU time 0.88 seconds
Started Dec 31 01:12:23 PM PST 23
Finished Dec 31 01:12:31 PM PST 23
Peak memory 208412 kb
Host smart-36e701d5-f1d9-4f81-847c-7d2990b752ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520241363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_rx_async_fifo_reset.3520241363
Directory /workspace/46.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/46.spi_device_rx_timeout.1519249400
Short name T1306
Test name
Test status
Simulation time 478080530 ps
CPU time 4.44 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:12:35 PM PST 23
Peak memory 216756 kb
Host smart-9a766b44-0e29-4e7e-bb0b-c0be6ac03bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519249400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_rx_timeout.1519249400
Directory /workspace/46.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/46.spi_device_smoke.1006933
Short name T1059
Test name
Test status
Simulation time 37719062 ps
CPU time 1.17 seconds
Started Dec 31 01:11:55 PM PST 23
Finished Dec 31 01:11:57 PM PST 23
Peak memory 216768 kb
Host smart-e1ad29f4-6b58-498a-91e9-900b2eab23a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_smoke.1006933
Directory /workspace/46.spi_device_smoke/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1841341629
Short name T183
Test name
Test status
Simulation time 271117449096 ps
CPU time 6359.11 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 02:58:22 PM PST 23
Peak memory 738940 kb
Host smart-20972dbc-e2f6-4413-909b-b7b99dc67406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841341629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1841341629
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2010396294
Short name T328
Test name
Test status
Simulation time 6473941609 ps
CPU time 21.98 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:46 PM PST 23
Peak memory 216920 kb
Host smart-72ee2abc-4089-4f11-9b36-aaace8402ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010396294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2010396294
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.775448046
Short name T813
Test name
Test status
Simulation time 7855697777 ps
CPU time 7.33 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:33 PM PST 23
Peak memory 216888 kb
Host smart-5807a6bb-4c85-4008-bc0c-ccc4601bc245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775448046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.775448046
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1289007621
Short name T1200
Test name
Test status
Simulation time 1344170567 ps
CPU time 7.64 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:12:34 PM PST 23
Peak memory 216788 kb
Host smart-e9e694e9-3a16-43db-b563-3e8307829dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289007621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1289007621
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.837338622
Short name T616
Test name
Test status
Simulation time 139821319 ps
CPU time 0.85 seconds
Started Dec 31 01:12:22 PM PST 23
Finished Dec 31 01:12:29 PM PST 23
Peak memory 206836 kb
Host smart-93527043-f485-4d7f-a5cf-67d21f2cfb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837338622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.837338622
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_tx_async_fifo_reset.909958046
Short name T124
Test name
Test status
Simulation time 34816011 ps
CPU time 0.79 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:24 PM PST 23
Peak memory 208504 kb
Host smart-b9a911dd-7283-4d0f-9f5f-82ee4f3e8723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909958046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tx_async_fifo_reset.909958046
Directory /workspace/46.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/46.spi_device_txrx.1180919171
Short name T1507
Test name
Test status
Simulation time 61984008888 ps
CPU time 400.9 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:19:09 PM PST 23
Peak memory 289836 kb
Host smart-e3422fef-b624-4c1f-bb62-67e1b09c3966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180919171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_txrx.1180919171
Directory /workspace/46.spi_device_txrx/latest

Test location /workspace/coverage/default/46.spi_device_upload.3241445499
Short name T1157
Test name
Test status
Simulation time 349696545 ps
CPU time 5.41 seconds
Started Dec 31 01:12:31 PM PST 23
Finished Dec 31 01:12:42 PM PST 23
Peak memory 233204 kb
Host smart-028664d1-fbb7-4f16-88be-9f3d1c37caab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241445499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3241445499
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_abort.1909039337
Short name T964
Test name
Test status
Simulation time 26239927 ps
CPU time 0.72 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 206628 kb
Host smart-6fd1d5e3-5e86-4259-a895-22887ce014b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909039337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_abort.1909039337
Directory /workspace/47.spi_device_abort/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3256224605
Short name T449
Test name
Test status
Simulation time 34432359 ps
CPU time 0.71 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:26 PM PST 23
Peak memory 206480 kb
Host smart-618d7173-557e-47f3-b8d2-d77673182ea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256224605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3256224605
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_bit_transfer.2225718646
Short name T1130
Test name
Test status
Simulation time 1265256513 ps
CPU time 2.74 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:29 PM PST 23
Peak memory 216752 kb
Host smart-b95dd87b-44a0-45ee-9472-c02671cd7c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225718646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_bit_transfer.2225718646
Directory /workspace/47.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/47.spi_device_byte_transfer.4018311132
Short name T468
Test name
Test status
Simulation time 933972558 ps
CPU time 3.43 seconds
Started Dec 31 01:12:05 PM PST 23
Finished Dec 31 01:12:10 PM PST 23
Peak memory 216888 kb
Host smart-8ddda7da-b62c-450a-a874-014fb42135bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018311132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_byte_transfer.4018311132
Directory /workspace/47.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1985952414
Short name T1349
Test name
Test status
Simulation time 1683828431 ps
CPU time 7.78 seconds
Started Dec 31 01:12:16 PM PST 23
Finished Dec 31 01:12:28 PM PST 23
Peak memory 239584 kb
Host smart-8f58c564-024f-496d-a124-7e37ff74f470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985952414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1985952414
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1416880252
Short name T1085
Test name
Test status
Simulation time 27403289 ps
CPU time 0.78 seconds
Started Dec 31 01:12:08 PM PST 23
Finished Dec 31 01:12:10 PM PST 23
Peak memory 207620 kb
Host smart-cb7988db-b19a-44b3-9473-3d8b12b0001d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416880252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1416880252
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_dummy_item_extra_dly.3911680712
Short name T643
Test name
Test status
Simulation time 33263201937 ps
CPU time 260.16 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:16:36 PM PST 23
Peak memory 267104 kb
Host smart-0a86dcce-ffdb-469b-9f04-091743af8880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911680712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_dummy_item_extra_dly.3911680712
Directory /workspace/47.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/47.spi_device_extreme_fifo_size.1612324132
Short name T976
Test name
Test status
Simulation time 37745932224 ps
CPU time 63.85 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:13:21 PM PST 23
Peak memory 239004 kb
Host smart-fec17095-69dd-4e9b-b217-c19747a08721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612324132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_extreme_fifo_size.1612324132
Directory /workspace/47.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/47.spi_device_fifo_full.3662993087
Short name T1574
Test name
Test status
Simulation time 43917780505 ps
CPU time 2392.33 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:52:18 PM PST 23
Peak memory 304860 kb
Host smart-ffb86852-3f37-413f-8a57-f88e6f8f91af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662993087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_fifo_full.3662993087
Directory /workspace/47.spi_device_fifo_full/latest

Test location /workspace/coverage/default/47.spi_device_fifo_underflow_overflow.2579025162
Short name T486
Test name
Test status
Simulation time 5924831280 ps
CPU time 66.69 seconds
Started Dec 31 01:12:05 PM PST 23
Finished Dec 31 01:13:13 PM PST 23
Peak memory 274308 kb
Host smart-c630647a-0b20-42e7-9af8-721f499d9e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579025162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_fifo_underflow_overf
low.2579025162
Directory /workspace/47.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.771946405
Short name T743
Test name
Test status
Simulation time 3086615352 ps
CPU time 25.84 seconds
Started Dec 31 01:12:09 PM PST 23
Finished Dec 31 01:12:36 PM PST 23
Peak memory 241596 kb
Host smart-2205f9b0-70e6-4095-8ee4-04685c596f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771946405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.771946405
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.907350096
Short name T1233
Test name
Test status
Simulation time 39850107960 ps
CPU time 74.64 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 01:13:37 PM PST 23
Peak memory 239028 kb
Host smart-d85cbf56-d5bb-4329-9ba9-d3484a3fd19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907350096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.907350096
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.4093215248
Short name T246
Test name
Test status
Simulation time 2409915892 ps
CPU time 16.82 seconds
Started Dec 31 01:12:13 PM PST 23
Finished Dec 31 01:12:31 PM PST 23
Peak memory 249476 kb
Host smart-fd0d1241-1a90-4ffa-b5eb-686a62cf3f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093215248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.4093215248
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2146347191
Short name T1688
Test name
Test status
Simulation time 5162387078 ps
CPU time 6.65 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:30 PM PST 23
Peak memory 241552 kb
Host smart-615a9faa-22cd-4b52-b141-67be631d27b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146347191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2146347191
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_intr.1145682527
Short name T1123
Test name
Test status
Simulation time 7468939142 ps
CPU time 13.78 seconds
Started Dec 31 01:12:04 PM PST 23
Finished Dec 31 01:12:19 PM PST 23
Peak memory 218244 kb
Host smart-3f44b56f-457b-4721-b164-c07dcc7ba33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145682527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intr.1145682527
Directory /workspace/47.spi_device_intr/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2713604800
Short name T906
Test name
Test status
Simulation time 36175395172 ps
CPU time 60.33 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 01:13:23 PM PST 23
Peak memory 241196 kb
Host smart-71b84c84-136b-4e14-ba8c-84e517d55cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713604800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2713604800
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.617103617
Short name T1745
Test name
Test status
Simulation time 32255792503 ps
CPU time 24.46 seconds
Started Dec 31 01:12:08 PM PST 23
Finished Dec 31 01:12:34 PM PST 23
Peak memory 230996 kb
Host smart-501932dc-324e-44ab-be6e-fbfa30c7c69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617103617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.617103617
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1491810853
Short name T275
Test name
Test status
Simulation time 10362313253 ps
CPU time 8.43 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 230328 kb
Host smart-ae33b663-d16c-4c44-83f5-d4c3fecfcab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491810853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1491810853
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_perf.2985260645
Short name T48
Test name
Test status
Simulation time 75395656204 ps
CPU time 372.67 seconds
Started Dec 31 01:12:06 PM PST 23
Finished Dec 31 01:18:21 PM PST 23
Peak memory 249736 kb
Host smart-a060e564-5ea4-4467-91fd-815ca337eb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985260645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_perf.2985260645
Directory /workspace/47.spi_device_perf/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.908130321
Short name T631
Test name
Test status
Simulation time 430533117 ps
CPU time 4.63 seconds
Started Dec 31 01:12:07 PM PST 23
Finished Dec 31 01:12:14 PM PST 23
Peak memory 234372 kb
Host smart-d52b6b23-548b-4da2-8cbd-54a01b9b27d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=908130321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.908130321
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_rx_async_fifo_reset.4267481877
Short name T735
Test name
Test status
Simulation time 23860132 ps
CPU time 0.88 seconds
Started Dec 31 01:12:04 PM PST 23
Finished Dec 31 01:12:06 PM PST 23
Peak memory 208512 kb
Host smart-d3ee2e5f-8526-47a9-a328-1d0beac46523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267481877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_rx_async_fifo_reset.4267481877
Directory /workspace/47.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/47.spi_device_rx_timeout.4010502787
Short name T971
Test name
Test status
Simulation time 3305302222 ps
CPU time 5.49 seconds
Started Dec 31 01:12:07 PM PST 23
Finished Dec 31 01:12:14 PM PST 23
Peak memory 216952 kb
Host smart-864cead0-78d5-40cf-8416-052ff2e036b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010502787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_rx_timeout.4010502787
Directory /workspace/47.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/47.spi_device_smoke.3803322491
Short name T481
Test name
Test status
Simulation time 53150878 ps
CPU time 1.15 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 01:12:24 PM PST 23
Peak memory 216596 kb
Host smart-8a193c73-8764-4f3a-8bec-538679d1a118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803322491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_smoke.3803322491
Directory /workspace/47.spi_device_smoke/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1940736003
Short name T238
Test name
Test status
Simulation time 329144868425 ps
CPU time 571.63 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:21:56 PM PST 23
Peak memory 537844 kb
Host smart-864d789e-938b-44df-a3c9-96b200eb95fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940736003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1940736003
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3398258631
Short name T95
Test name
Test status
Simulation time 11153412773 ps
CPU time 182.97 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 01:15:25 PM PST 23
Peak memory 216896 kb
Host smart-d03af033-173e-4a6d-a8e6-5978832834e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398258631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3398258631
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3701703057
Short name T737
Test name
Test status
Simulation time 1779881181 ps
CPU time 4.67 seconds
Started Dec 31 01:12:08 PM PST 23
Finished Dec 31 01:12:14 PM PST 23
Peak memory 216816 kb
Host smart-7b41781d-f8ef-4a48-9baf-abd4496a607b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701703057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3701703057
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2954417898
Short name T1528
Test name
Test status
Simulation time 417538192 ps
CPU time 1.63 seconds
Started Dec 31 01:12:12 PM PST 23
Finished Dec 31 01:12:15 PM PST 23
Peak memory 216864 kb
Host smart-3a759ec3-8f94-4b2f-8319-efc73d4f4af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954417898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2954417898
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1404848027
Short name T576
Test name
Test status
Simulation time 90240879 ps
CPU time 0.72 seconds
Started Dec 31 01:12:16 PM PST 23
Finished Dec 31 01:12:21 PM PST 23
Peak memory 206772 kb
Host smart-5b974f08-1732-4136-b671-281e9a5da2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404848027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1404848027
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_tx_async_fifo_reset.1304013842
Short name T609
Test name
Test status
Simulation time 181693659 ps
CPU time 0.77 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:27 PM PST 23
Peak memory 208404 kb
Host smart-0aede851-71e0-424c-a5db-99c2757e1aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304013842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tx_async_fifo_reset.1304013842
Directory /workspace/47.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/47.spi_device_txrx.1865207776
Short name T1176
Test name
Test status
Simulation time 65112664988 ps
CPU time 252.86 seconds
Started Dec 31 01:12:05 PM PST 23
Finished Dec 31 01:16:19 PM PST 23
Peak memory 285584 kb
Host smart-c3b12483-8fc1-4996-bb26-db2660ed79a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865207776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_txrx.1865207776
Directory /workspace/47.spi_device_txrx/latest

Test location /workspace/coverage/default/47.spi_device_upload.271450810
Short name T507
Test name
Test status
Simulation time 902256717 ps
CPU time 3.76 seconds
Started Dec 31 01:12:17 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 226096 kb
Host smart-66bcc907-924c-40d0-a4e9-ba64b98c50cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271450810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.271450810
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_abort.1536339998
Short name T1565
Test name
Test status
Simulation time 14946912 ps
CPU time 0.74 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 206648 kb
Host smart-147774db-2c61-4fc9-b08f-9b5ef5f25eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536339998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_abort.1536339998
Directory /workspace/48.spi_device_abort/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.523496234
Short name T1178
Test name
Test status
Simulation time 12467878 ps
CPU time 0.72 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 01:12:23 PM PST 23
Peak memory 206476 kb
Host smart-cf0dda5a-3b30-412c-846b-26b80593b22c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523496234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.523496234
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_bit_transfer.3438621157
Short name T678
Test name
Test status
Simulation time 95549096 ps
CPU time 2.82 seconds
Started Dec 31 01:12:12 PM PST 23
Finished Dec 31 01:12:17 PM PST 23
Peak memory 216736 kb
Host smart-8caabfc1-c997-45ce-948a-c226f3516d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438621157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_bit_transfer.3438621157
Directory /workspace/48.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/48.spi_device_byte_transfer.3757094670
Short name T543
Test name
Test status
Simulation time 248470886 ps
CPU time 2.9 seconds
Started Dec 31 01:12:05 PM PST 23
Finished Dec 31 01:12:09 PM PST 23
Peak memory 216812 kb
Host smart-a761e8de-43de-4cad-a8de-ac1c9167d5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757094670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_byte_transfer.3757094670
Directory /workspace/48.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.623059653
Short name T1000
Test name
Test status
Simulation time 185523772 ps
CPU time 2.3 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:29 PM PST 23
Peak memory 218680 kb
Host smart-dddd6bc8-3f16-4c13-a3c7-8963a04ee490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623059653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.623059653
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2983158601
Short name T1073
Test name
Test status
Simulation time 15074661 ps
CPU time 0.75 seconds
Started Dec 31 01:12:13 PM PST 23
Finished Dec 31 01:12:16 PM PST 23
Peak memory 206500 kb
Host smart-170de623-182e-49be-8d8d-ef6f6690c2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983158601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2983158601
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_dummy_item_extra_dly.120764703
Short name T1363
Test name
Test status
Simulation time 113813234439 ps
CPU time 476.58 seconds
Started Dec 31 01:12:22 PM PST 23
Finished Dec 31 01:20:25 PM PST 23
Peak memory 274368 kb
Host smart-55e67f78-be57-4299-b050-2c3c8bd169a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120764703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_dummy_item_extra_dly.120764703
Directory /workspace/48.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/48.spi_device_extreme_fifo_size.2378191636
Short name T668
Test name
Test status
Simulation time 69554771799 ps
CPU time 408.15 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:19:12 PM PST 23
Peak memory 219484 kb
Host smart-e3d8e47c-b47a-44c5-aaf6-ef905ce4e290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378191636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_extreme_fifo_size.2378191636
Directory /workspace/48.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/48.spi_device_fifo_full.656018929
Short name T505
Test name
Test status
Simulation time 24675024668 ps
CPU time 448.67 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:19:45 PM PST 23
Peak memory 298116 kb
Host smart-22a441e3-445a-4ffb-923b-746fe8392152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656018929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_fifo_full.656018929
Directory /workspace/48.spi_device_fifo_full/latest

Test location /workspace/coverage/default/48.spi_device_fifo_underflow_overflow.354283952
Short name T1332
Test name
Test status
Simulation time 70907978764 ps
CPU time 280.2 seconds
Started Dec 31 01:12:16 PM PST 23
Finished Dec 31 01:17:01 PM PST 23
Peak memory 340792 kb
Host smart-796ecb9d-833e-47bd-a2ff-6ba69ed33f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354283952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_fifo_underflow_overfl
ow.354283952
Directory /workspace/48.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.108743007
Short name T296
Test name
Test status
Simulation time 64285555530 ps
CPU time 290.98 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:17:08 PM PST 23
Peak memory 265248 kb
Host smart-945238c3-6ae5-4688-8496-fb7e27b948af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108743007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.108743007
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.792475070
Short name T1137
Test name
Test status
Simulation time 15211129459 ps
CPU time 89.53 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:13:55 PM PST 23
Peak memory 256940 kb
Host smart-017925fe-8fb6-4619-912a-03ddcd3ff168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792475070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.792475070
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3197853861
Short name T1560
Test name
Test status
Simulation time 98728687424 ps
CPU time 232.63 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:16:18 PM PST 23
Peak memory 257980 kb
Host smart-9623757f-2e65-468f-8d9b-8138b4689df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197853861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3197853861
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2198427937
Short name T760
Test name
Test status
Simulation time 1072864520 ps
CPU time 9.49 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 01:12:33 PM PST 23
Peak memory 257164 kb
Host smart-2a39b46b-0124-4178-a278-026fce9a6c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198427937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2198427937
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2042425375
Short name T85
Test name
Test status
Simulation time 1952370810 ps
CPU time 5.03 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:12:32 PM PST 23
Peak memory 241392 kb
Host smart-9faee429-dc21-44db-affd-9819b6a319b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042425375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2042425375
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_intr.4288467718
Short name T640
Test name
Test status
Simulation time 19565666486 ps
CPU time 73.88 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:13:29 PM PST 23
Peak memory 233340 kb
Host smart-7eb8f90a-0fae-4bf3-91f1-a13e46600d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288467718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intr.4288467718
Directory /workspace/48.spi_device_intr/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.358441103
Short name T1513
Test name
Test status
Simulation time 16272588152 ps
CPU time 33.27 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:12:49 PM PST 23
Peak memory 234912 kb
Host smart-c25eab55-af07-4d8a-85fd-09491f56b42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358441103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.358441103
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.397421961
Short name T1115
Test name
Test status
Simulation time 6679567109 ps
CPU time 12.96 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 01:12:35 PM PST 23
Peak memory 240424 kb
Host smart-c18bf3b4-e4b3-4776-991e-3b638b503560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397421961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.397421961
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1488589624
Short name T264
Test name
Test status
Simulation time 23232710293 ps
CPU time 33.4 seconds
Started Dec 31 01:12:22 PM PST 23
Finished Dec 31 01:13:02 PM PST 23
Peak memory 233272 kb
Host smart-0978b42a-a891-4124-9e8d-591c3c40259a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488589624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1488589624
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_perf.1465225823
Short name T1611
Test name
Test status
Simulation time 42095174679 ps
CPU time 720.46 seconds
Started Dec 31 01:12:04 PM PST 23
Finished Dec 31 01:24:05 PM PST 23
Peak memory 272032 kb
Host smart-4ca21f74-c16f-4bb8-b2f1-ed28a421d623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465225823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_perf.1465225823
Directory /workspace/48.spi_device_perf/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3874037109
Short name T1760
Test name
Test status
Simulation time 1628488497 ps
CPU time 4.57 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:28 PM PST 23
Peak memory 218736 kb
Host smart-a11ea0ff-0303-474c-bcb4-f271faa54c14
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3874037109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3874037109
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_rx_async_fifo_reset.231398419
Short name T1068
Test name
Test status
Simulation time 28664371 ps
CPU time 0.88 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:12:18 PM PST 23
Peak memory 208472 kb
Host smart-88619b48-675a-4acb-aa9a-0149c90ea3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231398419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_rx_async_fifo_reset.231398419
Directory /workspace/48.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/48.spi_device_rx_timeout.371337155
Short name T1647
Test name
Test status
Simulation time 3099619298 ps
CPU time 6.85 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:12:34 PM PST 23
Peak memory 216880 kb
Host smart-6e4956f7-8f0c-4eda-b8a0-bef12460f60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371337155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_rx_timeout.371337155
Directory /workspace/48.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/48.spi_device_smoke.1663668253
Short name T1503
Test name
Test status
Simulation time 137011323 ps
CPU time 1.03 seconds
Started Dec 31 01:12:16 PM PST 23
Finished Dec 31 01:12:20 PM PST 23
Peak memory 208232 kb
Host smart-30f58aa3-9b63-45cd-9e7c-c3ada6ab85be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663668253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_smoke.1663668253
Directory /workspace/48.spi_device_smoke/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.470580900
Short name T1716
Test name
Test status
Simulation time 497124933271 ps
CPU time 663.04 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 01:23:25 PM PST 23
Peak memory 339096 kb
Host smart-a37735b6-0400-4c63-83d2-9937035bef76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470580900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.470580900
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3080448241
Short name T1104
Test name
Test status
Simulation time 8889223024 ps
CPU time 68.52 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:13:32 PM PST 23
Peak memory 217240 kb
Host smart-6ac95cd0-571a-4a87-8b7e-f88579534fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080448241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3080448241
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1760509250
Short name T550
Test name
Test status
Simulation time 285287339 ps
CPU time 1.17 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:12:19 PM PST 23
Peak memory 207944 kb
Host smart-85ca198b-29c7-4834-b136-f88136d28b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760509250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1760509250
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3064889644
Short name T890
Test name
Test status
Simulation time 14971493 ps
CPU time 0.92 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:12:29 PM PST 23
Peak memory 207912 kb
Host smart-1577540c-2be9-4ecb-8918-84b3c7bde364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064889644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3064889644
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3825456184
Short name T1765
Test name
Test status
Simulation time 135522396 ps
CPU time 1.01 seconds
Started Dec 31 01:12:08 PM PST 23
Finished Dec 31 01:12:10 PM PST 23
Peak memory 208020 kb
Host smart-9c43de10-244c-4dd5-8061-d571b5f98707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825456184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3825456184
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_tx_async_fifo_reset.3989205828
Short name T1215
Test name
Test status
Simulation time 16452902 ps
CPU time 0.79 seconds
Started Dec 31 01:12:17 PM PST 23
Finished Dec 31 01:12:22 PM PST 23
Peak memory 208420 kb
Host smart-d22a77c7-a817-449e-9f63-394964bb3d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989205828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tx_async_fifo_reset.3989205828
Directory /workspace/48.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/48.spi_device_txrx.4263541402
Short name T961
Test name
Test status
Simulation time 54451819188 ps
CPU time 211 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:15:48 PM PST 23
Peak memory 292636 kb
Host smart-665aedd4-8dc1-40d8-b06a-ab637478a195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263541402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_txrx.4263541402
Directory /workspace/48.spi_device_txrx/latest

Test location /workspace/coverage/default/48.spi_device_upload.869765510
Short name T274
Test name
Test status
Simulation time 33924683227 ps
CPU time 33.11 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:57 PM PST 23
Peak memory 245612 kb
Host smart-76b6c1c2-c93b-49f6-8bcb-b5072da3fe20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869765510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.869765510
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_abort.438394542
Short name T911
Test name
Test status
Simulation time 14013099 ps
CPU time 0.77 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:27 PM PST 23
Peak memory 206624 kb
Host smart-e093bf01-b786-4d0b-95bd-afab99b31692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438394542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_abort.438394542
Directory /workspace/49.spi_device_abort/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1609276926
Short name T1274
Test name
Test status
Simulation time 11071710 ps
CPU time 0.72 seconds
Started Dec 31 01:12:31 PM PST 23
Finished Dec 31 01:12:37 PM PST 23
Peak memory 206476 kb
Host smart-ef6b1a74-69e0-45ef-992a-c08a471f18d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609276926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1609276926
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_bit_transfer.2237293048
Short name T933
Test name
Test status
Simulation time 446120490 ps
CPU time 2.81 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:12:21 PM PST 23
Peak memory 216776 kb
Host smart-93a8e787-7404-4ccd-bedf-063c2032ab69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237293048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_bit_transfer.2237293048
Directory /workspace/49.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/49.spi_device_byte_transfer.2391594913
Short name T480
Test name
Test status
Simulation time 271509123 ps
CPU time 3.33 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:27 PM PST 23
Peak memory 216856 kb
Host smart-b977c92c-d8a5-4a66-891f-8c826ecc495a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391594913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_byte_transfer.2391594913
Directory /workspace/49.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.451534981
Short name T293
Test name
Test status
Simulation time 2313274503 ps
CPU time 5.93 seconds
Started Dec 31 01:12:22 PM PST 23
Finished Dec 31 01:12:34 PM PST 23
Peak memory 220604 kb
Host smart-f24e1054-81e6-4a34-ba06-8335f4a57f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451534981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.451534981
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3777124845
Short name T608
Test name
Test status
Simulation time 75840546 ps
CPU time 0.85 seconds
Started Dec 31 01:12:13 PM PST 23
Finished Dec 31 01:12:16 PM PST 23
Peak memory 207524 kb
Host smart-b6c86568-eaf6-4ed4-b73c-c8ae2ae79ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777124845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3777124845
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_dummy_item_extra_dly.2575596789
Short name T1571
Test name
Test status
Simulation time 212731046802 ps
CPU time 1047.37 seconds
Started Dec 31 01:12:17 PM PST 23
Finished Dec 31 01:29:49 PM PST 23
Peak memory 272408 kb
Host smart-5af67f00-40c3-47f0-9185-96bd00e1a6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575596789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_dummy_item_extra_dly.2575596789
Directory /workspace/49.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/49.spi_device_extreme_fifo_size.3665994933
Short name T26
Test name
Test status
Simulation time 56090147062 ps
CPU time 552.64 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:21:36 PM PST 23
Peak memory 219064 kb
Host smart-5340c8b5-b4c9-4ba7-ba9b-211b4e8a3fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665994933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_extreme_fifo_size.3665994933
Directory /workspace/49.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/49.spi_device_fifo_full.3907576745
Short name T1109
Test name
Test status
Simulation time 90936121804 ps
CPU time 271.07 seconds
Started Dec 31 01:12:16 PM PST 23
Finished Dec 31 01:16:51 PM PST 23
Peak memory 272004 kb
Host smart-ed518134-b666-403c-9e5c-73ac7b702c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907576745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_fifo_full.3907576745
Directory /workspace/49.spi_device_fifo_full/latest

Test location /workspace/coverage/default/49.spi_device_fifo_underflow_overflow.3636643977
Short name T1285
Test name
Test status
Simulation time 200019856485 ps
CPU time 1564 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:38:31 PM PST 23
Peak memory 637728 kb
Host smart-4a54412d-6446-452f-b103-a74c8d94ba92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636643977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_fifo_underflow_overf
low.3636643977
Directory /workspace/49.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.236376039
Short name T316
Test name
Test status
Simulation time 195817741406 ps
CPU time 173.48 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 01:15:16 PM PST 23
Peak memory 252548 kb
Host smart-1abdf2e5-ec25-4cb9-b61e-d1a1c478bcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236376039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.236376039
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2193927369
Short name T885
Test name
Test status
Simulation time 2363666310 ps
CPU time 46.14 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:13:17 PM PST 23
Peak memory 259496 kb
Host smart-958514f7-2774-4ebb-8e2a-b874cf4d4fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193927369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2193927369
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.4166956750
Short name T709
Test name
Test status
Simulation time 80574554211 ps
CPU time 151.61 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:14:57 PM PST 23
Peak memory 249848 kb
Host smart-a75f5f06-1a18-4333-b832-51c570b4aca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166956750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.4166956750
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.980107439
Short name T151
Test name
Test status
Simulation time 10443896225 ps
CPU time 31.04 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:57 PM PST 23
Peak memory 249688 kb
Host smart-8d973111-935d-49dd-899b-dc31aba2f796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980107439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.980107439
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.512882171
Short name T592
Test name
Test status
Simulation time 1041787902 ps
CPU time 3.51 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:12:34 PM PST 23
Peak memory 218460 kb
Host smart-fee7f006-e43c-47ac-9586-0666dd37574f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512882171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.512882171
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_intr.2912718728
Short name T1613
Test name
Test status
Simulation time 57421084281 ps
CPU time 55.3 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 01:13:17 PM PST 23
Peak memory 224540 kb
Host smart-b563fa18-f104-4314-abd3-ab1eb39fa71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912718728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intr.2912718728
Directory /workspace/49.spi_device_intr/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1717735531
Short name T672
Test name
Test status
Simulation time 1768892468 ps
CPU time 3.19 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:12:34 PM PST 23
Peak memory 218148 kb
Host smart-c9deadb1-555a-4d4f-9b43-ccf553396127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717735531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1717735531
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1328297136
Short name T298
Test name
Test status
Simulation time 6215523397 ps
CPU time 8.47 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:34 PM PST 23
Peak memory 249640 kb
Host smart-165c8467-9946-47ff-897d-327f866d292d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328297136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1328297136
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3815285539
Short name T1139
Test name
Test status
Simulation time 37395659340 ps
CPU time 56.33 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:13:20 PM PST 23
Peak memory 266236 kb
Host smart-745ebe60-dfd7-4443-95dc-cbff9a4af2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815285539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3815285539
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_perf.287590183
Short name T791
Test name
Test status
Simulation time 43574584760 ps
CPU time 486.85 seconds
Started Dec 31 01:12:12 PM PST 23
Finished Dec 31 01:20:21 PM PST 23
Peak memory 241056 kb
Host smart-38b69aae-4eab-4a8b-b601-2126f4352943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287590183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_perf.287590183
Directory /workspace/49.spi_device_perf/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3813733056
Short name T754
Test name
Test status
Simulation time 1071925464 ps
CPU time 3.85 seconds
Started Dec 31 01:12:25 PM PST 23
Finished Dec 31 01:12:35 PM PST 23
Peak memory 218500 kb
Host smart-f3ca3829-d851-4ef7-9f30-1c8597f37e11
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3813733056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3813733056
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_rx_async_fifo_reset.1422289680
Short name T1663
Test name
Test status
Simulation time 132330667 ps
CPU time 0.84 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 01:12:24 PM PST 23
Peak memory 208496 kb
Host smart-5ed817a8-a81b-4ea4-8774-a5b0bdff36e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422289680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_rx_async_fifo_reset.1422289680
Directory /workspace/49.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/49.spi_device_rx_timeout.543318152
Short name T886
Test name
Test status
Simulation time 465176018 ps
CPU time 5.63 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 01:12:28 PM PST 23
Peak memory 216764 kb
Host smart-e69cd66e-3a5c-488e-afab-e9fbd29cd4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543318152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_rx_timeout.543318152
Directory /workspace/49.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/49.spi_device_smoke.1342853105
Short name T1416
Test name
Test status
Simulation time 72907571 ps
CPU time 1.33 seconds
Started Dec 31 01:12:07 PM PST 23
Finished Dec 31 01:12:10 PM PST 23
Peak memory 216864 kb
Host smart-c0516a63-781b-43fb-bccf-3629e84cdb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342853105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_smoke.1342853105
Directory /workspace/49.spi_device_smoke/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2863486973
Short name T653
Test name
Test status
Simulation time 166935904739 ps
CPU time 4892.23 seconds
Started Dec 31 01:12:22 PM PST 23
Finished Dec 31 02:34:01 PM PST 23
Peak memory 283732 kb
Host smart-33675f8a-790f-40a5-8a95-d02fae8b49af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863486973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2863486973
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2164474524
Short name T1785
Test name
Test status
Simulation time 408133701 ps
CPU time 5.54 seconds
Started Dec 31 01:12:12 PM PST 23
Finished Dec 31 01:12:19 PM PST 23
Peak memory 219316 kb
Host smart-d50b3776-6f90-4011-892a-1dbcd612e0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164474524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2164474524
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.13116100
Short name T1773
Test name
Test status
Simulation time 46318663673 ps
CPU time 13.56 seconds
Started Dec 31 01:12:22 PM PST 23
Finished Dec 31 01:12:42 PM PST 23
Peak memory 216824 kb
Host smart-61f0b6cd-b196-4237-a598-e217eb20b2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13116100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.13116100
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2840372646
Short name T1013
Test name
Test status
Simulation time 18274443 ps
CPU time 1.17 seconds
Started Dec 31 01:12:17 PM PST 23
Finished Dec 31 01:12:23 PM PST 23
Peak memory 216524 kb
Host smart-a5caaaaa-9d9b-4ad7-852d-a45b88540d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840372646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2840372646
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1101744104
Short name T953
Test name
Test status
Simulation time 74731732 ps
CPU time 1.01 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 207960 kb
Host smart-d8cb1023-9323-402d-b69e-fff41082d04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101744104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1101744104
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_tx_async_fifo_reset.1110626999
Short name T731
Test name
Test status
Simulation time 29242162 ps
CPU time 0.78 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 208444 kb
Host smart-40a0ec12-d33b-4ea6-8fed-81b40868de49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110626999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tx_async_fifo_reset.1110626999
Directory /workspace/49.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/49.spi_device_txrx.2157244068
Short name T1706
Test name
Test status
Simulation time 27254881662 ps
CPU time 249.78 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:16:38 PM PST 23
Peak memory 271368 kb
Host smart-5b24780c-962c-4405-bf89-b4f97089f49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157244068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_txrx.2157244068
Directory /workspace/49.spi_device_txrx/latest

Test location /workspace/coverage/default/49.spi_device_upload.1782400939
Short name T1160
Test name
Test status
Simulation time 341853470 ps
CPU time 3.15 seconds
Started Dec 31 01:12:22 PM PST 23
Finished Dec 31 01:12:32 PM PST 23
Peak memory 218328 kb
Host smart-3ad7c6b0-1ce1-4d61-b63b-203f0924d3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782400939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1782400939
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_abort.957060465
Short name T876
Test name
Test status
Simulation time 42959113 ps
CPU time 0.74 seconds
Started Dec 31 01:08:05 PM PST 23
Finished Dec 31 01:08:08 PM PST 23
Peak memory 206616 kb
Host smart-e278edd4-88ae-4675-9324-b5d48338f02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957060465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_abort.957060465
Directory /workspace/5.spi_device_abort/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3952945549
Short name T530
Test name
Test status
Simulation time 37614496 ps
CPU time 0.7 seconds
Started Dec 31 01:08:04 PM PST 23
Finished Dec 31 01:08:06 PM PST 23
Peak memory 206488 kb
Host smart-61c1ed2f-6d1e-4fd2-a639-283064dc4319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952945549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
952945549
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_bit_transfer.1156848498
Short name T1395
Test name
Test status
Simulation time 454304020 ps
CPU time 2.46 seconds
Started Dec 31 01:08:07 PM PST 23
Finished Dec 31 01:08:11 PM PST 23
Peak memory 216804 kb
Host smart-1241afbb-3831-42d6-90f3-24a234682806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156848498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_bit_transfer.1156848498
Directory /workspace/5.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/5.spi_device_byte_transfer.2207235793
Short name T1463
Test name
Test status
Simulation time 210007883 ps
CPU time 2.2 seconds
Started Dec 31 01:07:59 PM PST 23
Finished Dec 31 01:08:02 PM PST 23
Peak memory 216844 kb
Host smart-82cefe3f-4f02-4c80-baf0-a4ec3447677d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207235793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_byte_transfer.2207235793
Directory /workspace/5.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3820523335
Short name T1429
Test name
Test status
Simulation time 1176793334 ps
CPU time 3.42 seconds
Started Dec 31 01:08:05 PM PST 23
Finished Dec 31 01:08:11 PM PST 23
Peak memory 219192 kb
Host smart-f9806c8f-7a39-4dbc-9928-03babad58a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820523335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3820523335
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2516826199
Short name T460
Test name
Test status
Simulation time 73660396 ps
CPU time 0.75 seconds
Started Dec 31 01:08:04 PM PST 23
Finished Dec 31 01:08:06 PM PST 23
Peak memory 206536 kb
Host smart-9acccc6a-58fd-4ac2-a21f-a04d9a16d3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516826199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2516826199
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_dummy_item_extra_dly.1177953088
Short name T563
Test name
Test status
Simulation time 283935037419 ps
CPU time 314.53 seconds
Started Dec 31 01:08:28 PM PST 23
Finished Dec 31 01:13:43 PM PST 23
Peak memory 325208 kb
Host smart-7bc8595e-54ea-4916-a0db-4ab619db45d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177953088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_dummy_item_extra_dly.1177953088
Directory /workspace/5.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/5.spi_device_extreme_fifo_size.1740855504
Short name T848
Test name
Test status
Simulation time 54101519797 ps
CPU time 2389.37 seconds
Started Dec 31 01:08:46 PM PST 23
Finished Dec 31 01:48:36 PM PST 23
Peak memory 219940 kb
Host smart-228c0f1d-b55c-4b8b-be61-9cfb8325eca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740855504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_extreme_fifo_size.1740855504
Directory /workspace/5.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/5.spi_device_fifo_full.1799850586
Short name T1698
Test name
Test status
Simulation time 568389835946 ps
CPU time 535.21 seconds
Started Dec 31 01:08:27 PM PST 23
Finished Dec 31 01:17:24 PM PST 23
Peak memory 282132 kb
Host smart-132a5cd1-958b-4f4c-a3e0-69f342b617d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799850586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_fifo_full.1799850586
Directory /workspace/5.spi_device_fifo_full/latest

Test location /workspace/coverage/default/5.spi_device_fifo_underflow_overflow.2995522373
Short name T738
Test name
Test status
Simulation time 121535315967 ps
CPU time 256.5 seconds
Started Dec 31 01:08:23 PM PST 23
Finished Dec 31 01:12:40 PM PST 23
Peak memory 299792 kb
Host smart-2aa54289-3f70-493a-9191-2c662b7477e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995522373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_fifo_underflow_overfl
ow.2995522373
Directory /workspace/5.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3835206784
Short name T1159
Test name
Test status
Simulation time 6830219137 ps
CPU time 78.22 seconds
Started Dec 31 01:08:03 PM PST 23
Finished Dec 31 01:09:23 PM PST 23
Peak memory 265888 kb
Host smart-cbc9a94c-5b35-4bbd-a360-be4302c25688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835206784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3835206784
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.303828570
Short name T884
Test name
Test status
Simulation time 1835783484 ps
CPU time 12.69 seconds
Started Dec 31 01:08:27 PM PST 23
Finished Dec 31 01:08:41 PM PST 23
Peak memory 224076 kb
Host smart-22019809-a003-4af7-86e6-19b501d3a5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303828570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.303828570
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1889354052
Short name T1368
Test name
Test status
Simulation time 10359995917 ps
CPU time 18.99 seconds
Started Dec 31 01:08:02 PM PST 23
Finished Dec 31 01:08:23 PM PST 23
Peak memory 238272 kb
Host smart-e6a6af9f-9c82-4397-a30d-740e4202bc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889354052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1889354052
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_intr.543960387
Short name T1740
Test name
Test status
Simulation time 25373029404 ps
CPU time 48.19 seconds
Started Dec 31 01:08:07 PM PST 23
Finished Dec 31 01:08:57 PM PST 23
Peak memory 233388 kb
Host smart-462db9cf-e756-436d-94e0-6493227f59e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543960387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intr.543960387
Directory /workspace/5.spi_device_intr/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3132700922
Short name T1143
Test name
Test status
Simulation time 1396110944 ps
CPU time 2.62 seconds
Started Dec 31 01:08:06 PM PST 23
Finished Dec 31 01:08:11 PM PST 23
Peak memory 218296 kb
Host smart-f104e50f-9bc9-47a4-82a8-a1be17078883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132700922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3132700922
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.832983158
Short name T1621
Test name
Test status
Simulation time 80947821 ps
CPU time 1.05 seconds
Started Dec 31 01:08:02 PM PST 23
Finished Dec 31 01:08:04 PM PST 23
Peak memory 218876 kb
Host smart-100cc159-054d-4765-ab42-eb7f356c6827
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832983158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.832983158
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3344829821
Short name T287
Test name
Test status
Simulation time 12694004770 ps
CPU time 14.1 seconds
Started Dec 31 01:08:14 PM PST 23
Finished Dec 31 01:08:29 PM PST 23
Peak memory 246712 kb
Host smart-087196f5-5c93-4658-8588-1feb236beac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344829821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3344829821
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3193976936
Short name T1691
Test name
Test status
Simulation time 8705185469 ps
CPU time 26.5 seconds
Started Dec 31 01:08:26 PM PST 23
Finished Dec 31 01:08:54 PM PST 23
Peak memory 230888 kb
Host smart-0a8602ab-677a-482d-95c9-1e0ebad5ec2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193976936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3193976936
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_perf.419776256
Short name T542
Test name
Test status
Simulation time 33176187777 ps
CPU time 351.9 seconds
Started Dec 31 01:07:58 PM PST 23
Finished Dec 31 01:13:51 PM PST 23
Peak memory 248880 kb
Host smart-0bff1206-6573-4ccf-ba7a-06e3e2e16fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419776256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_perf.419776256
Directory /workspace/5.spi_device_perf/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.2035521636
Short name T1100
Test name
Test status
Simulation time 57337471 ps
CPU time 0.73 seconds
Started Dec 31 01:08:46 PM PST 23
Finished Dec 31 01:08:47 PM PST 23
Peak memory 216696 kb
Host smart-913860d7-5c48-42a0-bccd-95ad41be5d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035521636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.2035521636
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1589472363
Short name T487
Test name
Test status
Simulation time 1066544238 ps
CPU time 6.37 seconds
Started Dec 31 01:08:03 PM PST 23
Finished Dec 31 01:08:11 PM PST 23
Peak memory 234480 kb
Host smart-742f19e6-c849-4491-9eb3-83f3aec45c3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1589472363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1589472363
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_rx_async_fifo_reset.2020366103
Short name T573
Test name
Test status
Simulation time 52427061 ps
CPU time 0.88 seconds
Started Dec 31 01:08:04 PM PST 23
Finished Dec 31 01:08:06 PM PST 23
Peak memory 208464 kb
Host smart-e039c038-1c14-418f-acf3-5e46e9142ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020366103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_rx_async_fifo_reset.2020366103
Directory /workspace/5.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/5.spi_device_rx_timeout.3606951379
Short name T966
Test name
Test status
Simulation time 2062080802 ps
CPU time 5.15 seconds
Started Dec 31 01:07:59 PM PST 23
Finished Dec 31 01:08:05 PM PST 23
Peak memory 216748 kb
Host smart-e7cbe92b-cd13-4338-9012-993934d19826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606951379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_rx_timeout.3606951379
Directory /workspace/5.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/5.spi_device_smoke.1292099471
Short name T652
Test name
Test status
Simulation time 60248806 ps
CPU time 1.26 seconds
Started Dec 31 01:08:27 PM PST 23
Finished Dec 31 01:08:29 PM PST 23
Peak memory 216800 kb
Host smart-07317c94-b422-41c4-95c8-a27cf1cecc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292099471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_smoke.1292099471
Directory /workspace/5.spi_device_smoke/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.809919884
Short name T1296
Test name
Test status
Simulation time 78522559535 ps
CPU time 1564.72 seconds
Started Dec 31 01:08:30 PM PST 23
Finished Dec 31 01:34:36 PM PST 23
Peak memory 349564 kb
Host smart-9c1e3eaf-1f5b-40c0-af59-57e9036454f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809919884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.809919884
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2806399502
Short name T910
Test name
Test status
Simulation time 2143861874 ps
CPU time 25.14 seconds
Started Dec 31 01:08:06 PM PST 23
Finished Dec 31 01:08:33 PM PST 23
Peak memory 216804 kb
Host smart-43d79973-25c2-48b7-9230-cc8bf4450aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806399502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2806399502
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2304365403
Short name T1634
Test name
Test status
Simulation time 7468963128 ps
CPU time 22.86 seconds
Started Dec 31 01:08:48 PM PST 23
Finished Dec 31 01:09:13 PM PST 23
Peak memory 216876 kb
Host smart-7a588c9b-e831-4da1-a6e8-cc2dc5cc216a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304365403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2304365403
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1328891375
Short name T1308
Test name
Test status
Simulation time 100653333 ps
CPU time 1.19 seconds
Started Dec 31 01:08:26 PM PST 23
Finished Dec 31 01:08:28 PM PST 23
Peak memory 208360 kb
Host smart-54059608-6790-4cf2-b3fe-7f28ade9e425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328891375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1328891375
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3722943526
Short name T496
Test name
Test status
Simulation time 27159700 ps
CPU time 0.84 seconds
Started Dec 31 01:08:49 PM PST 23
Finished Dec 31 01:08:52 PM PST 23
Peak memory 206928 kb
Host smart-077a45bc-dd37-4ecd-a6af-755f01410f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722943526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3722943526
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_tx_async_fifo_reset.2006517699
Short name T509
Test name
Test status
Simulation time 59243570 ps
CPU time 0.76 seconds
Started Dec 31 01:08:24 PM PST 23
Finished Dec 31 01:08:26 PM PST 23
Peak memory 208464 kb
Host smart-ea057e71-6750-4c09-a5ad-86ade2192ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006517699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tx_async_fifo_reset.2006517699
Directory /workspace/5.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/5.spi_device_txrx.844798735
Short name T545
Test name
Test status
Simulation time 22041835475 ps
CPU time 230.53 seconds
Started Dec 31 01:08:28 PM PST 23
Finished Dec 31 01:12:19 PM PST 23
Peak memory 268008 kb
Host smart-fa20ab17-b41d-4924-9f7b-0b0560f6dfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844798735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_txrx.844798735
Directory /workspace/5.spi_device_txrx/latest

Test location /workspace/coverage/default/5.spi_device_upload.1270284073
Short name T1036
Test name
Test status
Simulation time 138048534 ps
CPU time 2.74 seconds
Started Dec 31 01:08:03 PM PST 23
Finished Dec 31 01:08:07 PM PST 23
Peak memory 218932 kb
Host smart-1f30ebbb-9969-4466-931c-187ab8fc3d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270284073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1270284073
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_abort.2245873861
Short name T1546
Test name
Test status
Simulation time 14997797 ps
CPU time 0.76 seconds
Started Dec 31 01:08:34 PM PST 23
Finished Dec 31 01:08:36 PM PST 23
Peak memory 206556 kb
Host smart-4d177b46-01bd-4191-8017-9b77a82d1fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245873861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_abort.2245873861
Directory /workspace/6.spi_device_abort/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3898795620
Short name T1102
Test name
Test status
Simulation time 12871460 ps
CPU time 0.72 seconds
Started Dec 31 01:08:00 PM PST 23
Finished Dec 31 01:08:02 PM PST 23
Peak memory 206448 kb
Host smart-a7f430df-67e8-4f1f-822c-7c518b18d661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898795620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
898795620
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_bit_transfer.2754720751
Short name T763
Test name
Test status
Simulation time 282555517 ps
CPU time 2.94 seconds
Started Dec 31 01:08:48 PM PST 23
Finished Dec 31 01:08:53 PM PST 23
Peak memory 216748 kb
Host smart-a8a612b2-6ea5-4d48-acb2-164213410617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754720751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_bit_transfer.2754720751
Directory /workspace/6.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/6.spi_device_byte_transfer.3780318699
Short name T1780
Test name
Test status
Simulation time 171112037 ps
CPU time 2.77 seconds
Started Dec 31 01:08:04 PM PST 23
Finished Dec 31 01:08:09 PM PST 23
Peak memory 216788 kb
Host smart-8329372b-19df-47cd-a7c3-4f99e211a770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780318699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_byte_transfer.3780318699
Directory /workspace/6.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2964530381
Short name T1279
Test name
Test status
Simulation time 268916420 ps
CPU time 4.64 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:09:02 PM PST 23
Peak memory 239712 kb
Host smart-f861011d-7e71-4487-bb96-99734fe1c5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964530381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2964530381
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1932860306
Short name T1154
Test name
Test status
Simulation time 179490424 ps
CPU time 0.76 seconds
Started Dec 31 01:08:00 PM PST 23
Finished Dec 31 01:08:01 PM PST 23
Peak memory 206536 kb
Host smart-8f2c5653-7a8a-4591-9bee-a7f68657cadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932860306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1932860306
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_dummy_item_extra_dly.772966646
Short name T447
Test name
Test status
Simulation time 69349820748 ps
CPU time 1538.82 seconds
Started Dec 31 01:07:58 PM PST 23
Finished Dec 31 01:33:39 PM PST 23
Peak memory 266008 kb
Host smart-ab4579c8-a9f4-43a6-814f-dfc9d27ea6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772966646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_dummy_item_extra_dly.772966646
Directory /workspace/6.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/6.spi_device_extreme_fifo_size.1731166639
Short name T1451
Test name
Test status
Simulation time 17855762476 ps
CPU time 56.9 seconds
Started Dec 31 01:07:58 PM PST 23
Finished Dec 31 01:08:57 PM PST 23
Peak memory 229792 kb
Host smart-c6f5299c-d1a4-4704-ba5b-80990d6a3ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731166639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_extreme_fifo_size.1731166639
Directory /workspace/6.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/6.spi_device_fifo_full.2858162804
Short name T1134
Test name
Test status
Simulation time 29135534087 ps
CPU time 648.16 seconds
Started Dec 31 01:08:06 PM PST 23
Finished Dec 31 01:18:56 PM PST 23
Peak memory 251000 kb
Host smart-0a48bff9-0e15-4ddd-a5f8-cd05ecac76b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858162804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_fifo_full.2858162804
Directory /workspace/6.spi_device_fifo_full/latest

Test location /workspace/coverage/default/6.spi_device_fifo_underflow_overflow.2453548279
Short name T1655
Test name
Test status
Simulation time 47563736111 ps
CPU time 93.75 seconds
Started Dec 31 01:07:59 PM PST 23
Finished Dec 31 01:09:34 PM PST 23
Peak memory 265944 kb
Host smart-49a721a5-8d00-400c-87da-184320d69c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453548279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_fifo_underflow_overfl
ow.2453548279
Directory /workspace/6.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.4025763860
Short name T207
Test name
Test status
Simulation time 57041613878 ps
CPU time 107.29 seconds
Started Dec 31 01:08:50 PM PST 23
Finished Dec 31 01:10:40 PM PST 23
Peak memory 266268 kb
Host smart-484682c1-95ad-4b1c-9bfc-9a723c4eee98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025763860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.4025763860
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3772961948
Short name T1248
Test name
Test status
Simulation time 6874751347 ps
CPU time 103 seconds
Started Dec 31 01:08:46 PM PST 23
Finished Dec 31 01:10:31 PM PST 23
Peak memory 254056 kb
Host smart-c9629ce3-a133-41e2-92ac-b997cdd4a28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772961948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3772961948
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.887347938
Short name T1549
Test name
Test status
Simulation time 26436766544 ps
CPU time 203.32 seconds
Started Dec 31 01:08:10 PM PST 23
Finished Dec 31 01:11:35 PM PST 23
Peak memory 266008 kb
Host smart-3deadd3c-9282-4d35-a2c5-c1bb91b1b5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887347938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
887347938
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.74050811
Short name T705
Test name
Test status
Simulation time 4411121922 ps
CPU time 15.83 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:09:12 PM PST 23
Peak memory 248424 kb
Host smart-db6cd519-a4c9-4b33-bfef-61ca888a826a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74050811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.74050811
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2630723855
Short name T220
Test name
Test status
Simulation time 4140334502 ps
CPU time 6.97 seconds
Started Dec 31 01:08:37 PM PST 23
Finished Dec 31 01:08:47 PM PST 23
Peak memory 221208 kb
Host smart-4a266040-4125-4a70-b793-6bafa008dbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630723855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2630723855
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_intr.359414360
Short name T181
Test name
Test status
Simulation time 65723323359 ps
CPU time 74.95 seconds
Started Dec 31 01:08:04 PM PST 23
Finished Dec 31 01:09:21 PM PST 23
Peak memory 241608 kb
Host smart-dd5b6c64-c7a7-44f0-9a09-c65fa5e3b3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359414360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intr.359414360
Directory /workspace/6.spi_device_intr/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2316237905
Short name T474
Test name
Test status
Simulation time 14065725042 ps
CPU time 10.9 seconds
Started Dec 31 01:08:51 PM PST 23
Finished Dec 31 01:09:05 PM PST 23
Peak memory 225116 kb
Host smart-52f2221a-b8ee-4e69-9bf3-30b6af37dd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316237905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2316237905
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2558391000
Short name T973
Test name
Test status
Simulation time 34521848 ps
CPU time 1.11 seconds
Started Dec 31 01:08:03 PM PST 23
Finished Dec 31 01:08:06 PM PST 23
Peak memory 218840 kb
Host smart-8f20dad5-957b-4013-af22-2b87e9912fbe
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558391000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2558391000
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2381717586
Short name T1058
Test name
Test status
Simulation time 39545428 ps
CPU time 2.66 seconds
Started Dec 31 01:08:49 PM PST 23
Finished Dec 31 01:08:54 PM PST 23
Peak memory 233360 kb
Host smart-4d0d2d80-6d1e-443c-b4e6-54096d1e0d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381717586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2381717586
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1939119329
Short name T1254
Test name
Test status
Simulation time 38115145181 ps
CPU time 30.55 seconds
Started Dec 31 01:08:50 PM PST 23
Finished Dec 31 01:09:23 PM PST 23
Peak memory 247404 kb
Host smart-5885fe60-37ea-4ed8-a55e-db8f574fe5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939119329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1939119329
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_perf.820575089
Short name T740
Test name
Test status
Simulation time 9053522001 ps
CPU time 274.08 seconds
Started Dec 31 01:08:03 PM PST 23
Finished Dec 31 01:12:39 PM PST 23
Peak memory 285672 kb
Host smart-982b1d24-18fc-4b2d-9259-bcdd99d0958a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820575089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_perf.820575089
Directory /workspace/6.spi_device_perf/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.3213310527
Short name T73
Test name
Test status
Simulation time 18047078 ps
CPU time 0.72 seconds
Started Dec 31 01:08:48 PM PST 23
Finished Dec 31 01:08:51 PM PST 23
Peak memory 216648 kb
Host smart-261037c6-ef08-41ec-bccc-b496f8e0b8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213310527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.3213310527
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2034689064
Short name T1142
Test name
Test status
Simulation time 559049319 ps
CPU time 5.04 seconds
Started Dec 31 01:08:55 PM PST 23
Finished Dec 31 01:09:05 PM PST 23
Peak memory 218564 kb
Host smart-130069da-60ed-4c50-8b87-22ee1ca13fd9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2034689064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2034689064
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_rx_async_fifo_reset.69902077
Short name T775
Test name
Test status
Simulation time 61312319 ps
CPU time 0.86 seconds
Started Dec 31 01:08:06 PM PST 23
Finished Dec 31 01:08:09 PM PST 23
Peak memory 208488 kb
Host smart-c4c4b667-1fff-4a18-91a7-a35f768f074c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69902077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_rx_async_fifo_reset.69902077
Directory /workspace/6.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/6.spi_device_rx_timeout.3713829990
Short name T905
Test name
Test status
Simulation time 2215687347 ps
CPU time 4.8 seconds
Started Dec 31 01:08:04 PM PST 23
Finished Dec 31 01:08:10 PM PST 23
Peak memory 216804 kb
Host smart-7b52c406-dbbc-4419-8a5d-52d4ccc3fa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713829990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_rx_timeout.3713829990
Directory /workspace/6.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/6.spi_device_smoke.28490107
Short name T1185
Test name
Test status
Simulation time 34542773 ps
CPU time 1.1 seconds
Started Dec 31 01:08:25 PM PST 23
Finished Dec 31 01:08:27 PM PST 23
Peak memory 207948 kb
Host smart-54f10cdf-5162-4087-ab50-ae5827b784d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28490107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_smoke.28490107
Directory /workspace/6.spi_device_smoke/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.998836121
Short name T313
Test name
Test status
Simulation time 234554748626 ps
CPU time 2447.49 seconds
Started Dec 31 01:08:24 PM PST 23
Finished Dec 31 01:49:13 PM PST 23
Peak memory 429688 kb
Host smart-6c388d3f-67e9-455b-8a72-32760bdd038b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998836121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.998836121
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2572403265
Short name T808
Test name
Test status
Simulation time 4762316559 ps
CPU time 17.26 seconds
Started Dec 31 01:08:24 PM PST 23
Finished Dec 31 01:08:42 PM PST 23
Peak memory 216996 kb
Host smart-6cc01e10-0288-4feb-a6d9-c19189ccf3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572403265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2572403265
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4035034798
Short name T1023
Test name
Test status
Simulation time 2186099239 ps
CPU time 9.83 seconds
Started Dec 31 01:08:24 PM PST 23
Finished Dec 31 01:08:34 PM PST 23
Peak memory 216904 kb
Host smart-1cc4355a-fac7-4a9a-b1e7-86903de52903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035034798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4035034798
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2424289405
Short name T982
Test name
Test status
Simulation time 73516812 ps
CPU time 1.64 seconds
Started Dec 31 01:08:10 PM PST 23
Finished Dec 31 01:08:13 PM PST 23
Peak memory 216836 kb
Host smart-b555679c-2e97-4442-a53a-03492059335c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424289405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2424289405
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1084467915
Short name T1480
Test name
Test status
Simulation time 103351739 ps
CPU time 0.91 seconds
Started Dec 31 01:08:37 PM PST 23
Finished Dec 31 01:08:41 PM PST 23
Peak memory 206908 kb
Host smart-c4d0b218-c259-4b21-b2da-4d841dc7f453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084467915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1084467915
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_tx_async_fifo_reset.1261316302
Short name T800
Test name
Test status
Simulation time 126524026 ps
CPU time 0.77 seconds
Started Dec 31 01:08:22 PM PST 23
Finished Dec 31 01:08:23 PM PST 23
Peak memory 208480 kb
Host smart-dab82e31-d479-4e97-85db-7d282787be12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261316302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tx_async_fifo_reset.1261316302
Directory /workspace/6.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/6.spi_device_txrx.3541978616
Short name T1124
Test name
Test status
Simulation time 75389568691 ps
CPU time 942.49 seconds
Started Dec 31 01:07:58 PM PST 23
Finished Dec 31 01:23:42 PM PST 23
Peak memory 336132 kb
Host smart-7dfaad21-bfeb-4587-891e-be7c70062fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541978616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_txrx.3541978616
Directory /workspace/6.spi_device_txrx/latest

Test location /workspace/coverage/default/6.spi_device_upload.4235685962
Short name T234
Test name
Test status
Simulation time 3563084415 ps
CPU time 13.64 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:09:10 PM PST 23
Peak memory 221660 kb
Host smart-6ecea15a-dd35-4c1d-92e3-0db480d351f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235685962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.4235685962
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_abort.2821898671
Short name T1457
Test name
Test status
Simulation time 14410810 ps
CPU time 0.72 seconds
Started Dec 31 01:08:57 PM PST 23
Finished Dec 31 01:09:05 PM PST 23
Peak memory 206624 kb
Host smart-b5db86f2-6308-4ea8-93f6-b5e78105a3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821898671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_abort.2821898671
Directory /workspace/7.spi_device_abort/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2798541183
Short name T1761
Test name
Test status
Simulation time 14225785 ps
CPU time 0.76 seconds
Started Dec 31 01:08:46 PM PST 23
Finished Dec 31 01:08:48 PM PST 23
Peak memory 206468 kb
Host smart-8a560ee6-d04e-4b73-b4a3-8e049df2bfa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798541183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
798541183
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_bit_transfer.2419010165
Short name T1032
Test name
Test status
Simulation time 391812010 ps
CPU time 2.93 seconds
Started Dec 31 01:08:11 PM PST 23
Finished Dec 31 01:08:15 PM PST 23
Peak memory 216780 kb
Host smart-0e259ed4-b4e7-47a7-836a-6012b03f6d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419010165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_bit_transfer.2419010165
Directory /workspace/7.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/7.spi_device_byte_transfer.896212359
Short name T1478
Test name
Test status
Simulation time 176487739 ps
CPU time 2.68 seconds
Started Dec 31 01:08:27 PM PST 23
Finished Dec 31 01:08:31 PM PST 23
Peak memory 216812 kb
Host smart-269fa529-6340-4c55-b9ba-f98dcf1e3ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896212359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_byte_transfer.896212359
Directory /workspace/7.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2756208249
Short name T1323
Test name
Test status
Simulation time 1259392991 ps
CPU time 4.64 seconds
Started Dec 31 01:08:25 PM PST 23
Finished Dec 31 01:08:31 PM PST 23
Peak memory 239628 kb
Host smart-bedde4f5-635c-4033-8442-ed4301183e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756208249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2756208249
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1866664896
Short name T831
Test name
Test status
Simulation time 53621018 ps
CPU time 0.77 seconds
Started Dec 31 01:08:04 PM PST 23
Finished Dec 31 01:08:06 PM PST 23
Peak memory 206556 kb
Host smart-3dba1439-7680-46f3-9ab0-17dd28a3faea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866664896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1866664896
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_dummy_item_extra_dly.1437642117
Short name T892
Test name
Test status
Simulation time 75898940604 ps
CPU time 603.29 seconds
Started Dec 31 01:08:06 PM PST 23
Finished Dec 31 01:18:12 PM PST 23
Peak memory 267812 kb
Host smart-daaed46e-fe85-4370-8ebb-b4cab2e6e8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437642117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_dummy_item_extra_dly.1437642117
Directory /workspace/7.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/7.spi_device_extreme_fifo_size.2156264470
Short name T254
Test name
Test status
Simulation time 157411118764 ps
CPU time 1554.56 seconds
Started Dec 31 01:08:47 PM PST 23
Finished Dec 31 01:34:43 PM PST 23
Peak memory 218196 kb
Host smart-86a87d13-463b-43f1-a122-c7ef3d0ac8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156264470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_extreme_fifo_size.2156264470
Directory /workspace/7.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/7.spi_device_fifo_full.1849556658
Short name T589
Test name
Test status
Simulation time 32278299920 ps
CPU time 536.99 seconds
Started Dec 31 01:08:00 PM PST 23
Finished Dec 31 01:16:58 PM PST 23
Peak memory 271828 kb
Host smart-eadd5946-37b7-4b88-b8ee-32427c01657c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849556658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_fifo_full.1849556658
Directory /workspace/7.spi_device_fifo_full/latest

Test location /workspace/coverage/default/7.spi_device_fifo_underflow_overflow.1130857882
Short name T1667
Test name
Test status
Simulation time 83504562942 ps
CPU time 674.39 seconds
Started Dec 31 01:08:09 PM PST 23
Finished Dec 31 01:19:25 PM PST 23
Peak memory 372852 kb
Host smart-b24745ce-32ba-40e3-b3ea-6534de85c9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130857882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_fifo_underflow_overfl
ow.1130857882
Directory /workspace/7.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.361555317
Short name T302
Test name
Test status
Simulation time 4720952465 ps
CPU time 63.91 seconds
Started Dec 31 01:08:24 PM PST 23
Finished Dec 31 01:09:29 PM PST 23
Peak memory 256888 kb
Host smart-affa66f2-7283-4643-b315-3c76fb1e8f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361555317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.361555317
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3048306848
Short name T308
Test name
Test status
Simulation time 9662791158 ps
CPU time 42.12 seconds
Started Dec 31 01:08:24 PM PST 23
Finished Dec 31 01:09:08 PM PST 23
Peak memory 239384 kb
Host smart-ba27c47a-abaa-4e24-8afb-c14b4d42a764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048306848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3048306848
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1556010216
Short name T862
Test name
Test status
Simulation time 2123901225 ps
CPU time 36.12 seconds
Started Dec 31 01:08:03 PM PST 23
Finished Dec 31 01:08:41 PM PST 23
Peak memory 237576 kb
Host smart-fe954e3f-f5bd-4949-87f0-aed42501eadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556010216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1556010216
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3825768555
Short name T687
Test name
Test status
Simulation time 10781141508 ps
CPU time 16.83 seconds
Started Dec 31 01:08:24 PM PST 23
Finished Dec 31 01:08:42 PM PST 23
Peak memory 247756 kb
Host smart-d5a6a775-fa92-4517-b415-f9c22ef744ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825768555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3825768555
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2981014281
Short name T1041
Test name
Test status
Simulation time 7714454228 ps
CPU time 5.21 seconds
Started Dec 31 01:08:57 PM PST 23
Finished Dec 31 01:09:10 PM PST 23
Peak memory 219488 kb
Host smart-422f3107-fa15-446b-9a50-0899221489dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981014281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2981014281
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_intr.851177480
Short name T1259
Test name
Test status
Simulation time 12096382705 ps
CPU time 26.98 seconds
Started Dec 31 01:08:07 PM PST 23
Finished Dec 31 01:08:35 PM PST 23
Peak memory 221088 kb
Host smart-e39d9db0-4133-4101-ab34-3c3cb5488bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851177480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intr.851177480
Directory /workspace/7.spi_device_intr/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.402594513
Short name T228
Test name
Test status
Simulation time 53863661472 ps
CPU time 39.41 seconds
Started Dec 31 01:08:59 PM PST 23
Finished Dec 31 01:09:46 PM PST 23
Peak memory 233292 kb
Host smart-3dc66a2d-1aa6-4d87-93b4-f9dd77955cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402594513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.402594513
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.167859194
Short name T962
Test name
Test status
Simulation time 42313653 ps
CPU time 0.97 seconds
Started Dec 31 01:08:48 PM PST 23
Finished Dec 31 01:08:51 PM PST 23
Peak memory 217848 kb
Host smart-a32697ae-585b-4261-8068-a674e598f899
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167859194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.167859194
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3190350618
Short name T611
Test name
Test status
Simulation time 2579576146 ps
CPU time 6.81 seconds
Started Dec 31 01:08:49 PM PST 23
Finished Dec 31 01:08:59 PM PST 23
Peak memory 220484 kb
Host smart-0c8708a5-06d6-4a2a-bdb7-16f850551366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190350618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3190350618
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3351895016
Short name T712
Test name
Test status
Simulation time 1866428242 ps
CPU time 8.57 seconds
Started Dec 31 01:08:53 PM PST 23
Finished Dec 31 01:09:06 PM PST 23
Peak memory 249624 kb
Host smart-cd6bbb33-42ce-488b-a4b0-8d42d482197d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351895016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3351895016
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_perf.2668107242
Short name T485
Test name
Test status
Simulation time 33162632862 ps
CPU time 2022.82 seconds
Started Dec 31 01:08:45 PM PST 23
Finished Dec 31 01:42:29 PM PST 23
Peak memory 282492 kb
Host smart-afc1e266-1404-4546-a0f8-fa815a9e7ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668107242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_perf.2668107242
Directory /workspace/7.spi_device_perf/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.703553141
Short name T1015
Test name
Test status
Simulation time 17676721 ps
CPU time 0.74 seconds
Started Dec 31 01:08:34 PM PST 23
Finished Dec 31 01:08:36 PM PST 23
Peak memory 216620 kb
Host smart-68e990ae-a42d-4c9f-b6c8-beb7aba53d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703553141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.703553141
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2156557187
Short name T670
Test name
Test status
Simulation time 420838143 ps
CPU time 4.28 seconds
Started Dec 31 01:08:03 PM PST 23
Finished Dec 31 01:08:09 PM PST 23
Peak memory 218920 kb
Host smart-12ac5675-e1e4-4504-8147-c24d1639ab73
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2156557187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2156557187
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_rx_async_fifo_reset.487714386
Short name T809
Test name
Test status
Simulation time 20413693 ps
CPU time 0.86 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:08:57 PM PST 23
Peak memory 208424 kb
Host smart-9dbf6913-3781-41e4-963a-667aba9ec9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487714386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_rx_async_fifo_reset.487714386
Directory /workspace/7.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/7.spi_device_rx_timeout.4233837588
Short name T498
Test name
Test status
Simulation time 616799830 ps
CPU time 6.03 seconds
Started Dec 31 01:08:07 PM PST 23
Finished Dec 31 01:08:16 PM PST 23
Peak memory 216796 kb
Host smart-3ebb26d6-5aee-48d6-bd01-b87e8f49060f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233837588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_rx_timeout.4233837588
Directory /workspace/7.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/7.spi_device_smoke.828213796
Short name T1212
Test name
Test status
Simulation time 171779636 ps
CPU time 1.09 seconds
Started Dec 31 01:08:46 PM PST 23
Finished Dec 31 01:08:48 PM PST 23
Peak memory 208004 kb
Host smart-344e4a45-2f7f-4779-8dc1-3fb20cd82bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828213796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_smoke.828213796
Directory /workspace/7.spi_device_smoke/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3412983773
Short name T121
Test name
Test status
Simulation time 64686211979 ps
CPU time 1904.64 seconds
Started Dec 31 01:08:26 PM PST 23
Finished Dec 31 01:40:12 PM PST 23
Peak memory 420548 kb
Host smart-25df6193-7691-4477-bc34-7f7a2a709b1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412983773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3412983773
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.489598161
Short name T993
Test name
Test status
Simulation time 10878450479 ps
CPU time 24.31 seconds
Started Dec 31 01:08:34 PM PST 23
Finished Dec 31 01:09:00 PM PST 23
Peak memory 216808 kb
Host smart-bcf6f93f-606c-4893-b079-1bb853a95164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489598161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.489598161
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1813322950
Short name T996
Test name
Test status
Simulation time 18377415602 ps
CPU time 16.33 seconds
Started Dec 31 01:08:28 PM PST 23
Finished Dec 31 01:08:46 PM PST 23
Peak memory 216904 kb
Host smart-d84d803e-48b4-4e39-8919-75a6647078ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813322950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1813322950
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.470104534
Short name T1423
Test name
Test status
Simulation time 134461939 ps
CPU time 1.63 seconds
Started Dec 31 01:08:57 PM PST 23
Finished Dec 31 01:09:06 PM PST 23
Peak memory 216824 kb
Host smart-cd1da552-c48b-4463-8e95-68596db96fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470104534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.470104534
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3781450244
Short name T1094
Test name
Test status
Simulation time 112403256 ps
CPU time 1.03 seconds
Started Dec 31 01:08:55 PM PST 23
Finished Dec 31 01:09:03 PM PST 23
Peak memory 206860 kb
Host smart-22f7cc55-5dea-4539-8f67-a43590a7119a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781450244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3781450244
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_tx_async_fifo_reset.2878281135
Short name T1520
Test name
Test status
Simulation time 20201744 ps
CPU time 0.78 seconds
Started Dec 31 01:08:50 PM PST 23
Finished Dec 31 01:08:53 PM PST 23
Peak memory 208384 kb
Host smart-4cdb9730-6021-40b4-a325-fd55b5eec4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878281135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tx_async_fifo_reset.2878281135
Directory /workspace/7.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/7.spi_device_txrx.560956646
Short name T1350
Test name
Test status
Simulation time 46012432864 ps
CPU time 333.94 seconds
Started Dec 31 01:08:03 PM PST 23
Finished Dec 31 01:13:39 PM PST 23
Peak memory 290156 kb
Host smart-d75554b7-3bc5-4a3f-aac1-986cebf35528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560956646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_txrx.560956646
Directory /workspace/7.spi_device_txrx/latest

Test location /workspace/coverage/default/7.spi_device_upload.37908165
Short name T586
Test name
Test status
Simulation time 161753199 ps
CPU time 2.94 seconds
Started Dec 31 01:08:04 PM PST 23
Finished Dec 31 01:08:09 PM PST 23
Peak memory 233328 kb
Host smart-1e161a95-ede0-4951-928e-46de1449c7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37908165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.37908165
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_abort.2764109917
Short name T719
Test name
Test status
Simulation time 34897217 ps
CPU time 0.73 seconds
Started Dec 31 01:08:49 PM PST 23
Finished Dec 31 01:08:52 PM PST 23
Peak memory 206608 kb
Host smart-4eaf1e87-ee47-410b-8baf-5dba0a034b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764109917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_abort.2764109917
Directory /workspace/8.spi_device_abort/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1932255443
Short name T955
Test name
Test status
Simulation time 12561716 ps
CPU time 0.73 seconds
Started Dec 31 01:08:34 PM PST 23
Finished Dec 31 01:08:36 PM PST 23
Peak memory 206480 kb
Host smart-8fff39ef-6fd4-4d8d-817a-50d5b5f375e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932255443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
932255443
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_bit_transfer.3781143594
Short name T50
Test name
Test status
Simulation time 990532706 ps
CPU time 2.47 seconds
Started Dec 31 01:08:49 PM PST 23
Finished Dec 31 01:08:53 PM PST 23
Peak memory 216888 kb
Host smart-105e7ac8-fbff-45a5-9563-95c01cf85fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781143594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_bit_transfer.3781143594
Directory /workspace/8.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/8.spi_device_byte_transfer.267356670
Short name T1620
Test name
Test status
Simulation time 479284569 ps
CPU time 2.86 seconds
Started Dec 31 01:08:27 PM PST 23
Finished Dec 31 01:08:31 PM PST 23
Peak memory 216896 kb
Host smart-c1a0ff9e-c744-435a-9f0a-c7a32ef317f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267356670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_byte_transfer.267356670
Directory /workspace/8.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2241637071
Short name T799
Test name
Test status
Simulation time 1035802980 ps
CPU time 5.12 seconds
Started Dec 31 01:08:49 PM PST 23
Finished Dec 31 01:08:56 PM PST 23
Peak memory 220376 kb
Host smart-b83cfebd-0b4c-428c-b531-187a9af8586a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241637071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2241637071
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2879340307
Short name T27
Test name
Test status
Simulation time 35003352 ps
CPU time 0.81 seconds
Started Dec 31 01:08:47 PM PST 23
Finished Dec 31 01:08:49 PM PST 23
Peak memory 207532 kb
Host smart-c3839ff0-fe9c-40fd-99f5-7bb91a42af9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879340307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2879340307
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_dummy_item_extra_dly.4088576334
Short name T1114
Test name
Test status
Simulation time 42190946940 ps
CPU time 321.74 seconds
Started Dec 31 01:08:48 PM PST 23
Finished Dec 31 01:14:11 PM PST 23
Peak memory 289732 kb
Host smart-4c153231-5578-49f5-aa2c-473ac16d2fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088576334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_dummy_item_extra_dly.4088576334
Directory /workspace/8.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/8.spi_device_extreme_fifo_size.901030036
Short name T913
Test name
Test status
Simulation time 99834428046 ps
CPU time 2586.87 seconds
Started Dec 31 01:08:46 PM PST 23
Finished Dec 31 01:51:54 PM PST 23
Peak memory 218036 kb
Host smart-ebd48782-4a28-47d1-85ef-9fb717b28f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901030036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_extreme_fifo_size.901030036
Directory /workspace/8.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/8.spi_device_fifo_full.1441608517
Short name T623
Test name
Test status
Simulation time 26111671095 ps
CPU time 1582.39 seconds
Started Dec 31 01:08:34 PM PST 23
Finished Dec 31 01:34:58 PM PST 23
Peak memory 270784 kb
Host smart-37991044-c0c2-419a-aace-14278664217e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441608517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_fifo_full.1441608517
Directory /workspace/8.spi_device_fifo_full/latest

Test location /workspace/coverage/default/8.spi_device_fifo_underflow_overflow.4005826052
Short name T45
Test name
Test status
Simulation time 52551549803 ps
CPU time 281.16 seconds
Started Dec 31 01:08:48 PM PST 23
Finished Dec 31 01:13:31 PM PST 23
Peak memory 349148 kb
Host smart-e3e48c0b-f065-42d1-a0c8-551cd709b83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005826052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_fifo_underflow_overfl
ow.4005826052
Directory /workspace/8.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.687380793
Short name T1007
Test name
Test status
Simulation time 36682941419 ps
CPU time 46.96 seconds
Started Dec 31 01:08:48 PM PST 23
Finished Dec 31 01:09:37 PM PST 23
Peak memory 236808 kb
Host smart-5494e420-c061-4c9f-bb89-8a82cd04ceda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687380793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.687380793
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3086152378
Short name T317
Test name
Test status
Simulation time 139838390959 ps
CPU time 255.1 seconds
Started Dec 31 01:08:36 PM PST 23
Finished Dec 31 01:12:55 PM PST 23
Peak memory 255944 kb
Host smart-1428ff56-3742-428b-849e-7ae705fd746f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086152378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3086152378
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2067872123
Short name T923
Test name
Test status
Simulation time 7642878531 ps
CPU time 97.71 seconds
Started Dec 31 01:08:36 PM PST 23
Finished Dec 31 01:10:17 PM PST 23
Peak memory 266188 kb
Host smart-322972c6-5646-4e1c-8875-dad08169d6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067872123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2067872123
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1065885824
Short name T1690
Test name
Test status
Simulation time 1652061271 ps
CPU time 9.23 seconds
Started Dec 31 01:08:47 PM PST 23
Finished Dec 31 01:08:58 PM PST 23
Peak memory 222892 kb
Host smart-e281c03a-d881-4634-9635-72aaf0e08305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065885824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1065885824
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1166777372
Short name T1203
Test name
Test status
Simulation time 12557156067 ps
CPU time 12.86 seconds
Started Dec 31 01:08:46 PM PST 23
Finished Dec 31 01:09:00 PM PST 23
Peak memory 220476 kb
Host smart-96024d0d-8acb-4d16-8bc2-5c4cf33ab986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166777372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1166777372
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_intr.1211084773
Short name T1020
Test name
Test status
Simulation time 10135896052 ps
CPU time 39.49 seconds
Started Dec 31 01:08:50 PM PST 23
Finished Dec 31 01:09:32 PM PST 23
Peak memory 221508 kb
Host smart-c297fb92-c148-4aa8-bbb3-a243114ca831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211084773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intr.1211084773
Directory /workspace/8.spi_device_intr/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.4166593172
Short name T1338
Test name
Test status
Simulation time 3279324172 ps
CPU time 11.32 seconds
Started Dec 31 01:08:48 PM PST 23
Finished Dec 31 01:09:02 PM PST 23
Peak memory 240924 kb
Host smart-84200c21-cd5c-4f6a-afdb-de4f6b9f1c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166593172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.4166593172
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1788018618
Short name T1661
Test name
Test status
Simulation time 88905928 ps
CPU time 1.04 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:08:56 PM PST 23
Peak memory 218880 kb
Host smart-b2478801-a497-484d-aa8f-cb67808ff7b2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788018618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1788018618
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1646167924
Short name T1239
Test name
Test status
Simulation time 14431674973 ps
CPU time 11.2 seconds
Started Dec 31 01:08:33 PM PST 23
Finished Dec 31 01:08:46 PM PST 23
Peak memory 241444 kb
Host smart-eaa130d5-c405-41c9-8748-aba31a50aa40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646167924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1646167924
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.228351235
Short name T944
Test name
Test status
Simulation time 43363188263 ps
CPU time 9.19 seconds
Started Dec 31 01:08:48 PM PST 23
Finished Dec 31 01:08:59 PM PST 23
Peak memory 238224 kb
Host smart-b7bec2a9-e4c1-45ab-b69f-3a97fabd0440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228351235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.228351235
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_perf.1621192896
Short name T689
Test name
Test status
Simulation time 107578897596 ps
CPU time 505.84 seconds
Started Dec 31 01:08:39 PM PST 23
Finished Dec 31 01:17:09 PM PST 23
Peak memory 257656 kb
Host smart-c7d2bc23-aee0-40fa-a6f4-4de15474596e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621192896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_perf.1621192896
Directory /workspace/8.spi_device_perf/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.1963907747
Short name T1222
Test name
Test status
Simulation time 31739237 ps
CPU time 0.71 seconds
Started Dec 31 01:08:48 PM PST 23
Finished Dec 31 01:08:51 PM PST 23
Peak memory 216640 kb
Host smart-8f00df43-73c9-4d0b-824d-3ca75a85ff1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963907747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.1963907747
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1747981386
Short name T826
Test name
Test status
Simulation time 352755167 ps
CPU time 3.94 seconds
Started Dec 31 01:08:47 PM PST 23
Finished Dec 31 01:08:53 PM PST 23
Peak memory 218712 kb
Host smart-8e08fc59-ef28-41a2-aaee-be18212f25d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1747981386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1747981386
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_rx_async_fifo_reset.1263522243
Short name T118
Test name
Test status
Simulation time 20720578 ps
CPU time 0.91 seconds
Started Dec 31 01:08:34 PM PST 23
Finished Dec 31 01:08:37 PM PST 23
Peak memory 208464 kb
Host smart-d3619524-06a9-451e-afeb-bceed74c8d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263522243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_rx_async_fifo_reset.1263522243
Directory /workspace/8.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/8.spi_device_rx_timeout.1780359689
Short name T466
Test name
Test status
Simulation time 5253220141 ps
CPU time 5.29 seconds
Started Dec 31 01:08:35 PM PST 23
Finished Dec 31 01:08:44 PM PST 23
Peak memory 216932 kb
Host smart-be7f058e-ebe5-49a1-b68b-0f4699134938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780359689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_rx_timeout.1780359689
Directory /workspace/8.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/8.spi_device_smoke.465414371
Short name T465
Test name
Test status
Simulation time 128684464 ps
CPU time 1.02 seconds
Started Dec 31 01:08:14 PM PST 23
Finished Dec 31 01:08:16 PM PST 23
Peak memory 208048 kb
Host smart-977db01a-22e3-4fee-bb34-63ca58d30ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465414371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_smoke.465414371
Directory /workspace/8.spi_device_smoke/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1688166295
Short name T43
Test name
Test status
Simulation time 93751232320 ps
CPU time 1284.05 seconds
Started Dec 31 01:08:48 PM PST 23
Finished Dec 31 01:30:15 PM PST 23
Peak memory 282656 kb
Host smart-dcc829cd-a63a-40e0-bde4-6ad73fb823d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688166295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1688166295
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1034170042
Short name T1280
Test name
Test status
Simulation time 10947169644 ps
CPU time 88.05 seconds
Started Dec 31 01:08:36 PM PST 23
Finished Dec 31 01:10:08 PM PST 23
Peak memory 222024 kb
Host smart-56bc9185-32a2-418c-970f-861836235504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034170042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1034170042
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2222538900
Short name T1110
Test name
Test status
Simulation time 10738736171 ps
CPU time 11.89 seconds
Started Dec 31 01:08:50 PM PST 23
Finished Dec 31 01:09:04 PM PST 23
Peak memory 216856 kb
Host smart-45a604b8-3176-4e00-91d3-2970b325ff48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222538900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2222538900
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.4043978365
Short name T869
Test name
Test status
Simulation time 39427416 ps
CPU time 1.31 seconds
Started Dec 31 01:08:34 PM PST 23
Finished Dec 31 01:08:37 PM PST 23
Peak memory 216872 kb
Host smart-2135c286-300c-4e1a-8040-9218835066ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043978365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.4043978365
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.153714908
Short name T483
Test name
Test status
Simulation time 57774863 ps
CPU time 1 seconds
Started Dec 31 01:08:48 PM PST 23
Finished Dec 31 01:08:51 PM PST 23
Peak memory 206880 kb
Host smart-7a4cf047-c8e4-441d-838d-2e63f53b9211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153714908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.153714908
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_tx_async_fifo_reset.1014126094
Short name T999
Test name
Test status
Simulation time 44869298 ps
CPU time 0.78 seconds
Started Dec 31 01:08:34 PM PST 23
Finished Dec 31 01:08:35 PM PST 23
Peak memory 208448 kb
Host smart-ff612fdf-201c-4973-92a3-4c72bc434899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014126094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tx_async_fifo_reset.1014126094
Directory /workspace/8.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/8.spi_device_txrx.3286664304
Short name T942
Test name
Test status
Simulation time 30689614383 ps
CPU time 211.7 seconds
Started Dec 31 01:08:50 PM PST 23
Finished Dec 31 01:12:24 PM PST 23
Peak memory 265564 kb
Host smart-1ce04218-442c-4489-921f-b224199e4930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286664304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_txrx.3286664304
Directory /workspace/8.spi_device_txrx/latest

Test location /workspace/coverage/default/8.spi_device_upload.2049943608
Short name T1526
Test name
Test status
Simulation time 8053920966 ps
CPU time 16.36 seconds
Started Dec 31 01:08:35 PM PST 23
Finished Dec 31 01:08:55 PM PST 23
Peak memory 249736 kb
Host smart-f56fb776-6554-4a7e-b102-b243b5353db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049943608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2049943608
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_abort.517923540
Short name T64
Test name
Test status
Simulation time 54399295 ps
CPU time 0.75 seconds
Started Dec 31 01:08:35 PM PST 23
Finished Dec 31 01:08:37 PM PST 23
Peak memory 206584 kb
Host smart-08c2e61a-a553-425b-bdde-7f04efbd49f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517923540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_abort.517923540
Directory /workspace/9.spi_device_abort/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2932639563
Short name T1388
Test name
Test status
Simulation time 13845077 ps
CPU time 0.72 seconds
Started Dec 31 01:08:50 PM PST 23
Finished Dec 31 01:08:53 PM PST 23
Peak memory 206492 kb
Host smart-c0f1c29d-3f7d-45c5-8fbf-08f14012076b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932639563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
932639563
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_bit_transfer.51262782
Short name T1005
Test name
Test status
Simulation time 68691376 ps
CPU time 2.12 seconds
Started Dec 31 01:08:49 PM PST 23
Finished Dec 31 01:08:54 PM PST 23
Peak memory 216876 kb
Host smart-586b71d6-a6d4-4ee4-bc34-b1272984aacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51262782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_bit_transfer.51262782
Directory /workspace/9.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/9.spi_device_byte_transfer.2063219186
Short name T544
Test name
Test status
Simulation time 67955114 ps
CPU time 2.73 seconds
Started Dec 31 01:08:50 PM PST 23
Finished Dec 31 01:08:55 PM PST 23
Peak memory 216792 kb
Host smart-6a52cc5f-b1b8-4104-8e38-1c0e465740db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063219186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_byte_transfer.2063219186
Directory /workspace/9.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3979466368
Short name T664
Test name
Test status
Simulation time 7352072991 ps
CPU time 5.99 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:09:01 PM PST 23
Peak memory 241372 kb
Host smart-3835aea2-5084-48d1-bb2b-35414d9f70cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979466368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3979466368
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1359266805
Short name T1651
Test name
Test status
Simulation time 58410998 ps
CPU time 0.79 seconds
Started Dec 31 01:08:38 PM PST 23
Finished Dec 31 01:08:43 PM PST 23
Peak memory 207544 kb
Host smart-6fbf1f1d-1038-454a-a306-1ae9cb20edba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359266805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1359266805
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_dummy_item_extra_dly.1582164681
Short name T455
Test name
Test status
Simulation time 88263440929 ps
CPU time 286.1 seconds
Started Dec 31 01:08:37 PM PST 23
Finished Dec 31 01:13:26 PM PST 23
Peak memory 281984 kb
Host smart-717abeb6-3105-4eb0-9fc0-a08b35d29ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582164681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_dummy_item_extra_dly.1582164681
Directory /workspace/9.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/9.spi_device_extreme_fifo_size.919036064
Short name T732
Test name
Test status
Simulation time 33026316183 ps
CPU time 122.49 seconds
Started Dec 31 01:08:36 PM PST 23
Finished Dec 31 01:10:41 PM PST 23
Peak memory 233048 kb
Host smart-a3279b19-3880-4852-a383-3de219115f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919036064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_extreme_fifo_size.919036064
Directory /workspace/9.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/9.spi_device_fifo_full.2395066768
Short name T795
Test name
Test status
Simulation time 201658530853 ps
CPU time 804.27 seconds
Started Dec 31 01:08:28 PM PST 23
Finished Dec 31 01:21:53 PM PST 23
Peak memory 263476 kb
Host smart-30bfbe02-682a-469c-9357-c9a53abeabff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395066768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_fifo_full.2395066768
Directory /workspace/9.spi_device_fifo_full/latest

Test location /workspace/coverage/default/9.spi_device_fifo_underflow_overflow.4087507870
Short name T1120
Test name
Test status
Simulation time 71750199302 ps
CPU time 241.9 seconds
Started Dec 31 01:08:47 PM PST 23
Finished Dec 31 01:12:50 PM PST 23
Peak memory 393596 kb
Host smart-12641fdc-e8f2-4b70-addd-8c0aca42d929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087507870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_fifo_underflow_overfl
ow.4087507870
Directory /workspace/9.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3719009000
Short name T1430
Test name
Test status
Simulation time 27343730702 ps
CPU time 113.96 seconds
Started Dec 31 01:08:49 PM PST 23
Finished Dec 31 01:10:46 PM PST 23
Peak memory 249772 kb
Host smart-81efc072-6743-4cce-9cc0-a3ede4092508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719009000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3719009000
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3726974454
Short name T1648
Test name
Test status
Simulation time 33108758782 ps
CPU time 242.56 seconds
Started Dec 31 01:08:51 PM PST 23
Finished Dec 31 01:12:56 PM PST 23
Peak memory 257988 kb
Host smart-790801ce-e621-4b4f-b9e6-c9d7b1930a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726974454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3726974454
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2662164312
Short name T714
Test name
Test status
Simulation time 1192883177 ps
CPU time 10.07 seconds
Started Dec 31 01:08:49 PM PST 23
Finished Dec 31 01:09:01 PM PST 23
Peak memory 247988 kb
Host smart-e60c70d9-317c-4692-bcc5-dcdbd8d18332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662164312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2662164312
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.666518633
Short name T1640
Test name
Test status
Simulation time 350765295 ps
CPU time 2.42 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:08:59 PM PST 23
Peak memory 224888 kb
Host smart-fdfb5de7-d4a2-44ac-ba3c-9941b534dd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666518633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.666518633
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_intr.595462697
Short name T1228
Test name
Test status
Simulation time 8208771714 ps
CPU time 35.43 seconds
Started Dec 31 01:08:34 PM PST 23
Finished Dec 31 01:09:11 PM PST 23
Peak memory 221104 kb
Host smart-8458c1bd-ac19-4ab0-8cc7-9af29ae0d720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595462697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intr.595462697
Directory /workspace/9.spi_device_intr/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1767560528
Short name T1322
Test name
Test status
Simulation time 2353306742 ps
CPU time 10.53 seconds
Started Dec 31 01:08:34 PM PST 23
Finished Dec 31 01:08:45 PM PST 23
Peak memory 218428 kb
Host smart-a6898d49-2b2c-45cf-85d9-48a7cfe6dfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767560528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1767560528
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3938234911
Short name T1226
Test name
Test status
Simulation time 88371357 ps
CPU time 1.19 seconds
Started Dec 31 01:08:35 PM PST 23
Finished Dec 31 01:08:40 PM PST 23
Peak memory 218804 kb
Host smart-243397ad-94ba-4018-85df-9ce035cc1bf6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938234911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3938234911
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.418687832
Short name T319
Test name
Test status
Simulation time 1955230895 ps
CPU time 7.79 seconds
Started Dec 31 01:08:54 PM PST 23
Finished Dec 31 01:09:07 PM PST 23
Peak memory 231196 kb
Host smart-9775d3bb-809e-41e9-a237-1ba4ad76bd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418687832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
418687832
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.202051578
Short name T1357
Test name
Test status
Simulation time 7908407044 ps
CPU time 19.57 seconds
Started Dec 31 01:08:48 PM PST 23
Finished Dec 31 01:09:09 PM PST 23
Peak memory 249516 kb
Host smart-97e24bdc-a227-41b5-89ef-8666a888d62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202051578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.202051578
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_perf.1850217344
Short name T256
Test name
Test status
Simulation time 66083935911 ps
CPU time 337.12 seconds
Started Dec 31 01:08:35 PM PST 23
Finished Dec 31 01:14:16 PM PST 23
Peak memory 251620 kb
Host smart-b5998334-2f66-405c-9ece-1f5212cc2864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850217344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_perf.1850217344
Directory /workspace/9.spi_device_perf/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.3751409922
Short name T772
Test name
Test status
Simulation time 16718054 ps
CPU time 0.72 seconds
Started Dec 31 01:08:35 PM PST 23
Finished Dec 31 01:08:39 PM PST 23
Peak memory 216720 kb
Host smart-5a86531a-50b7-4c5b-a6d3-48680c8a0565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751409922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.3751409922
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.315024330
Short name T581
Test name
Test status
Simulation time 1864954169 ps
CPU time 7.74 seconds
Started Dec 31 01:08:51 PM PST 23
Finished Dec 31 01:09:02 PM PST 23
Peak memory 234236 kb
Host smart-fb0e2c58-843a-4a68-94c4-d23a337fb81a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=315024330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.315024330
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_rx_async_fifo_reset.2877001285
Short name T1406
Test name
Test status
Simulation time 38882339 ps
CPU time 0.86 seconds
Started Dec 31 01:08:51 PM PST 23
Finished Dec 31 01:08:55 PM PST 23
Peak memory 208532 kb
Host smart-80f62104-c305-4ed8-be7b-b6980f31ad52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877001285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_rx_async_fifo_reset.2877001285
Directory /workspace/9.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/9.spi_device_rx_timeout.4207127945
Short name T1681
Test name
Test status
Simulation time 1338593670 ps
CPU time 5.65 seconds
Started Dec 31 01:08:36 PM PST 23
Finished Dec 31 01:08:45 PM PST 23
Peak memory 216776 kb
Host smart-a9520c55-9413-456d-b8fe-5bc7567ccc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207127945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_rx_timeout.4207127945
Directory /workspace/9.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/9.spi_device_smoke.4210259077
Short name T681
Test name
Test status
Simulation time 156450472 ps
CPU time 1.03 seconds
Started Dec 31 01:08:35 PM PST 23
Finished Dec 31 01:08:39 PM PST 23
Peak memory 207912 kb
Host smart-1c518e42-d80e-44ac-ab34-9c3eb5209dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210259077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_smoke.4210259077
Directory /workspace/9.spi_device_smoke/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1227332378
Short name T195
Test name
Test status
Simulation time 566931689837 ps
CPU time 1903.77 seconds
Started Dec 31 01:08:58 PM PST 23
Finished Dec 31 01:40:49 PM PST 23
Peak memory 883096 kb
Host smart-cace8900-c981-432c-8396-6cfc43121f1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227332378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1227332378
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3202877618
Short name T1675
Test name
Test status
Simulation time 4817662456 ps
CPU time 9.4 seconds
Started Dec 31 01:08:46 PM PST 23
Finished Dec 31 01:08:56 PM PST 23
Peak memory 216868 kb
Host smart-ab9178a7-5917-4abd-b741-921255c29b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202877618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3202877618
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3787533749
Short name T954
Test name
Test status
Simulation time 12813732440 ps
CPU time 21.1 seconds
Started Dec 31 01:08:52 PM PST 23
Finished Dec 31 01:09:17 PM PST 23
Peak memory 216904 kb
Host smart-31860eec-4c7b-43ce-b378-437777d3e130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787533749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3787533749
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2380526666
Short name T810
Test name
Test status
Simulation time 165674444 ps
CPU time 1.21 seconds
Started Dec 31 01:08:50 PM PST 23
Finished Dec 31 01:08:54 PM PST 23
Peak memory 216524 kb
Host smart-c9e95abd-5a17-4261-adf6-60b2bae6f6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380526666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2380526666
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3793428239
Short name T560
Test name
Test status
Simulation time 195946353 ps
CPU time 0.86 seconds
Started Dec 31 01:08:37 PM PST 23
Finished Dec 31 01:08:41 PM PST 23
Peak memory 206924 kb
Host smart-6ac49990-303e-43b3-a3d1-6a3ba917b195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793428239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3793428239
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_tx_async_fifo_reset.520115814
Short name T67
Test name
Test status
Simulation time 17756045 ps
CPU time 0.77 seconds
Started Dec 31 01:08:36 PM PST 23
Finished Dec 31 01:08:40 PM PST 23
Peak memory 208488 kb
Host smart-f1a3b0e8-2553-4b3a-987d-5728e60bedc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520115814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tx_async_fifo_reset.520115814
Directory /workspace/9.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/9.spi_device_txrx.3746216283
Short name T805
Test name
Test status
Simulation time 56071018455 ps
CPU time 257.15 seconds
Started Dec 31 01:08:35 PM PST 23
Finished Dec 31 01:12:55 PM PST 23
Peak memory 300076 kb
Host smart-9f77a318-4046-43a4-bc7f-b73e974f9f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746216283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_txrx.3746216283
Directory /workspace/9.spi_device_txrx/latest

Test location /workspace/coverage/default/9.spi_device_upload.2442686349
Short name T266
Test name
Test status
Simulation time 2918844499 ps
CPU time 8.05 seconds
Started Dec 31 01:08:49 PM PST 23
Finished Dec 31 01:09:00 PM PST 23
Peak memory 233336 kb
Host smart-13d6a8e1-97fa-42b0-8f31-5fbeecd8d982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442686349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2442686349
Directory /workspace/9.spi_device_upload/latest
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