Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.10 99.01 96.33 98.63 92.06 98.05 95.86 99.76


Total test records in report: 1786
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html

T1511 /workspace/coverage/default/26.spi_device_perf.278206913 Dec 31 01:10:34 PM PST 23 Dec 31 01:28:59 PM PST 23 202693866199 ps
T1512 /workspace/coverage/default/4.spi_device_mem_parity.3075570259 Dec 31 01:08:58 PM PST 23 Dec 31 01:09:07 PM PST 23 111002198 ps
T317 /workspace/coverage/default/8.spi_device_flash_and_tpm.3086152378 Dec 31 01:08:36 PM PST 23 Dec 31 01:12:55 PM PST 23 139838390959 ps
T1513 /workspace/coverage/default/48.spi_device_mailbox.358441103 Dec 31 01:12:14 PM PST 23 Dec 31 01:12:49 PM PST 23 16272588152 ps
T1514 /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2443414536 Dec 31 01:10:17 PM PST 23 Dec 31 01:10:46 PM PST 23 14690626056 ps
T1515 /workspace/coverage/default/40.spi_device_fifo_full.3140300728 Dec 31 01:11:54 PM PST 23 Dec 31 01:53:50 PM PST 23 85680007884 ps
T1516 /workspace/coverage/default/45.spi_device_abort.3831113547 Dec 31 01:12:14 PM PST 23 Dec 31 01:12:17 PM PST 23 41886302 ps
T1517 /workspace/coverage/default/11.spi_device_flash_all.2689216640 Dec 31 01:08:53 PM PST 23 Dec 31 01:11:16 PM PST 23 259388642305 ps
T1518 /workspace/coverage/default/42.spi_device_read_buffer_direct.1107056364 Dec 31 01:11:56 PM PST 23 Dec 31 01:12:01 PM PST 23 181470771 ps
T1519 /workspace/coverage/default/23.spi_device_tpm_rw.2719163903 Dec 31 01:10:02 PM PST 23 Dec 31 01:10:08 PM PST 23 261225501 ps
T1520 /workspace/coverage/default/7.spi_device_tx_async_fifo_reset.2878281135 Dec 31 01:08:50 PM PST 23 Dec 31 01:08:53 PM PST 23 20201744 ps
T1521 /workspace/coverage/default/2.spi_device_tpm_rw.3022742073 Dec 31 01:08:27 PM PST 23 Dec 31 01:08:34 PM PST 23 103556318 ps
T1522 /workspace/coverage/default/4.spi_device_txrx.524840879 Dec 31 01:08:56 PM PST 23 Dec 31 01:12:32 PM PST 23 22414907118 ps
T1523 /workspace/coverage/default/25.spi_device_cfg_cmd.13212584 Dec 31 01:10:22 PM PST 23 Dec 31 01:10:33 PM PST 23 73559293 ps
T1524 /workspace/coverage/default/37.spi_device_csb_read.3129374426 Dec 31 01:11:17 PM PST 23 Dec 31 01:11:22 PM PST 23 119665430 ps
T1525 /workspace/coverage/default/31.spi_device_read_buffer_direct.1493146528 Dec 31 01:10:51 PM PST 23 Dec 31 01:10:56 PM PST 23 1003087966 ps
T1526 /workspace/coverage/default/8.spi_device_upload.2049943608 Dec 31 01:08:35 PM PST 23 Dec 31 01:08:55 PM PST 23 8053920966 ps
T1527 /workspace/coverage/default/45.spi_device_mailbox.2980751296 Dec 31 01:12:17 PM PST 23 Dec 31 01:12:50 PM PST 23 7175958547 ps
T1528 /workspace/coverage/default/47.spi_device_tpm_rw.2954417898 Dec 31 01:12:12 PM PST 23 Dec 31 01:12:15 PM PST 23 417538192 ps
T1529 /workspace/coverage/default/19.spi_device_fifo_underflow_overflow.1188668690 Dec 31 01:09:37 PM PST 23 Dec 31 01:14:19 PM PST 23 12729431990 ps
T1530 /workspace/coverage/default/29.spi_device_csb_read.846880450 Dec 31 01:10:17 PM PST 23 Dec 31 01:10:25 PM PST 23 57570935 ps
T1531 /workspace/coverage/default/16.spi_device_flash_mode.1245965734 Dec 31 01:09:27 PM PST 23 Dec 31 01:10:01 PM PST 23 10106440970 ps
T1532 /workspace/coverage/default/45.spi_device_dummy_item_extra_dly.3116134108 Dec 31 01:11:40 PM PST 23 Dec 31 01:21:30 PM PST 23 61003435588 ps
T1533 /workspace/coverage/default/16.spi_device_flash_all.929104578 Dec 31 01:09:29 PM PST 23 Dec 31 01:11:07 PM PST 23 17959674954 ps
T1534 /workspace/coverage/default/33.spi_device_abort.260751884 Dec 31 01:10:49 PM PST 23 Dec 31 01:10:52 PM PST 23 40571855 ps
T1535 /workspace/coverage/default/13.spi_device_byte_transfer.1844878494 Dec 31 01:09:17 PM PST 23 Dec 31 01:09:22 PM PST 23 177720377 ps
T1536 /workspace/coverage/default/1.spi_device_perf.1672711517 Dec 31 01:07:49 PM PST 23 Dec 31 01:19:11 PM PST 23 104056026926 ps
T1537 /workspace/coverage/default/32.spi_device_cfg_cmd.1775910092 Dec 31 01:10:52 PM PST 23 Dec 31 01:11:00 PM PST 23 2823463272 ps
T1538 /workspace/coverage/default/20.spi_device_flash_and_tpm.4176791639 Dec 31 01:09:47 PM PST 23 Dec 31 01:10:32 PM PST 23 16481316501 ps
T1539 /workspace/coverage/default/44.spi_device_fifo_full.3028628872 Dec 31 01:12:14 PM PST 23 Dec 31 01:22:29 PM PST 23 144194440533 ps
T1540 /workspace/coverage/default/1.spi_device_tpm_all.3609317919 Dec 31 01:07:32 PM PST 23 Dec 31 01:08:40 PM PST 23 16559573534 ps
T295 /workspace/coverage/default/36.spi_device_flash_all.1849407036 Dec 31 01:11:13 PM PST 23 Dec 31 01:15:34 PM PST 23 109166461624 ps
T1541 /workspace/coverage/default/41.spi_device_flash_all.4096328500 Dec 31 01:12:05 PM PST 23 Dec 31 01:12:45 PM PST 23 16242492108 ps
T1542 /workspace/coverage/default/4.spi_device_cfg_cmd.2580794438 Dec 31 01:08:05 PM PST 23 Dec 31 01:08:15 PM PST 23 10827933694 ps
T1543 /workspace/coverage/default/32.spi_device_smoke.1678437172 Dec 31 01:11:13 PM PST 23 Dec 31 01:11:16 PM PST 23 81093646 ps
T1544 /workspace/coverage/default/16.spi_device_bit_transfer.1247295406 Dec 31 01:09:21 PM PST 23 Dec 31 01:09:26 PM PST 23 557027734 ps
T1545 /workspace/coverage/default/23.spi_device_tpm_all.281263288 Dec 31 01:10:16 PM PST 23 Dec 31 01:10:55 PM PST 23 3688319076 ps
T1546 /workspace/coverage/default/6.spi_device_abort.2245873861 Dec 31 01:08:34 PM PST 23 Dec 31 01:08:36 PM PST 23 14997797 ps
T1547 /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2329950702 Dec 31 01:12:19 PM PST 23 Dec 31 01:15:25 PM PST 23 48783016249 ps
T303 /workspace/coverage/default/37.spi_device_flash_and_tpm.4173116287 Dec 31 01:11:18 PM PST 23 Dec 31 01:16:28 PM PST 23 65378414676 ps
T1548 /workspace/coverage/default/20.spi_device_upload.548501604 Dec 31 01:09:37 PM PST 23 Dec 31 01:10:29 PM PST 23 16365544746 ps
T1549 /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.887347938 Dec 31 01:08:10 PM PST 23 Dec 31 01:11:35 PM PST 23 26436766544 ps
T1550 /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.918745048 Dec 31 01:10:14 PM PST 23 Dec 31 01:10:23 PM PST 23 2021415609 ps
T1551 /workspace/coverage/default/4.spi_device_dummy_item_extra_dly.1573315412 Dec 31 01:09:12 PM PST 23 Dec 31 01:13:09 PM PST 23 52766333981 ps
T1552 /workspace/coverage/default/42.spi_device_flash_all.2722124607 Dec 31 01:12:16 PM PST 23 Dec 31 01:13:58 PM PST 23 9178821336 ps
T1553 /workspace/coverage/default/19.spi_device_bit_transfer.2015745099 Dec 31 01:09:38 PM PST 23 Dec 31 01:09:45 PM PST 23 312744922 ps
T1554 /workspace/coverage/default/33.spi_device_perf.2449842172 Dec 31 01:10:55 PM PST 23 Dec 31 01:18:42 PM PST 23 18373415182 ps
T1555 /workspace/coverage/default/4.spi_device_extreme_fifo_size.3570952584 Dec 31 01:08:54 PM PST 23 Dec 31 02:05:25 PM PST 23 157550545609 ps
T1556 /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1179606556 Dec 31 01:09:37 PM PST 23 Dec 31 01:11:54 PM PST 23 69671326980 ps
T1557 /workspace/coverage/default/11.spi_device_tpm_rw.412734394 Dec 31 01:08:57 PM PST 23 Dec 31 01:09:06 PM PST 23 303698501 ps
T1558 /workspace/coverage/default/45.spi_device_perf.3470644566 Dec 31 01:11:55 PM PST 23 Dec 31 01:26:06 PM PST 23 33779397135 ps
T1559 /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.4208843444 Dec 31 01:08:46 PM PST 23 Dec 31 01:09:44 PM PST 23 76708136690 ps
T1560 /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3197853861 Dec 31 01:12:20 PM PST 23 Dec 31 01:16:18 PM PST 23 98728687424 ps
T1561 /workspace/coverage/default/13.spi_device_tx_async_fifo_reset.436512925 Dec 31 01:08:56 PM PST 23 Dec 31 01:09:03 PM PST 23 27245241 ps
T1562 /workspace/coverage/default/27.spi_device_flash_and_tpm.623537408 Dec 31 01:10:17 PM PST 23 Dec 31 01:11:59 PM PST 23 4214454237 ps
T1563 /workspace/coverage/default/33.spi_device_extreme_fifo_size.1143639596 Dec 31 01:10:52 PM PST 23 Dec 31 01:39:09 PM PST 23 181360399880 ps
T1564 /workspace/coverage/default/18.spi_device_upload.3527191834 Dec 31 01:09:40 PM PST 23 Dec 31 01:10:16 PM PST 23 37913469523 ps
T1565 /workspace/coverage/default/48.spi_device_abort.1536339998 Dec 31 01:12:19 PM PST 23 Dec 31 01:12:25 PM PST 23 14946912 ps
T1566 /workspace/coverage/default/32.spi_device_flash_all.4282552158 Dec 31 01:10:52 PM PST 23 Dec 31 01:12:21 PM PST 23 53807908093 ps
T1567 /workspace/coverage/default/20.spi_device_fifo_full.3166621426 Dec 31 01:09:39 PM PST 23 Dec 31 01:15:59 PM PST 23 61140670076 ps
T1568 /workspace/coverage/default/10.spi_device_stress_all.194824827 Dec 31 01:08:48 PM PST 23 Dec 31 02:31:26 PM PST 23 220259368656 ps
T1569 /workspace/coverage/default/37.spi_device_mailbox.4045773282 Dec 31 01:11:15 PM PST 23 Dec 31 01:11:27 PM PST 23 8284825978 ps
T1570 /workspace/coverage/default/24.spi_device_cfg_cmd.1467503146 Dec 31 01:10:00 PM PST 23 Dec 31 01:10:08 PM PST 23 2363829394 ps
T1571 /workspace/coverage/default/49.spi_device_dummy_item_extra_dly.2575596789 Dec 31 01:12:17 PM PST 23 Dec 31 01:29:49 PM PST 23 212731046802 ps
T1572 /workspace/coverage/default/18.spi_device_dummy_item_extra_dly.462407113 Dec 31 01:09:39 PM PST 23 Dec 31 01:27:51 PM PST 23 303041725201 ps
T1573 /workspace/coverage/default/30.spi_device_upload.3242974252 Dec 31 01:10:52 PM PST 23 Dec 31 01:11:03 PM PST 23 2424890233 ps
T1574 /workspace/coverage/default/47.spi_device_fifo_full.3662993087 Dec 31 01:12:20 PM PST 23 Dec 31 01:52:18 PM PST 23 43917780505 ps
T1575 /workspace/coverage/default/39.spi_device_perf.3626520126 Dec 31 01:11:15 PM PST 23 Dec 31 01:21:31 PM PST 23 113219976885 ps
T1576 /workspace/coverage/default/39.spi_device_tpm_rw.3173927809 Dec 31 01:11:19 PM PST 23 Dec 31 01:11:25 PM PST 23 43719973 ps
T1577 /workspace/coverage/default/32.spi_device_stress_all.3724599870 Dec 31 01:10:50 PM PST 23 Dec 31 01:20:13 PM PST 23 40561312176 ps
T297 /workspace/coverage/default/37.spi_device_flash_all.704253521 Dec 31 01:11:18 PM PST 23 Dec 31 01:18:52 PM PST 23 94704558185 ps
T1578 /workspace/coverage/default/30.spi_device_dummy_item_extra_dly.2632788759 Dec 31 01:10:20 PM PST 23 Dec 31 01:13:49 PM PST 23 101194185090 ps
T1579 /workspace/coverage/default/46.spi_device_extreme_fifo_size.1220393520 Dec 31 01:12:15 PM PST 23 Dec 31 01:12:51 PM PST 23 15939160216 ps
T1580 /workspace/coverage/default/42.spi_device_tpm_all.2535208926 Dec 31 01:11:43 PM PST 23 Dec 31 01:13:11 PM PST 23 12542521739 ps
T1581 /workspace/coverage/default/43.spi_device_intercept.2121125451 Dec 31 01:12:16 PM PST 23 Dec 31 01:12:36 PM PST 23 5257199827 ps
T1582 /workspace/coverage/default/22.spi_device_tpm_rw.4117982964 Dec 31 01:10:23 PM PST 23 Dec 31 01:10:33 PM PST 23 458614957 ps
T1583 /workspace/coverage/default/10.spi_device_perf.116026433 Dec 31 01:08:50 PM PST 23 Dec 31 01:16:18 PM PST 23 125302554309 ps
T1584 /workspace/coverage/default/16.spi_device_mem_parity.939790897 Dec 31 01:09:10 PM PST 23 Dec 31 01:09:12 PM PST 23 33991836 ps
T1585 /workspace/coverage/default/36.spi_device_perf.3265917331 Dec 31 01:11:44 PM PST 23 Dec 31 01:44:13 PM PST 23 32030051279 ps
T1586 /workspace/coverage/default/44.spi_device_perf.963506243 Dec 31 01:12:23 PM PST 23 Dec 31 01:55:05 PM PST 23 490953559596 ps
T1587 /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1706132795 Dec 31 01:09:36 PM PST 23 Dec 31 01:09:51 PM PST 23 3450147404 ps
T1588 /workspace/coverage/default/30.spi_device_flash_mode.1464599100 Dec 31 01:10:50 PM PST 23 Dec 31 01:11:02 PM PST 23 899845408 ps
T1589 /workspace/coverage/default/43.spi_device_extreme_fifo_size.3144687827 Dec 31 01:12:15 PM PST 23 Dec 31 01:12:57 PM PST 23 4448280730 ps
T1590 /workspace/coverage/default/25.spi_device_tpm_rw.1745235550 Dec 31 01:10:18 PM PST 23 Dec 31 01:10:26 PM PST 23 82663852 ps
T1591 /workspace/coverage/default/45.spi_device_upload.2819628511 Dec 31 01:12:16 PM PST 23 Dec 31 01:12:25 PM PST 23 190088139 ps
T1592 /workspace/coverage/default/21.spi_device_smoke.1061767258 Dec 31 01:09:40 PM PST 23 Dec 31 01:09:52 PM PST 23 171960437 ps
T1593 /workspace/coverage/default/41.spi_device_smoke.4008351151 Dec 31 01:11:15 PM PST 23 Dec 31 01:11:18 PM PST 23 38749414 ps
T1594 /workspace/coverage/default/23.spi_device_intr.2231494958 Dec 31 01:10:03 PM PST 23 Dec 31 01:10:15 PM PST 23 9065482668 ps
T1595 /workspace/coverage/default/25.spi_device_abort.2695402227 Dec 31 01:10:16 PM PST 23 Dec 31 01:10:22 PM PST 23 15664829 ps
T1596 /workspace/coverage/default/46.spi_device_flash_and_tpm.1721967708 Dec 31 01:12:06 PM PST 23 Dec 31 01:15:26 PM PST 23 23035839197 ps
T1597 /workspace/coverage/default/22.spi_device_alert_test.1163039213 Dec 31 01:10:16 PM PST 23 Dec 31 01:10:21 PM PST 23 44171441 ps
T1598 /workspace/coverage/default/39.spi_device_tx_async_fifo_reset.3417071474 Dec 31 01:11:20 PM PST 23 Dec 31 01:11:26 PM PST 23 24297332 ps
T1599 /workspace/coverage/default/4.spi_device_fifo_full.3705419510 Dec 31 01:08:53 PM PST 23 Dec 31 01:20:25 PM PST 23 41296807701 ps
T1600 /workspace/coverage/default/0.spi_device_mailbox.3185077258 Dec 31 01:07:31 PM PST 23 Dec 31 01:07:35 PM PST 23 170816016 ps
T1601 /workspace/coverage/default/14.spi_device_extreme_fifo_size.859921480 Dec 31 01:09:22 PM PST 23 Dec 31 01:12:08 PM PST 23 29126110201 ps
T1602 /workspace/coverage/default/22.spi_device_rx_timeout.3264060226 Dec 31 01:10:14 PM PST 23 Dec 31 01:10:20 PM PST 23 1516400271 ps
T1603 /workspace/coverage/default/44.spi_device_abort.390947777 Dec 31 01:11:56 PM PST 23 Dec 31 01:11:58 PM PST 23 40702884 ps
T1604 /workspace/coverage/default/43.spi_device_rx_timeout.1236204371 Dec 31 01:12:07 PM PST 23 Dec 31 01:12:14 PM PST 23 2222473131 ps
T1605 /workspace/coverage/default/36.spi_device_fifo_underflow_overflow.2712722993 Dec 31 01:11:40 PM PST 23 Dec 31 01:28:45 PM PST 23 205374585028 ps
T1606 /workspace/coverage/default/13.spi_device_flash_all.733584927 Dec 31 01:08:58 PM PST 23 Dec 31 01:10:55 PM PST 23 20194681392 ps
T1607 /workspace/coverage/default/4.spi_device_pass_cmd_filtering.623933960 Dec 31 01:08:25 PM PST 23 Dec 31 01:09:06 PM PST 23 79135794030 ps
T1608 /workspace/coverage/default/15.spi_device_flash_all.1843605011 Dec 31 01:09:17 PM PST 23 Dec 31 01:10:07 PM PST 23 6752830498 ps
T1609 /workspace/coverage/default/30.spi_device_rx_async_fifo_reset.1317200101 Dec 31 01:10:35 PM PST 23 Dec 31 01:10:45 PM PST 23 46672573 ps
T1610 /workspace/coverage/default/33.spi_device_fifo_underflow_overflow.4048172636 Dec 31 01:10:55 PM PST 23 Dec 31 01:22:51 PM PST 23 135367595522 ps
T1611 /workspace/coverage/default/48.spi_device_perf.1465225823 Dec 31 01:12:04 PM PST 23 Dec 31 01:24:05 PM PST 23 42095174679 ps
T1612 /workspace/coverage/default/14.spi_device_mem_parity.605036890 Dec 31 01:09:12 PM PST 23 Dec 31 01:09:16 PM PST 23 309796432 ps
T1613 /workspace/coverage/default/49.spi_device_intr.2912718728 Dec 31 01:12:18 PM PST 23 Dec 31 01:13:17 PM PST 23 57421084281 ps
T1614 /workspace/coverage/default/39.spi_device_flash_mode.4240365115 Dec 31 01:11:25 PM PST 23 Dec 31 01:11:48 PM PST 23 2485197811 ps
T1615 /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1729188511 Dec 31 01:10:13 PM PST 23 Dec 31 01:10:47 PM PST 23 52257348329 ps
T1616 /workspace/coverage/default/25.spi_device_txrx.1882137846 Dec 31 01:10:14 PM PST 23 Dec 31 01:18:24 PM PST 23 23158498728 ps
T1617 /workspace/coverage/default/34.spi_device_intr.3727822879 Dec 31 01:11:18 PM PST 23 Dec 31 01:11:37 PM PST 23 15755621680 ps
T1618 /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2555839694 Dec 31 01:09:35 PM PST 23 Dec 31 01:10:06 PM PST 23 32066295803 ps
T1619 /workspace/coverage/default/44.spi_device_smoke.2247878681 Dec 31 01:12:20 PM PST 23 Dec 31 01:12:26 PM PST 23 41462092 ps
T1620 /workspace/coverage/default/8.spi_device_byte_transfer.267356670 Dec 31 01:08:27 PM PST 23 Dec 31 01:08:31 PM PST 23 479284569 ps
T1621 /workspace/coverage/default/5.spi_device_mem_parity.832983158 Dec 31 01:08:02 PM PST 23 Dec 31 01:08:04 PM PST 23 80947821 ps
T1622 /workspace/coverage/default/17.spi_device_read_buffer_direct.1331215942 Dec 31 01:09:36 PM PST 23 Dec 31 01:09:41 PM PST 23 290850569 ps
T1623 /workspace/coverage/default/18.spi_device_intercept.3809312715 Dec 31 01:09:39 PM PST 23 Dec 31 01:09:50 PM PST 23 711698155 ps
T1624 /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.608752906 Dec 31 01:10:04 PM PST 23 Dec 31 01:16:59 PM PST 23 54977628379 ps
T1625 /workspace/coverage/default/15.spi_device_intr.3843963184 Dec 31 01:09:01 PM PST 23 Dec 31 01:09:14 PM PST 23 1940892511 ps
T1626 /workspace/coverage/default/38.spi_device_intr.139980463 Dec 31 01:11:14 PM PST 23 Dec 31 01:11:50 PM PST 23 31435646669 ps
T1627 /workspace/coverage/default/31.spi_device_upload.1902245482 Dec 31 01:10:53 PM PST 23 Dec 31 01:11:18 PM PST 23 28693908666 ps
T316 /workspace/coverage/default/49.spi_device_flash_all.236376039 Dec 31 01:12:18 PM PST 23 Dec 31 01:15:16 PM PST 23 195817741406 ps
T1628 /workspace/coverage/default/4.spi_device_rx_timeout.341664686 Dec 31 01:09:00 PM PST 23 Dec 31 01:09:15 PM PST 23 839536642 ps
T1629 /workspace/coverage/default/18.spi_device_rx_timeout.3244907595 Dec 31 01:09:38 PM PST 23 Dec 31 01:09:49 PM PST 23 1105636079 ps
T1630 /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.352216596 Dec 31 01:11:15 PM PST 23 Dec 31 01:11:18 PM PST 23 1932909763 ps
T1631 /workspace/coverage/default/30.spi_device_fifo_underflow_overflow.2720002971 Dec 31 01:10:19 PM PST 23 Dec 31 01:16:38 PM PST 23 81241761523 ps
T1632 /workspace/coverage/default/13.spi_device_stress_all.228445518 Dec 31 01:08:58 PM PST 23 Dec 31 01:28:35 PM PST 23 217735171412 ps
T1633 /workspace/coverage/default/17.spi_device_flash_and_tpm.2017506540 Dec 31 01:09:36 PM PST 23 Dec 31 01:14:44 PM PST 23 192167668004 ps
T1634 /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2304365403 Dec 31 01:08:48 PM PST 23 Dec 31 01:09:13 PM PST 23 7468963128 ps
T1635 /workspace/coverage/default/12.spi_device_mem_parity.2636849334 Dec 31 01:08:53 PM PST 23 Dec 31 01:08:58 PM PST 23 134817076 ps
T1636 /workspace/coverage/default/38.spi_device_upload.3636351077 Dec 31 01:11:16 PM PST 23 Dec 31 01:11:28 PM PST 23 1076897522 ps
T1637 /workspace/coverage/default/18.spi_device_tpm_sts_read.150966170 Dec 31 01:09:37 PM PST 23 Dec 31 01:09:43 PM PST 23 105830335 ps
T1638 /workspace/coverage/default/36.spi_device_smoke.2447380640 Dec 31 01:11:24 PM PST 23 Dec 31 01:11:29 PM PST 23 128297205 ps
T1639 /workspace/coverage/default/37.spi_device_dummy_item_extra_dly.3932097254 Dec 31 01:11:15 PM PST 23 Dec 31 01:19:46 PM PST 23 72921159447 ps
T1640 /workspace/coverage/default/9.spi_device_intercept.666518633 Dec 31 01:08:52 PM PST 23 Dec 31 01:08:59 PM PST 23 350765295 ps
T1641 /workspace/coverage/default/23.spi_device_alert_test.2475392858 Dec 31 01:10:13 PM PST 23 Dec 31 01:10:15 PM PST 23 10069290 ps
T1642 /workspace/coverage/default/34.spi_device_tpm_sts_read.2024388034 Dec 31 01:10:49 PM PST 23 Dec 31 01:10:52 PM PST 23 1075995919 ps
T1643 /workspace/coverage/default/44.spi_device_flash_mode.1350568704 Dec 31 01:12:04 PM PST 23 Dec 31 01:12:22 PM PST 23 8125437150 ps
T1644 /workspace/coverage/default/27.spi_device_extreme_fifo_size.3118608618 Dec 31 01:10:16 PM PST 23 Dec 31 01:11:03 PM PST 23 12569474797 ps
T1645 /workspace/coverage/default/22.spi_device_tpm_all.3581293155 Dec 31 01:10:16 PM PST 23 Dec 31 01:10:33 PM PST 23 952032866 ps
T1646 /workspace/coverage/default/34.spi_device_read_buffer_direct.2395001578 Dec 31 01:10:49 PM PST 23 Dec 31 01:10:55 PM PST 23 426151883 ps
T1647 /workspace/coverage/default/48.spi_device_rx_timeout.371337155 Dec 31 01:12:21 PM PST 23 Dec 31 01:12:34 PM PST 23 3099619298 ps
T1648 /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3726974454 Dec 31 01:08:51 PM PST 23 Dec 31 01:12:56 PM PST 23 33108758782 ps
T1649 /workspace/coverage/default/32.spi_device_tx_async_fifo_reset.2379918787 Dec 31 01:10:52 PM PST 23 Dec 31 01:10:55 PM PST 23 57096544 ps
T1650 /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1911500270 Dec 31 01:10:01 PM PST 23 Dec 31 01:10:06 PM PST 23 190593346 ps
T1651 /workspace/coverage/default/9.spi_device_csb_read.1359266805 Dec 31 01:08:38 PM PST 23 Dec 31 01:08:43 PM PST 23 58410998 ps
T1652 /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3689967509 Dec 31 01:12:08 PM PST 23 Dec 31 01:12:13 PM PST 23 250225942 ps
T1653 /workspace/coverage/default/33.spi_device_tpm_sts_read.241620567 Dec 31 01:10:49 PM PST 23 Dec 31 01:10:52 PM PST 23 161911169 ps
T1654 /workspace/coverage/default/20.spi_device_dummy_item_extra_dly.786930474 Dec 31 01:09:34 PM PST 23 Dec 31 01:18:21 PM PST 23 58419683324 ps
T1655 /workspace/coverage/default/6.spi_device_fifo_underflow_overflow.2453548279 Dec 31 01:07:59 PM PST 23 Dec 31 01:09:34 PM PST 23 47563736111 ps
T1656 /workspace/coverage/default/25.spi_device_byte_transfer.3705145186 Dec 31 01:10:16 PM PST 23 Dec 31 01:10:25 PM PST 23 822630521 ps
T1657 /workspace/coverage/default/41.spi_device_cfg_cmd.2235547021 Dec 31 01:12:12 PM PST 23 Dec 31 01:12:19 PM PST 23 1113731749 ps
T1658 /workspace/coverage/default/3.spi_device_ram_cfg.1398431823 Dec 31 01:08:06 PM PST 23 Dec 31 01:08:09 PM PST 23 35467772 ps
T1659 /workspace/coverage/default/26.spi_device_stress_all.958747767 Dec 31 01:10:18 PM PST 23 Dec 31 02:14:45 PM PST 23 128557722885 ps
T1660 /workspace/coverage/default/11.spi_device_upload.3267322676 Dec 31 01:08:59 PM PST 23 Dec 31 01:09:15 PM PST 23 6492141531 ps
T1661 /workspace/coverage/default/8.spi_device_mem_parity.1788018618 Dec 31 01:08:52 PM PST 23 Dec 31 01:08:56 PM PST 23 88905928 ps
T1662 /workspace/coverage/default/41.spi_device_extreme_fifo_size.3865248413 Dec 31 01:11:23 PM PST 23 Dec 31 01:28:39 PM PST 23 248597650953 ps
T1663 /workspace/coverage/default/49.spi_device_rx_async_fifo_reset.1422289680 Dec 31 01:12:18 PM PST 23 Dec 31 01:12:24 PM PST 23 132330667 ps
T1664 /workspace/coverage/default/35.spi_device_csb_read.3150560113 Dec 31 01:11:17 PM PST 23 Dec 31 01:11:21 PM PST 23 280068896 ps
T1665 /workspace/coverage/default/19.spi_device_tpm_all.1897035181 Dec 31 01:09:38 PM PST 23 Dec 31 01:10:23 PM PST 23 10909597285 ps
T1666 /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.711641099 Dec 31 01:10:52 PM PST 23 Dec 31 01:11:31 PM PST 23 11938043128 ps
T1667 /workspace/coverage/default/7.spi_device_fifo_underflow_overflow.1130857882 Dec 31 01:08:09 PM PST 23 Dec 31 01:19:25 PM PST 23 83504562942 ps
T1668 /workspace/coverage/default/10.spi_device_tx_async_fifo_reset.1781160236 Dec 31 01:08:59 PM PST 23 Dec 31 01:09:08 PM PST 23 17633195 ps
T1669 /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2692697121 Dec 31 01:08:48 PM PST 23 Dec 31 01:09:01 PM PST 23 9803748994 ps
T1670 /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1255230654 Dec 31 01:12:24 PM PST 23 Dec 31 01:12:55 PM PST 23 8267192263 ps
T1671 /workspace/coverage/default/36.spi_device_rx_async_fifo_reset.4191069100 Dec 31 01:11:16 PM PST 23 Dec 31 01:11:20 PM PST 23 131723820 ps
T1672 /workspace/coverage/default/24.spi_device_smoke.2008736220 Dec 31 01:10:21 PM PST 23 Dec 31 01:10:31 PM PST 23 341056176 ps
T1673 /workspace/coverage/default/32.spi_device_fifo_underflow_overflow.4006955788 Dec 31 01:10:51 PM PST 23 Dec 31 01:13:50 PM PST 23 62654988706 ps
T1674 /workspace/coverage/default/46.spi_device_intercept.2262226428 Dec 31 01:12:31 PM PST 23 Dec 31 01:12:49 PM PST 23 3987998408 ps
T1675 /workspace/coverage/default/9.spi_device_tpm_all.3202877618 Dec 31 01:08:46 PM PST 23 Dec 31 01:08:56 PM PST 23 4817662456 ps
T1676 /workspace/coverage/default/16.spi_device_smoke.3996193117 Dec 31 01:09:17 PM PST 23 Dec 31 01:09:20 PM PST 23 19295715 ps
T1677 /workspace/coverage/default/1.spi_device_abort.3130136004 Dec 31 01:07:48 PM PST 23 Dec 31 01:07:50 PM PST 23 16138824 ps
T1678 /workspace/coverage/default/19.spi_device_read_buffer_direct.2095852109 Dec 31 01:09:39 PM PST 23 Dec 31 01:09:52 PM PST 23 1085133410 ps
T1679 /workspace/coverage/default/34.spi_device_mailbox.197216179 Dec 31 01:10:50 PM PST 23 Dec 31 01:11:39 PM PST 23 31038299508 ps
T1680 /workspace/coverage/default/11.spi_device_tx_async_fifo_reset.3929835322 Dec 31 01:08:52 PM PST 23 Dec 31 01:08:56 PM PST 23 51745587 ps
T1681 /workspace/coverage/default/9.spi_device_rx_timeout.4207127945 Dec 31 01:08:36 PM PST 23 Dec 31 01:08:45 PM PST 23 1338593670 ps
T1682 /workspace/coverage/default/3.spi_device_csb_read.2578879835 Dec 31 01:08:28 PM PST 23 Dec 31 01:08:30 PM PST 23 47903467 ps
T1683 /workspace/coverage/default/2.spi_device_abort.3820475350 Dec 31 01:07:58 PM PST 23 Dec 31 01:07:59 PM PST 23 15849185 ps
T1684 /workspace/coverage/default/24.spi_device_flash_and_tpm.47293567 Dec 31 01:10:01 PM PST 23 Dec 31 01:12:39 PM PST 23 75243724636 ps
T1685 /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3907565156 Dec 31 01:09:00 PM PST 23 Dec 31 01:09:20 PM PST 23 17999091439 ps
T1686 /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1544342529 Dec 31 01:10:17 PM PST 23 Dec 31 01:10:36 PM PST 23 14785898950 ps
T1687 /workspace/coverage/default/32.spi_device_mailbox.1327486541 Dec 31 01:10:56 PM PST 23 Dec 31 01:11:13 PM PST 23 16831216272 ps
T1688 /workspace/coverage/default/47.spi_device_intercept.2146347191 Dec 31 01:12:19 PM PST 23 Dec 31 01:12:30 PM PST 23 5162387078 ps
T1689 /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.603841402 Dec 31 01:11:55 PM PST 23 Dec 31 01:12:05 PM PST 23 4116547727 ps
T1690 /workspace/coverage/default/8.spi_device_flash_mode.1065885824 Dec 31 01:08:47 PM PST 23 Dec 31 01:08:58 PM PST 23 1652061271 ps
T1691 /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3193976936 Dec 31 01:08:26 PM PST 23 Dec 31 01:08:54 PM PST 23 8705185469 ps
T1692 /workspace/coverage/default/19.spi_device_dummy_item_extra_dly.2314977477 Dec 31 01:09:35 PM PST 23 Dec 31 01:11:15 PM PST 23 25303308756 ps
T1693 /workspace/coverage/default/24.spi_device_tpm_rw.2935863834 Dec 31 01:10:18 PM PST 23 Dec 31 01:10:27 PM PST 23 124788136 ps
T1694 /workspace/coverage/default/26.spi_device_intr.69344375 Dec 31 01:10:19 PM PST 23 Dec 31 01:11:24 PM PST 23 16564064881 ps
T1695 /workspace/coverage/default/1.spi_device_fifo_full.4112234720 Dec 31 01:07:35 PM PST 23 Dec 31 01:31:11 PM PST 23 126701489045 ps
T1696 /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2121327159 Dec 31 01:10:18 PM PST 23 Dec 31 01:12:15 PM PST 23 38509094707 ps
T1697 /workspace/coverage/default/38.spi_device_tpm_sts_read.918669110 Dec 31 01:11:16 PM PST 23 Dec 31 01:11:19 PM PST 23 153846483 ps
T1698 /workspace/coverage/default/5.spi_device_fifo_full.1799850586 Dec 31 01:08:27 PM PST 23 Dec 31 01:17:24 PM PST 23 568389835946 ps
T1699 /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2215052221 Dec 31 01:09:37 PM PST 23 Dec 31 01:10:30 PM PST 23 14718216262 ps
T1700 /workspace/coverage/default/13.spi_device_fifo_underflow_overflow.955979676 Dec 31 01:09:12 PM PST 23 Dec 31 01:27:43 PM PST 23 383891704029 ps
T1701 /workspace/coverage/default/16.spi_device_alert_test.2465605479 Dec 31 01:09:11 PM PST 23 Dec 31 01:09:13 PM PST 23 27010404 ps
T1702 /workspace/coverage/default/4.spi_device_byte_transfer.2907275923 Dec 31 01:08:56 PM PST 23 Dec 31 01:09:07 PM PST 23 301738703 ps
T1703 /workspace/coverage/default/11.spi_device_extreme_fifo_size.4041588697 Dec 31 01:08:57 PM PST 23 Dec 31 01:10:15 PM PST 23 156396085653 ps
T1704 /workspace/coverage/default/43.spi_device_txrx.628569406 Dec 31 01:11:56 PM PST 23 Dec 31 01:16:34 PM PST 23 80344283053 ps
T1705 /workspace/coverage/default/1.spi_device_intercept.1096306032 Dec 31 01:08:48 PM PST 23 Dec 31 01:08:55 PM PST 23 1062628669 ps
T1706 /workspace/coverage/default/49.spi_device_txrx.2157244068 Dec 31 01:12:21 PM PST 23 Dec 31 01:16:38 PM PST 23 27254881662 ps
T1707 /workspace/coverage/default/10.spi_device_ram_cfg.818796314 Dec 31 01:09:00 PM PST 23 Dec 31 01:09:09 PM PST 23 40945385 ps
T1708 /workspace/coverage/default/4.spi_device_perf.3074104384 Dec 31 01:08:58 PM PST 23 Dec 31 01:56:31 PM PST 23 179779298088 ps
T1709 /workspace/coverage/default/10.spi_device_rx_async_fifo_reset.1458661951 Dec 31 01:08:58 PM PST 23 Dec 31 01:09:07 PM PST 23 20341856 ps
T1710 /workspace/coverage/default/33.spi_device_byte_transfer.1065583663 Dec 31 01:10:55 PM PST 23 Dec 31 01:11:01 PM PST 23 1427361011 ps
T1711 /workspace/coverage/default/37.spi_device_smoke.2578474655 Dec 31 01:11:18 PM PST 23 Dec 31 01:11:24 PM PST 23 129934201 ps
T1712 /workspace/coverage/default/19.spi_device_txrx.3179340499 Dec 31 01:09:38 PM PST 23 Dec 31 01:26:36 PM PST 23 56545036694 ps
T1713 /workspace/coverage/default/41.spi_device_flash_and_tpm.4620773 Dec 31 01:11:42 PM PST 23 Dec 31 01:22:22 PM PST 23 361439951009 ps
T1714 /workspace/coverage/default/41.spi_device_tpm_sts_read.2493347432 Dec 31 01:11:56 PM PST 23 Dec 31 01:11:58 PM PST 23 216673799 ps
T1715 /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3246959060 Dec 31 01:09:42 PM PST 23 Dec 31 01:09:59 PM PST 23 2004597131 ps
T1716 /workspace/coverage/default/48.spi_device_stress_all.470580900 Dec 31 01:12:18 PM PST 23 Dec 31 01:23:25 PM PST 23 497124933271 ps
T1717 /workspace/coverage/default/31.spi_device_tpm_sts_read.547156906 Dec 31 01:11:13 PM PST 23 Dec 31 01:11:15 PM PST 23 85423925 ps
T1718 /workspace/coverage/default/23.spi_device_abort.2869767165 Dec 31 01:10:14 PM PST 23 Dec 31 01:10:17 PM PST 23 53771538 ps
T1719 /workspace/coverage/default/21.spi_device_upload.510764766 Dec 31 01:09:40 PM PST 23 Dec 31 01:10:03 PM PST 23 2439929590 ps
T1720 /workspace/coverage/default/2.spi_device_perf.4107809563 Dec 31 01:08:24 PM PST 23 Dec 31 01:32:46 PM PST 23 228607639290 ps
T1721 /workspace/coverage/default/10.spi_device_flash_mode.2650918238 Dec 31 01:08:53 PM PST 23 Dec 31 01:09:15 PM PST 23 943138258 ps
T1722 /workspace/coverage/default/45.spi_device_read_buffer_direct.2817082181 Dec 31 01:12:08 PM PST 23 Dec 31 01:12:14 PM PST 23 975383201 ps
T1723 /workspace/coverage/default/28.spi_device_mailbox.1162146179 Dec 31 01:10:16 PM PST 23 Dec 31 01:10:46 PM PST 23 30679409959 ps
T1724 /workspace/coverage/default/4.spi_device_ram_cfg.1100637843 Dec 31 01:08:53 PM PST 23 Dec 31 01:08:58 PM PST 23 18056832 ps
T1725 /workspace/coverage/default/11.spi_device_mailbox.3930673051 Dec 31 01:08:54 PM PST 23 Dec 31 01:09:14 PM PST 23 17095851068 ps
T322 /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1715046906 Dec 31 01:09:09 PM PST 23 Dec 31 01:15:40 PM PST 23 69736019217 ps
T1726 /workspace/coverage/default/28.spi_device_tpm_all.1786165366 Dec 31 01:10:17 PM PST 23 Dec 31 01:11:50 PM PST 23 12526557401 ps
T1727 /workspace/coverage/default/14.spi_device_ram_cfg.2973557766 Dec 31 01:08:55 PM PST 23 Dec 31 01:09:02 PM PST 23 14854694 ps
T1728 /workspace/coverage/default/42.spi_device_upload.2601796685 Dec 31 01:11:41 PM PST 23 Dec 31 01:11:54 PM PST 23 3112799399 ps
T1729 /workspace/coverage/default/38.spi_device_alert_test.221583096 Dec 31 01:11:18 PM PST 23 Dec 31 01:11:23 PM PST 23 18713386 ps
T1730 /workspace/coverage/default/0.spi_device_cfg_cmd.731467536 Dec 31 01:07:32 PM PST 23 Dec 31 01:07:39 PM PST 23 570340130 ps
T1731 /workspace/coverage/default/33.spi_device_mailbox.3906264454 Dec 31 01:11:11 PM PST 23 Dec 31 01:11:18 PM PST 23 966835030 ps
T1732 /workspace/coverage/default/45.spi_device_csb_read.1913772054 Dec 31 01:11:43 PM PST 23 Dec 31 01:11:45 PM PST 23 13954403 ps
T1733 /workspace/coverage/default/21.spi_device_tpm_sts_read.3436186438 Dec 31 01:09:44 PM PST 23 Dec 31 01:09:56 PM PST 23 605173241 ps
T80 /workspace/coverage/default/0.spi_device_sec_cm.1233758142 Dec 31 01:07:33 PM PST 23 Dec 31 01:07:36 PM PST 23 36436678 ps
T1734 /workspace/coverage/default/2.spi_device_fifo_full.856308189 Dec 31 01:08:05 PM PST 23 Dec 31 01:34:26 PM PST 23 28551630741 ps
T1735 /workspace/coverage/default/42.spi_device_perf.744912636 Dec 31 01:11:54 PM PST 23 Dec 31 01:21:20 PM PST 23 27033663129 ps
T1736 /workspace/coverage/default/23.spi_device_perf.161596578 Dec 31 01:10:17 PM PST 23 Dec 31 01:22:49 PM PST 23 47549377706 ps
T1737 /workspace/coverage/default/24.spi_device_rx_timeout.4184370979 Dec 31 01:10:01 PM PST 23 Dec 31 01:10:08 PM PST 23 482674031 ps
T1738 /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2397139737 Dec 31 01:10:14 PM PST 23 Dec 31 01:10:25 PM PST 23 2968081433 ps
T1739 /workspace/coverage/default/45.spi_device_byte_transfer.2638804253 Dec 31 01:12:14 PM PST 23 Dec 31 01:12:20 PM PST 23 519542460 ps
T1740 /workspace/coverage/default/5.spi_device_intr.543960387 Dec 31 01:08:07 PM PST 23 Dec 31 01:08:57 PM PST 23 25373029404 ps
T1741 /workspace/coverage/default/42.spi_device_intercept.1042898915 Dec 31 01:12:05 PM PST 23 Dec 31 01:12:13 PM PST 23 3525516824 ps
T1742 /workspace/coverage/default/33.spi_device_tpm_all.3159977248 Dec 31 01:10:54 PM PST 23 Dec 31 01:11:13 PM PST 23 1115375252 ps
T318 /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3023840515 Dec 31 01:12:05 PM PST 23 Dec 31 01:14:26 PM PST 23 7316733073 ps
T1743 /workspace/coverage/default/2.spi_device_extreme_fifo_size.4134814134 Dec 31 01:07:58 PM PST 23 Dec 31 01:31:43 PM PST 23 42059955144 ps
T1744 /workspace/coverage/default/12.spi_device_stress_all.3061751649 Dec 31 01:08:54 PM PST 23 Dec 31 01:35:12 PM PST 23 1890258727404 ps
T1745 /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.617103617 Dec 31 01:12:08 PM PST 23 Dec 31 01:12:34 PM PST 23 32255792503 ps
T1746 /workspace/coverage/default/38.spi_device_rx_async_fifo_reset.3743694257 Dec 31 01:11:14 PM PST 23 Dec 31 01:11:17 PM PST 23 24607982 ps
T1747 /workspace/coverage/default/2.spi_device_flash_and_tpm.4267931171 Dec 31 01:08:06 PM PST 23 Dec 31 01:09:54 PM PST 23 4537396490 ps
T1748 /workspace/coverage/default/26.spi_device_rx_async_fifo_reset.3339554991 Dec 31 01:10:01 PM PST 23 Dec 31 01:10:04 PM PST 23 27628461 ps
T1749 /workspace/coverage/default/40.spi_device_mailbox.3980973647 Dec 31 01:11:18 PM PST 23 Dec 31 01:11:28 PM PST 23 906839253 ps
T1750 /workspace/coverage/default/0.spi_device_txrx.4192388685 Dec 31 01:07:30 PM PST 23 Dec 31 01:11:32 PM PST 23 51252827142 ps
T1751 /workspace/coverage/default/2.spi_device_ram_cfg.1479985865 Dec 31 01:07:47 PM PST 23 Dec 31 01:07:49 PM PST 23 43262900 ps
T1752 /workspace/coverage/default/35.spi_device_perf.2884915442 Dec 31 01:10:54 PM PST 23 Dec 31 01:57:00 PM PST 23 47925277581 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%