SPI_DEVICE Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: `a9c19f09f3`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke	1.350s	128.072us	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.450s	188.733us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.940s	499.429us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.960s	8.314ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	28.220s	13.559ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.620s	135.688us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.940s	499.429us	20	20	100.00
		spi_device_csr_aliasing	28.220s	13.559ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	13.190s	764.982us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	6.590s	209.586us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	base_random_seq	spi_device_txrx	35.804m	84.687ms	50	50	100.00
V2	fifo_full	spi_device_fifo_full	41.911m	85.680ms	50	50	100.00
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow	49.537m	177.469ms	50	50	100.00
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly	25.777m	146.754ms	50	50	100.00
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly	25.777m	146.754ms	50	50	100.00
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset	0.840s	17.633us	50	50	100.00
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset	1.000s	209.974us	49	50	98.00
V2	interrupts	spi_device_intr	2.132m	122.816ms	50	50	100.00
V2	abort	spi_device_abort	0.830s	41.886us	50	50	100.00
V2	byte_transfer_on_spi	spi_device_byte_transfer	4.150s	222.896us	50	50	100.00
V2	rx_timeout	spi_device_rx_timeout	7.200s	2.895ms	50	50	100.00
V2	bit_transfer_on_spi	spi_device_bit_transfer	3.350s	308.612us	50	50	100.00
V2	extreme_fifo_setting	spi_device_extreme_fifo_size	1.006h	614.252ms	50	50	100.00
V2	perf	spi_device_perf	47.426m	179.779ms	50	50	100.00
V2	csb_read	spi_device_csb_read	0.850s	75.841us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.190s	88.371us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	18.057us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	7.640s	1.344ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.640s	1.344ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	34.410s	23.149ms	50	50	100.00
		spi_device_tpm_sts_read	1.200s	605.173us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.350m	12.135ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	56.330s	37.396ms	50	50	100.00
		spi_device_flash_all	8.042m	110.012ms	44	50	88.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	57.410s	76.708ms	50	50	100.00
		spi_device_flash_all	8.042m	110.012ms	44	50	88.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	57.410s	76.708ms	50	50	100.00
		spi_device_flash_all	8.042m	110.012ms	44	50	88.00
V2	cmd_info_slots	spi_device_flash_all	8.042m	110.012ms	44	50	88.00
V2	cmd_read_status	spi_device_intercept	18.990s	10.360ms	50	50	100.00
		spi_device_flash_all	8.042m	110.012ms	44	50	88.00
V2	cmd_read_jedec	spi_device_intercept	18.990s	10.360ms	50	50	100.00
		spi_device_flash_all	8.042m	110.012ms	44	50	88.00
V2	cmd_read_sfdp	spi_device_intercept	18.990s	10.360ms	50	50	100.00
		spi_device_flash_all	8.042m	110.012ms	44	50	88.00
V2	cmd_fast_read	spi_device_intercept	18.990s	10.360ms	50	50	100.00
		spi_device_flash_all	8.042m	110.012ms	44	50	88.00
V2	flash_cmd_upload	spi_device_upload	48.280s	16.366ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.006m	36.175ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.006m	36.175ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.006m	36.175ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.269m	59.289ms	46	50	92.00
		spi_device_read_buffer_direct	8.590s	1.852ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.006m	36.175ms	50	50	100.00
		spi_device_flash_all	8.042m	110.012ms	44	50	88.00
V2	quad_spi	spi_device_flash_all	8.042m	110.012ms	44	50	88.00
V2	dual_spi	spi_device_flash_all	8.042m	110.012ms	44	50	88.00
V2	4b_3b_feature	spi_device_cfg_cmd	8.150s	7.423ms	49	50	98.00
V2	write_enable_disable	spi_device_cfg_cmd	8.150s	7.423ms	49	50	98.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.030m	108.476ms	45	50	90.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.479m	355.434ms	44	50	88.00
V2	stress_all	spi_device_stress_all	1.766h	271.117ms	40	50	80.00
V2	alert_test	spi_device_alert_test	0.790s	17.024us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	122.362us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.810s	276.507us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.810s	276.507us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.450s	188.733us	5	5	100.00
		spi_device_csr_rw	2.940s	499.429us	20	20	100.00
		spi_device_csr_aliasing	28.220s	13.559ms	5	5	100.00
		spi_device_same_csr_outstanding	4.390s	994.342us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.450s	188.733us	5	5	100.00
		spi_device_csr_rw	2.940s	499.429us	20	20	100.00
		spi_device_csr_aliasing	28.220s	13.559ms	5	5	100.00
		spi_device_same_csr_outstanding	4.390s	994.342us	20	20	100.00
V2		TOTAL			1647	1680	98.04
V2S	tl_intg_err	spi_device_sec_cm	1.250s	135.523us	5	5	100.00
		spi_device_tl_intg_err	21.190s	885.780us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.190s	885.780us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1786	1820	98.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	36	36	29	80.56
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.10	99.01	96.33	98.63	92.06	98.05	95.86	99.76

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: * has 14 failures:

Test spi_device_flash_and_tpm has 2 failures.

1.spi_device_flash_and_tpm.37962023940528818451683952691045344664924682514052293961657555006522154904706
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 17574040948 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_ERROR @ 17598272008 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_ERROR @ 17602579752 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_ERROR @ 18240279712 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 18735918575 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/14

19.spi_device_flash_and_tpm.47987695230800647750420934678671429723947407649041735250283757151270657770490
Line 262, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/19.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 1980757436 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 2226512004 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 8/16
  UVM_INFO @ 2456254548 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/16
  UVM_INFO @ 2655726951 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/16
  UVM_INFO @ 2888591861 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/16

Test spi_device_stress_all has 5 failures.

4.spi_device_stress_all.27624645781270352501192216671241002422340874709696909320716777325036057170517
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/4.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 81697390780 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 82140922044 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 14/16
  UVM_ERROR @ 82259870780 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 82435910780 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 17/17
  UVM_INFO @ 83204490010 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 15/16

11.spi_device_stress_all.102030276344231010482844058173858712940671455122321561614818474371299736262478
Line 377, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/11.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 220190875350 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 226421213163 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 12/20
  UVM_INFO @ 227169263694 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 13/20
  UVM_INFO @ 228830653778 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 14/20
  UVM_INFO @ 230529647427 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 15/20

... and 3 more failures.

Test spi_device_flash_and_tpm_min_idle has 2 failures.

23.spi_device_flash_and_tpm_min_idle.50924277953346551995766596486839106192956472544816063013288535817469176849161
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 10858037816 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_ERROR @ 11897684576 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  "../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv", 193: tb.dut.u_readcmd.u_readsram.u_sram_fifo.DataKnown_A: started at 11903476510ps failed at 11903476510ps
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 11903476510 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A

34.spi_device_flash_and_tpm_min_idle.14163957756349787995522688529865324890531991580836481420357046367886131385618
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 1912436870 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 2608229968 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 5/15
  UVM_INFO @ 2628175671 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 4/18
  UVM_INFO @ 3356493495 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 6/15
  UVM_INFO @ 3359507883 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 5/18

Test spi_device_flash_all has 4 failures.

26.spi_device_flash_all.43513843771595269952732447579084662273398157949712699250882158957844556707929
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/26.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 1667798016 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 1667889150 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 7/18
  UVM_INFO @ 1892163658 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 8/18
  UVM_INFO @ 2194363759 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 9/18
  UVM_INFO @ 2488438127 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 10/18

31.spi_device_flash_all.31455341047833222387110640182256299675211160703325404575981964427920180981371
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/31.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 3226760447 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 3228239615 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 3/11
  UVM_INFO @ 4523122118 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 4/11
  UVM_INFO @ 5336439036 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 5/11
  UVM_ERROR @ 5977032449 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0

... and 2 more failures.

Test spi_device_cfg_cmd has 1 failures.

30.spi_device_cfg_cmd.60699205202785373430301637695105147946602357673139498371717012695771867874719
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/30.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 521448919 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 523888919 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 4, test op = 0x6
  UVM_INFO @ 555288919 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 5, test op = 0x4
  UVM_INFO @ 669288919 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 6, test op = 0x4
  UVM_INFO @ 673528919 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 7, test op = 0x6

UVM_ERROR (spi_device_scoreboard.sv:1085) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 3 failures:
- Test spi_device_flash_mode has 3 failures.
  - 14.spi_device_flash_mode.112209648510351353012046587670409833458105854028403272706090833212838959089154
    Line 248, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/14.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 897226785 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 982935764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.spi_device_flash_mode.101479863230314811926787940497713179226312238793076226511705505274385749178032
    Line 248, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/35.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 3071242894 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 7059562894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (spi_device_scoreboard.sv:436) scoreboard [scoreboard] Compare TPM reg failed, offset: *, act: *, exp: '{*} has 2 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

5.spi_device_flash_and_tpm_min_idle.88991627699776368344780811891607300810848343377065166846267533828402382177905
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @  22104572 ps: (spi_device_scoreboard.sv:436) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare TPM reg failed, offset: 1, act: 0x4ba0c5, exp: '{'hffffff}
  UVM_FATAL @  64902719 ps: (spi_device_scoreboard.sv:1165) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @  64902719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_flash_and_tpm has 1 failures.

15.spi_device_flash_and_tpm.109316742285511647429599900051677827386725067537376709412688942305369666337175
Line 271, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/15.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 10136477899 ps: (spi_device_scoreboard.sv:436) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare TPM reg failed, offset: 0, act: 0x7e60f1ff, exp: '{'hffffffff}
  UVM_FATAL @ 10205150791 ps: (spi_device_scoreboard.sv:1165) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 10205150791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job spi_device-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test spi_device_stress_all has 2 failures.
  - 36.spi_device_stress_all.70588605347232712278187193234484012580869309339801410291755377192714569328902
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/36.spi_device_stress_all/latest/run.log
```
  Job ID: smart:cf804673-9025-4c98-b496-6d7afeb1f379
```
  - 40.spi_device_stress_all.84408432289319797581004590028615425335443389764343814938973765734240638473313
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/40.spi_device_stress_all/latest/run.log
```
  Job ID: smart:b980dcb4-b637-4477-a6c6-e6f1d59c3db6
```

UVM_ERROR (spi_device_scoreboard.sv:497) scoreboard [scoreboard] flash_status mismatch, backdoor value: *, exp: * has 2 failures:

Test spi_device_flash_all has 1 failures.

44.spi_device_flash_all.30929537771133854377713784426878083588436696136466856005372490652781141945372
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/44.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 105594983708 ps: (spi_device_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0xadf19e, exp: 0x364b52
  UVM_ERROR @ 105594983708 ps: (spi_device_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0xadf19e, exp: 0x364b52
  UVM_INFO @ 110056638073 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 8/14
  UVM_INFO @ 127634686326 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 9/14
  UVM_INFO @ 131805023093 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 10/14

Test spi_device_flash_and_tpm_min_idle has 1 failures.

47.spi_device_flash_and_tpm_min_idle.99846693982852821680953944657400778263477919979837898871824816662050261049568
Line 263, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 6853393139 ps: (spi_device_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0x84e7ea, exp: 0x84e7e8
  UVM_INFO @ 7280591278 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 9/17
  UVM_INFO @ 8688234739 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 10/17
  UVM_INFO @ 9672958815 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 11/17
  UVM_ERROR @ 10240803893 ps: (spi_device_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0xce7d02, exp: 0xce7d00

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_stress_all has 1 failures.

0.spi_device_stress_all.17763262683159224455833763495913248214159870690817297641149855246266420755953
Line 268, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 9162802194 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2a735e) != exp '{'{other_status:'h1fa41e, wel:'h1, busy:'h0}, '{other_status:'h1ed4c1, wel:'h0, busy:'h0}}
  UVM_INFO @ 9314458194 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/19
  UVM_INFO @ 10176590194 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/19
  UVM_INFO @ 10583422194 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 11/13
  UVM_INFO @ 10761583194 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 12/19

UVM_ERROR (cip_base_vseq.sv:365) [spi_device_intr_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 1 failures:

Test spi_device_stress_all has 1 failures.

1.spi_device_stress_all.69773595120542617800437056813890004239687508645006781289537486446982644327671
Line 283, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 215193869221 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 215193956177 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 215196956159 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.rxf_empty reset value: 0x1
  UVM_ERROR @ 215198006644 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 16 [0x10])
  UVM_ERROR @ 215198130065 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16 [0x10]) Regname: spi_device_reg_block.intr_state reset value: 0x0

UVM_ERROR (spi_device_pass_base_vseq.sv:641) [spi_device_flash_all_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_all has 1 failures.

2.spi_device_flash_all.80747946734062454656178011389334138068518279739534493090798799283666863688866
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/2.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 427553557 ps: (spi_device_pass_base_vseq.sv:641) [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 666104070 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 1/8
  UVM_INFO @ 1443989038 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 2/8
  UVM_INFO @ 1913189124 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 3/8
  UVM_INFO @ 2225163247 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 4/8

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'addr_4b_en' while register 'spi_device_reg_block.cfg' is being accessed has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

3.spi_device_flash_and_tpm.27417079974639716952869029702014143322897952554303937530057987457969932095971
Line 272, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/3.spi_device_flash_and_tpm/latest/run.log

  UVM_WARNING @ 190505570618 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'addr_4b_en' while register 'spi_device_reg_block.cfg' is being accessed
  UVM_INFO @ 191075478166 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 12/15
  UVM_INFO @ 192912802935 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 13/15
  UVM_INFO @ 194627608831 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 14/15
  UVM_INFO @ 195630821946 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 15/15

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test spi_device_csr_mem_rw_with_rand_reset has 1 failures.

4.spi_device_csr_mem_rw_with_rand_reset.64052266131603851137417567943519529226156175899871646017505124398366200529482
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest/run.log

  [make]: simulate
  cd /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115966538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.115966538
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Dec 31 12:49 2023
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

Offending '(!$isunknown(rdata_o))' has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

21.spi_device_flash_and_tpm_min_idle.74140786335966712039921615586373824791065189795436572462207919276007917686127
Line 270, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest/run.log

      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 51298562496 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  "../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv", 193: tb.dut.u_readcmd.u_readsram.u_sram_fifo.DataKnown_A: started at 51298624350ps failed at 51298624350ps
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 51298624350 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A

UVM_ERROR (spi_device_scoreboard.sv:1395) [scoreboard] Check failed rx_word_q.size == * (* [*] vs * [*]) has 1 failures:
- Test spi_device_rx_async_fifo_reset has 1 failures.
  - 24.spi_device_rx_async_fifo_reset.106944511314245758867225428941380287110067383669131153982676552705913473711427
    Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/24.spi_device_rx_async_fifo_reset/latest/run.log
```
  UVM_ERROR @ 141425069 ps: (spi_device_scoreboard.sv:1395) [uvm_test_top.env.scoreboard] Check failed rx_word_q.size == 0 (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 141425069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:1085) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp * has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

25.spi_device_flash_and_tpm.101670972534430744882546310700346343679880759717140667629466092496416770427242
Line 266, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/25.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 77741760123 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 80343252015 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/15
  UVM_INFO @ 84049597415 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 8/18
  UVM_INFO @ 85035946667 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 12/15
  UVM_INFO @ 89887224183 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 9/18

UVM_ERROR (spi_device_pass_base_vseq.sv:641) [flash_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

28.spi_device_flash_and_tpm_min_idle.103548601105287179705278827614661319952569508842581488792587091550309482374844
Line 276, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 16860410217 ps: (spi_device_pass_base_vseq.sv:641) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 16898523227 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 12/17
  UVM_INFO @ 17801394991 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 13/17
  UVM_INFO @ 18475052761 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 14/17
  UVM_INFO @ 19596703503 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 15/17

UVM_FATAL (spi_device_scoreboard.sv:890) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 41.spi_device_flash_mode.18685526567127291339900463864758591097963371574668430695314735161048281842869
    Line 248, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/41.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 11101648726 ps: (spi_device_scoreboard.sv:890) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 11101648726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (spi_device_base_vseq.sv:398) [spi_device_intr_vseq] wait_for_tx_avail_bytes::SramSpaceAvail has 1 failures:
- Test spi_device_stress_all has 1 failures.
  - 43.spi_device_stress_all.101569259987077878123345228238513375884044956816383919542949027310683255745064
    Line 266, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/43.spi_device_stress_all/latest/run.log
```
  UVM_FATAL @ 34772236727 ps: (spi_device_base_vseq.sv:398) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] wait_for_tx_avail_bytes::SramSpaceAvail
  UVM_INFO @ 34772236727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```