Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : spid_csb_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_spid_csb_sync 95.24 100.00 100.00 85.71
tb.dut.u_upload.u_sys_cmdfifo_set 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_spid_csb_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 100.00 100.00 85.71


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 100.00 90.91


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.69 94.25 84.31 96.94 87.50 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_count_sync 100.00 100.00 100.00


Module Instance : tb.dut.u_upload.u_sys_cmdfifo_set

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.37 100.00 86.11 100.00 95.74 100.00 u_upload


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_count_sync 100.00 100.00 100.00

Line Coverage for Module : spid_csb_sync
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS3244100.00
ALWAYS4433100.00
ALWAYS6333100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 1 1
33 1 1
35 1 1
36 1 1
MISSING_ELSE
44 1 1
45 1 1
47 1 1
63 1 1
64 1 1
66 1 1
70 1 1

Cond Coverage for Module : spid_csb_sync
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       70
 EXPRESSION (sys_toggle != sys_toggle_last)
            ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5
Branch Coverage for Module : spid_csb_sync
Line No.TotalCoveredPercent
Branches 7 7 100.00
IF 32 3 3 100.00
IF 44 2 2 100.00
IF 63 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	35	if (sck_pulse_en_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	44	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4 



	LineNo.	Expression
-1-:	63	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_csb_sync
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS3244100.00
ALWAYS4433100.00
ALWAYS6333100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 1 1
33 1 1
35 1 1
36 1 1
==> MISSING_ELSE
44 1 1
45 1 1
47 1 1
63 1 1
64 1 1
66 1 1
70 1 1

Cond Coverage for Instance : tb.dut.u_spid_csb_sync
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       70
 EXPRESSION (sys_toggle != sys_toggle_last)
            ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5
Branch Coverage for Instance : tb.dut.u_spid_csb_sync
Line No.TotalCoveredPercent
Branches 7 6 85.71
IF 32 3 2 66.67
IF 44 2 2 100.00
IF 63 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	35	if (sck_pulse_en_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered 



	LineNo.	Expression
-1-:	44	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4 



	LineNo.	Expression
-1-:	63	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS3244100.00
ALWAYS4433100.00
ALWAYS6333100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 1 1
33 1 1
35 1 1
36 1 1
MISSING_ELSE
44 1 1
45 1 1
47 1 1
63 1 1
64 1 1
66 1 1
70 1 1

Cond Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       70
 EXPRESSION (sys_toggle != sys_toggle_last)
            ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T7,T9
Branch Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set
Line No.TotalCoveredPercent
Branches 7 7 100.00
IF 32 3 3 100.00
IF 44 2 2 100.00
IF 63 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	35	if (sck_pulse_en_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T5,T7,T9
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	44	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4 



	LineNo.	Expression
-1-:	63	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%