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Module Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.17 86.36 42.31 60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.09 82.50 42.31 55.56 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
78.16 94.03 62.07 70.83 85.71 u_tlul2sram_egress


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 63.89 77.78 50.00


Module Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.60 90.91 41.18 58.33 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.29 85.00 41.18 55.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
78.16 94.03 62.07 70.83 85.71 u_tlul2sram_egress


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 63.89 77.78 50.00


Module Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.77 100.00 73.08 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.85 95.00 73.08 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.09 94.03 75.00 83.33 100.00 u_tlul2sram_ingress


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.94 88.89 75.00


Module Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.81 100.00 69.23 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.89 95.00 69.23 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.09 94.03 75.00 83.33 100.00 u_tlul2sram_ingress


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.94 88.89 75.00


Module Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.03 100.00 76.47 91.67 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.12 95.00 76.47 85.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.09 94.03 75.00 83.33 100.00 u_tlul2sram_ingress


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.94 88.89 75.00


Module Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.85 100.00 65.38 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.96 100.00 65.38 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_sys_sram_arbiter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00

Go back
Module Instances:
tb.dut.u_tlul2sram_egress.u_sramreqfifo
tb.dut.u_tlul2sram_egress.u_rspfifo
tb.dut.u_tlul2sram_ingress.u_reqfifo
tb.dut.u_tlul2sram_ingress.u_sramreqfifo
tb.dut.u_tlul2sram_ingress.u_rspfifo
tb.dut.u_sys_sram_arbiter.u_req_fifo
Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL221986.36
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN154100.00
ALWAYS1572150.00
CONT_ASSIGN175100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 0 1
157 1 1
158 0 1
MISSING_ELSE
175 0 1
176 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
TotalCoveredPercent
Conditions261142.31
Logical261142.31
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111Not Covered

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 10 6 60.00
TERNARY 88 3 1 33.33
TERNARY 180 2 1 50.00
IF 70 3 3 100.00
IF 165 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1203785710 0 0 0
DepthKnown_A 1203785710 1203617844 0 0
RvalidKnown_A 1203785710 1203617844 0 0
WreadyKnown_A 1203785710 1203617844 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 1203785710 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1203617844 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1203617844 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1203617844 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 0 0 0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo
Line No.TotalCoveredPercent
TOTAL222090.91
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN154100.00
ALWAYS1572150.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 0 1
157 1 1
158 0 1
MISSING_ELSE
172 1 1
173 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo
TotalCoveredPercent
Conditions341441.18
Logical341441.18
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111Not Covered

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo
Line No.TotalCoveredPercent
Branches 12 7 58.33
TERNARY 88 3 1 33.33
TERNARY 172 2 1 50.00
TERNARY 180 2 1 50.00
IF 70 3 3 100.00
IF 157 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 172 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 157 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1203785710 0 0 0
DepthKnown_A 1203785710 1203617844 0 0
RvalidKnown_A 1203785710 1203617844 0 0
WreadyKnown_A 1203785710 1203617844 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 1203785710 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1203617844 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1203617844 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1203617844 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 0 0 0

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15411100.00
ALWAYS15722100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 1 1
157 1 1
158 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo
TotalCoveredPercent
Conditions261973.08
Logical261973.08
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T7,T9

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT5,T7,T9

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT7,T9,T11
110Not Covered
111CoveredT5,T7,T9

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT5,T7,T9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T7,T9

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T7,T9

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT5,T7,T9
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo
Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 88 3 2 66.67
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 165 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T5,T7,T9
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T7,T9


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T5,T7,T9
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1203785710 1032242 0 0
DepthKnown_A 1203785710 1203617844 0 0
RvalidKnown_A 1203785710 1203617844 0 0
WreadyKnown_A 1203785710 1203617844 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 1203785710 1032242 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1032242 0 0
T5 405811 795 0 0
T6 1762 0 0 0
T7 232174 3224 0 0
T8 365507 0 0 0
T9 127203 1831 0 0
T10 42843 0 0 0
T11 664506 4579 0 0
T12 68526 0 0 0
T13 131303 0 0 0
T14 0 5542 0 0
T15 0 1086 0 0
T16 0 512 0 0
T23 0 224 0 0
T24 0 59 0 0
T25 0 415 0 0
T26 15735 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1203617844 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1203617844 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1203617844 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1032242 0 0
T5 405811 795 0 0
T6 1762 0 0 0
T7 232174 3224 0 0
T8 365507 0 0 0
T9 127203 1831 0 0
T10 42843 0 0 0
T11 664506 4579 0 0
T12 68526 0 0 0
T13 131303 0 0 0
T14 0 5542 0 0
T15 0 1086 0 0
T16 0 512 0 0
T23 0 224 0 0
T24 0 59 0 0
T25 0 415 0 0
T26 15735 0 0 0

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15411100.00
ALWAYS15722100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 1 1
157 1 1
158 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo
TotalCoveredPercent
Conditions261869.23
Logical261869.23
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T7,T9

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT5,T7,T9

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT5,T7,T9

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT5,T7,T9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T7,T9

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T7,T9

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT5,T7,T9
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 88 3 2 66.67
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 165 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T5,T7,T9
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T7,T9


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T5,T7,T9
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1203785710 423299 0 0
DepthKnown_A 1203785710 1203617844 0 0
RvalidKnown_A 1203785710 1203617844 0 0
WreadyKnown_A 1203785710 1203617844 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 1203785710 423299 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 423299 0 0
T5 405811 795 0 0
T6 1762 0 0 0
T7 232174 1036 0 0
T8 365507 0 0 0
T9 127203 417 0 0
T10 42843 0 0 0
T11 664506 993 0 0
T12 68526 0 0 0
T13 131303 0 0 0
T14 0 1197 0 0
T15 0 1086 0 0
T16 0 512 0 0
T23 0 224 0 0
T24 0 59 0 0
T25 0 125 0 0
T26 15735 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1203617844 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1203617844 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1203617844 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 423299 0 0
T5 405811 795 0 0
T6 1762 0 0 0
T7 232174 1036 0 0
T8 365507 0 0 0
T9 127203 417 0 0
T10 42843 0 0 0
T11 664506 993 0 0
T12 68526 0 0 0
T13 131303 0 0 0
T14 0 1197 0 0
T15 0 1086 0 0
T16 0 512 0 0
T23 0 224 0 0
T24 0 59 0 0
T25 0 125 0 0
T26 15735 0 0 0

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15411100.00
ALWAYS15722100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 1 1
157 1 1
158 1 1
MISSING_ELSE
172 1 1
173 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo
TotalCoveredPercent
Conditions342676.47
Logical342676.47
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T9,T11

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT5,T7,T9

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT7,T9,T11
110Not Covered
111CoveredT5,T7,T9

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT7,T9,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T7,T9

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T9,T11

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T7,T9

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT5,T7,T9

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT7,T9,T11
10CoveredT5,T7,T9
11CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT5,T7,T9
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo
Line No.TotalCoveredPercent
Branches 12 11 91.67
TERNARY 88 3 2 66.67
TERNARY 172 2 2 100.00
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 157 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T7,T9,T11
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 172 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T5,T7,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T7,T9


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 157 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T5,T7,T9
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1203785710 1032242 0 0
DepthKnown_A 1203785710 1203617844 0 0
RvalidKnown_A 1203785710 1203617844 0 0
WreadyKnown_A 1203785710 1203617844 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 1203785710 1032242 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1032242 0 0
T5 405811 795 0 0
T6 1762 0 0 0
T7 232174 3224 0 0
T8 365507 0 0 0
T9 127203 1831 0 0
T10 42843 0 0 0
T11 664506 4579 0 0
T12 68526 0 0 0
T13 131303 0 0 0
T14 0 5542 0 0
T15 0 1086 0 0
T16 0 512 0 0
T23 0 224 0 0
T24 0 59 0 0
T25 0 415 0 0
T26 15735 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1203617844 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1203617844 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1203617844 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1032242 0 0
T5 405811 795 0 0
T6 1762 0 0 0
T7 232174 3224 0 0
T8 365507 0 0 0
T9 127203 1831 0 0
T10 42843 0 0 0
T11 664506 4579 0 0
T12 68526 0 0 0
T13 131303 0 0 0
T14 0 5542 0 0
T15 0 1086 0 0
T16 0 512 0 0
T23 0 224 0 0
T24 0 59 0 0
T25 0 415 0 0
T26 15735 0 0 0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS16522100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo
TotalCoveredPercent
Conditions261765.38
Logical261765.38
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT5,T7,T9
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT5,T7,T9
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT5,T7,T9

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT5,T7,T9

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T7,T9

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT5,T7,T9
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo
Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 88 3 2 66.67
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 165 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T5,T7,T9


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T7,T9


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T5,T7,T9
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1203785710 431531 0 0
DepthKnown_A 1203785710 1203617844 0 0
RvalidKnown_A 1203785710 1203617844 0 0
WreadyKnown_A 1203785710 1203617844 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 1203785710 431531 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 431531 0 0
T5 405811 832 0 0
T6 1762 0 0 0
T7 232174 1085 0 0
T8 365507 0 0 0
T9 127203 430 0 0
T10 42843 0 0 0
T11 664506 1036 0 0
T12 68526 0 0 0
T13 131303 0 0 0
T14 0 1218 0 0
T15 0 1146 0 0
T16 0 545 0 0
T23 0 236 0 0
T24 0 59 0 0
T25 0 133 0 0
T26 15735 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1203617844 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1203617844 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 1203617844 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 1203785710 431531 0 0
T5 405811 832 0 0
T6 1762 0 0 0
T7 232174 1085 0 0
T8 365507 0 0 0
T9 127203 430 0 0
T10 42843 0 0 0
T11 664506 1036 0 0
T12 68526 0 0 0
T13 131303 0 0 0
T14 0 1218 0 0
T15 0 1146 0 0
T16 0 545 0 0
T23 0 236 0 0
T24 0 59 0 0
T25 0 133 0 0
T26 15735 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%