Module Definition
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Module : spid_dpram
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 75.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_dpram.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_spid_dpram 91.67 100.00 75.00 100.00



Module Instance : tb.dut.u_spid_dpram

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 75.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 75.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.69 94.25 84.31 96.94 87.50 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_ram1r1w.u_spi2sys_mem 100.00 100.00 100.00
gen_ram1r1w.u_sys2spi_mem 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : spid_dpram
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN9111100.00
CONT_ASSIGN9211100.00
ALWAYS10377100.00
ALWAYS11833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_dpram.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_dpram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
64 1 1
65 1 1
70 1 1
71 1 1
83 1 1
84 1 1
91 1 1
92 1 1
103 1 1
105 1 1
106 1 1
108 1 1
110 1 1
111 1 1
113 1 1
MISSING_ELSE
118 1 1
119 1 1
121 1 1


Cond Coverage for Module : spid_dpram
TotalCoveredPercent
Conditions161275.00
Logical161275.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION ((sys_addr_i < Sys2SpiEnd) & sys_req_i & sys_write_i)
             ------------1------------   ----2----   -----3-----
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT1,T2,T5

 LINE       70
 EXPRESSION (spi_req_i & ((!spi_write_i)))
             ----1----   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T7,T9
11CoveredT1,T2,T5

 LINE       83
 EXPRESSION (spi_req_i & spi_write_i)
             ----1----   -----2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T5
11CoveredT5,T7,T9

 LINE       91
 EXPRESSION (sys_req_i & ((!sys_write_i)))
             ----1----   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T5
11CoveredT5,T7,T9

 LINE       108
 EXPRESSION (spi2sys_wr_req && ((!initialized_words_q[7'(spi2sys_wr_addr)])))
             -------1------    ----------------------2----------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T7,T9
11CoveredT5,T7,T9

Branch Coverage for Module : spid_dpram
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 108 2 2 100.00
IF 118 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_dpram.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_dpram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 108 if ((spi2sys_wr_req && (!initialized_words_q[7'(spi2sys_wr_addr)])))

Branches:
-1-StatusTests
1 Covered T5,T7,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 118 if ((!rst_spi_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%