Module Definition
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Module : prim_ram_1r1w_async_adv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem 100.00 100.00 100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem 100.00 100.00 100.00


Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.67 100.00 75.00 100.00 u_spid_dpram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_mem 100.00 100.00 100.00


Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.67 100.00 75.00 100.00 u_spid_dpram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_mem 100.00 100.00 100.00

Line Coverage for Module : prim_ram_1r1w_async_adv
Line No.TotalCoveredPercent
TOTAL2828100.00
ALWAYS11833100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
ALWAYS18088100.00
CONT_ASSIGN20311100.00
CONT_ASSIGN23411100.00
CONT_ASSIGN23511100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23711100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN24011100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN26111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' or '../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
118 1 1
119 1 1
121 1 1
125 1 1
126 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
180 1 1
181 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
193 1 1
203 1 1
234 1 1
235 1 1
236 1 1
237 1 1
239 1 1
240 1 1
258 1 1
259 1 1
261 1 1

Branch Coverage for Module : prim_ram_1r1w_async_adv
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 118 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' or '../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	118	if ((!rst_b_ni))

Branches:
-1-StatusTests
1 Covered T3,T4,T7
0 Covered T3,T4,T7

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem
Line No.TotalCoveredPercent
TOTAL2828100.00
ALWAYS11833100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
ALWAYS18088100.00
CONT_ASSIGN20311100.00
CONT_ASSIGN23411100.00
CONT_ASSIGN23511100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23711100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN24011100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN26111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' or '../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
118 1 1
119 1 1
121 1 1
125 1 1
126 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
180 1 1
181 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
193 1 1
203 1 1
234 1 1
235 1 1
236 1 1
237 1 1
239 1 1
240 1 1
258 1 1
259 1 1
261 1 1

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 118 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' or '../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	118	if ((!rst_b_ni))

Branches:
-1-StatusTests
1 Covered T3,T4,T7
0 Covered T3,T7,T10

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem
Line No.TotalCoveredPercent
TOTAL2828100.00
ALWAYS11833100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
ALWAYS18088100.00
CONT_ASSIGN20311100.00
CONT_ASSIGN23411100.00
CONT_ASSIGN23511100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23711100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN24011100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN26111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' or '../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
118 1 1
119 1 1
121 1 1
125 1 1
126 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
180 1 1
181 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
193 1 1
203 1 1
234 1 1
235 1 1
236 1 1
237 1 1
239 1 1
240 1 1
258 1 1
259 1 1
261 1 1

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 118 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' or '../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	118	if ((!rst_b_ni))

Branches:
-1-StatusTests
1 Covered T3,T4,T7
0 Covered T3,T4,T7

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%