Unified Coverage Report :: Module :: spid_readsram

Module : spid_readsram

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.77	98.25	100.00		100.00	90.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_readsram.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_readcmd.u_readsram	97.77	98.25	100.00		100.00	90.62	100.00

---

Module Instance : tb.dut.u_readcmd.u_readsram

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.77	98.25	100.00		100.00	90.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.94	97.81	85.71		100.00	91.18	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.19	96.32	100.00		80.00	84.62	100.00	u_readcmd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_fifo	96.88	100.00	87.50			100.00	100.00
u_sram_fifo	88.33	95.00	75.00			83.33	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spid_readsram

	Line No.	Total	Covered	Percent
TOTAL		57	56	98.25
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
ALWAYS	166	4	4	100.00
ALWAYS	172	6	6	100.00
ALWAYS	179	5	5	100.00
CONT_ASSIGN	189	1	1	100.00
ALWAYS	195	5	5	100.00
ALWAYS	225	3	3	100.00
ALWAYS	230	26	25	96.15
CONT_ASSIGN	346	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_readsram.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_readsram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
118	1	1
123	1	1
129	1	1
146	1	1
160	1	1
161	1	1
166	2	2
167	2	2
			MISSING_ELSE
172	2	2
173	2	2
174	2	2
			MISSING_ELSE
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
189	1	1
195	1	1
196	1	1
197	1	1
198	1	1
200	1	1
225	2	2
226	1	1
230	1	1
232	1	1
234	1	1
235	1	1
237	1	1
238	1	1
240	1	1
242	1	1
244	1	1
245	1	1
			MISSING_ELSE
248	1	1
251	1	1
253	1	1
258	1	1
259	1	1
			MISSING_ELSE
262	2	2
			MISSING_ELSE
264	1	1
266	1	1
268	1	1
270	1	1
277	1	1
278	1	1
279	1	1
281	1	1
283	0	1
346	1	1

---

Cond Coverage for Module : spid_readsram

	Total	Covered	Percent
Conditions	20	20	100.00
Logical	20	20	100.00
Non-Logical	0	0
Event	0	0

 LINE       161
 EXPRESSION (mailbox_en_i && (mailbox_masked_addr == mailbox_addr_i))
             ------1-----    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T2,T5,T7

 LINE       161
 SUB-EXPRESSION (mailbox_masked_addr == mailbox_addr_i)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       189
 EXPRESSION ((addr_sel == AddrContinuous) ? ({(current_address_i[31:2] + 1'b1), 2'b0}) : current_address_i)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       189
 SUB-EXPRESSION (addr_sel == AddrContinuous)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       248
 EXPRESSION ((sram_read_req_i || sram_latched) && strb_set)
             ----------------1----------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       248
 SUB-EXPRESSION (sram_read_req_i || sram_latched)
                 -------1-------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       264
 EXPRESSION ((strb == 2'b11) && fifo_wready)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       264
 SUB-EXPRESSION (strb == 2'b11)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

---

FSM Coverage for Module : spid_readsram

Summary for FSM :: st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	3	3	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StActive	266	Covered	T1,T2,T5
StIdle	253	Covered	T1,T2,T3
StPush	251	Covered	T1,T2,T5

transitions	Line No.	Covered	Tests
StActive->StPush	279	Covered	T1,T2,T5
StIdle->StPush	251	Covered	T1,T2,T5
StPush->StActive	266	Covered	T1,T2,T5

---

Branch Coverage for Module : spid_readsram

	Line No.	Total	Covered	Percent
Branches		32	29	90.62
TERNARY	189	2	2	100.00
IF	166	3	3	100.00
IF	172	4	4	100.00
CASE	179	5	4	80.00
IF	195	3	3	100.00
IF	225	2	2	100.00
CASE	240	13	11	84.62

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_readsram.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_readsram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	189	((addr_sel == AddrContinuous)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	if ((!rst_ni))
-2-:	167	if (sram_req)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	172	if ((!rst_ni))
-2-:	173	if (data_inc)
-3-:	174	if (strb_set)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	179	case (strb)

Branches:

-1-	Status	Tests
2'b00	Covered	T1,T2,T3
2'b01	Covered	T1,T2,T5
2'b10	Covered	T1,T2,T5
2'b11	Covered	T1,T2,T5
default	Not Covered

	LineNo.	Expression
-1-:	195	if (sfdp_hit_i)
-2-:	197	if (mailbox_hit)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T7,T9
0	1	Covered	T2,T5,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	225	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	240	case (st_q)
-2-:	244	if (sram_read_req_i)
-3-:	248	if (((sram_read_req_i || sram_latched) && strb_set))
-4-:	258	if (sram_d_valid)
-5-:	262	if (fifo_wready)
-6-:	264	if (((strb == 2'b11) && fifo_wready))
-7-:	278	if ((!sram_fifo_full))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle	1	-	-	-	-	-	Covered	T1,T2,T5
StIdle	0	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	1	-	-	-	-	Covered	T1,T2,T5
StIdle	-	0	-	-	-	-	Covered	T1,T2,T3
StPush	-	-	1	-	-	-	Covered	T1,T2,T5
StPush	-	-	0	-	-	-	Covered	T5,T7,T8
StPush	-	-	-	1	-	-	Covered	T1,T2,T5
StPush	-	-	-	0	-	-	Covered	T1,T2,T5
StPush	-	-	-	-	1	-	Covered	T1,T2,T5
StPush	-	-	-	-	0	-	Covered	T1,T2,T5
StActive	-	-	-	-	-	1	Covered	T1,T2,T5
StActive	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	Not Covered

---

Assert Coverage for Module : spid_readsram

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrLatchedPulse_M	381988954	163926	0	0
FifoNotEmpty_A	381988954	11860710	0	0
NotOverflow_A	381988954	2990051	0	0
ReqStrbRelation_M	381988954	19936	0	0
SramDataReturnRequirement_M	381988954	2988765	0	0
SramReadOnly_A	381988954	2990051	0	0

AddrLatchedPulse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	163926	0	0
T1	13408	16	0	0
T2	39758	27	0	0
T3	1325	0	0	0
T5	992277	557	0	0
T6	360	0	0	0
T7	749009	699	0	0
T8	181176	32	0	0
T9	318604	169	0	0
T10	19687	16	0	0
T11	145674	810	0	0
T12	0	32	0	0
T13	0	38	0	0

FifoNotEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	11860710	0	0
T1	13408	3782	0	0
T2	39758	1925	0	0
T3	1325	0	0	0
T5	992277	38137	0	0
T6	360	0	0	0
T7	749009	10812	0	0
T8	181176	4344	0	0
T9	318604	2937	0	0
T10	19687	3552	0	0
T11	145674	72644	0	0
T12	0	10950	0	0
T13	0	256	0	0

NotOverflow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	2990051	0	0
T1	13408	957	0	0
T2	39758	485	0	0
T3	1325	0	0	0
T5	992277	9607	0	0
T6	360	0	0	0
T7	749009	2767	0	0
T8	181176	1090	0	0
T9	318604	753	0	0
T10	19687	897	0	0
T11	145674	18272	0	0
T12	0	2748	0	0
T13	0	66	0	0

ReqStrbRelation_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	19936	0	0
T1	13408	8	0	0
T2	39758	4	0	0
T3	1325	0	0	0
T5	992277	61	0	0
T6	360	0	0	0
T7	749009	47	0	0
T8	181176	2	0	0
T9	318604	13	0	0
T10	19687	8	0	0
T11	145674	91	0	0
T12	0	8	0	0
T13	0	2	0	0

SramDataReturnRequirement_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	2988765	0	0
T1	13408	957	0	0
T2	39758	485	0	0
T3	1325	0	0	0
T5	992277	9603	0	0
T6	360	0	0	0
T7	749009	2765	0	0
T8	181176	1088	0	0
T9	318604	752	0	0
T10	19687	897	0	0
T11	145674	18264	0	0
T12	0	2748	0	0
T13	0	66	0	0

SramReadOnly_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	2990051	0	0
T1	13408	957	0	0
T2	39758	485	0	0
T3	1325	0	0	0
T5	992277	9607	0	0
T6	360	0	0	0
T7	749009	2767	0	0
T8	181176	1090	0	0
T9	318604	753	0	0
T10	19687	897	0	0
T11	145674	18272	0	0
T12	0	2748	0	0
T13	0	66	0	0