SPI_DEVICE/1R1W Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: `4ee21f808f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.160m	135.604ms	48	50	96.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.360s	24.351us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.560s	39.406us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.100s	3.675ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.730s	930.405us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.820s	163.870us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.560s	39.406us	20	20	100.00
		spi_device_csr_aliasing	23.730s	930.405us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.720s	17.076us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.280s	58.848us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	csb_read	spi_device_csb_read	0.900s	65.315us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.760s	4.744us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.800s	29.337us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	18.320s	1.622ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	18.320s	1.622ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	32.420s	10.450ms	50	50	100.00
		spi_device_tpm_sts_read	1.280s	248.105us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.478m	17.651ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	43.680s	32.868ms	50	50	100.00
		spi_device_flash_all	6.259m	293.043ms	49	50	98.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	47.470s	16.209ms	50	50	100.00
		spi_device_flash_all	6.259m	293.043ms	49	50	98.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	47.470s	16.209ms	50	50	100.00
		spi_device_flash_all	6.259m	293.043ms	49	50	98.00
V2	cmd_info_slots	spi_device_flash_all	6.259m	293.043ms	49	50	98.00
V2	cmd_read_status	spi_device_intercept	14.630s	5.274ms	50	50	100.00
		spi_device_flash_all	6.259m	293.043ms	49	50	98.00
V2	cmd_read_jedec	spi_device_intercept	14.630s	5.274ms	50	50	100.00
		spi_device_flash_all	6.259m	293.043ms	49	50	98.00
V2	cmd_read_sfdp	spi_device_intercept	14.630s	5.274ms	50	50	100.00
		spi_device_flash_all	6.259m	293.043ms	49	50	98.00
V2	cmd_fast_read	spi_device_intercept	14.630s	5.274ms	50	50	100.00
		spi_device_flash_all	6.259m	293.043ms	49	50	98.00
V2	cmd_read_pipeline	spi_device_intercept	14.630s	5.274ms	50	50	100.00
		spi_device_flash_all	6.259m	293.043ms	49	50	98.00
V2	flash_cmd_upload	spi_device_upload	53.840s	47.376ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	47.580s	99.388ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	47.580s	99.388ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	47.580s	99.388ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.808m	24.061ms	50	50	100.00
		spi_device_read_buffer_direct	8.810s	9.416ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	47.580s	99.388ms	50	50	100.00
		spi_device_flash_all	6.259m	293.043ms	49	50	98.00
V2	quad_spi	spi_device_flash_all	6.259m	293.043ms	49	50	98.00
V2	dual_spi	spi_device_flash_all	6.259m	293.043ms	49	50	98.00
V2	4b_3b_feature	spi_device_cfg_cmd	11.560s	3.471ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	11.560s	3.471ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.160m	135.604ms	48	50	96.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.298m	79.160ms	49	50	98.00
V2	stress_all	spi_device_stress_all	14.620m	250.389ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	16.342us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.790s	28.564us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.250s	485.800us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.250s	485.800us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.360s	24.351us	5	5	100.00
		spi_device_csr_rw	2.560s	39.406us	20	20	100.00
		spi_device_csr_aliasing	23.730s	930.405us	5	5	100.00
		spi_device_same_csr_outstanding	4.490s	388.292us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.360s	24.351us	5	5	100.00
		spi_device_csr_rw	2.560s	39.406us	20	20	100.00
		spi_device_csr_aliasing	23.730s	930.405us	5	5	100.00
		spi_device_same_csr_outstanding	4.490s	388.292us	20	20	100.00
V2		TOTAL			958	980	97.76
V2S	tl_intg_err	spi_device_sec_cm	1.170s	171.894us	5	5	100.00
		spi_device_tl_intg_err	22.840s	1.032ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.840s	1.032ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1096	1120	97.86

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	22	22	19	86.36
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.92	98.30	94.08	98.61	89.36	97.00	95.84	98.22

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.31487519106199935736940442904870522433506596887395482709882413792704303908544
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   3428886 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[49])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   3428886 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   3428886 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[945])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.65164359138540337196901018668909150237352813610832389282077024606341223159308
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   6427423 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[101])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   6427423 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   6427423 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[997])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [flash_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 2 failures:

Test spi_device_flash_and_tpm has 2 failures.

8.spi_device_flash_and_tpm.42107650536010803240673118108657860636445936445249416857239698737621011109575
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 1946678591 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 2031311904 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 4/14
  UVM_INFO @ 2364549776 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 5/14
  UVM_INFO @ 2948609351 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 6/14
  UVM_INFO @ 3204375001 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 7/14

28.spi_device_flash_and_tpm.35469870833624880351828395250044360780612815592989972152294271039027775965474
Line 269, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 4723805424 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 4752849772 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 13/14
  UVM_INFO @ 5238571736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_scoreboard.sv:1101) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp * has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

12.spi_device_flash_and_tpm_min_idle.14028475345284253042691798111746940703980195226939204562981716322890440760745
Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 1836132938 ps: (spi_device_scoreboard.sv:1101) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 1915030266 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 6/8
  UVM_INFO @ 1915178653 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 5/7
  UVM_INFO @ 2270353954 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 7/8
  UVM_INFO @ 2324415563 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 6/7

UVM_ERROR (spi_device_scoreboard.sv:1070) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_flash_all has 1 failures.

33.spi_device_flash_all.60862598532206858632551537050090500510529937604439771672431778345468670975963
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 305824330 ps: (spi_device_scoreboard.sv:1070) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xdb1ab2) != exp '{'{other_status:'h23982e, wel:'h1, busy:'h0}, '{other_status:'h2a3514, wel:'h1, busy:'h0}}
  UVM_INFO @ 484944754 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 3/6
  UVM_INFO @ 660157036 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 4/6
  UVM_INFO @ 840418524 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 5/6
  UVM_INFO @ 1018924330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]