SPI_DEVICE/1R1W Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: `d51405297e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.681m	150.742ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.360s	147.623us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.920s	528.326us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	42.140s	12.353ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.870s	1.858ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.360s	56.271us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.920s	528.326us	20	20	100.00
		spi_device_csr_aliasing	24.870s	1.858ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	16.288us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.110s	185.556us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	80.243us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.740s	892.775ns	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	34.201us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	15.920s	323.385us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	15.920s	323.385us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.770s	12.586ms	50	50	100.00
		spi_device_tpm_sts_read	1.040s	136.639us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	48.390s	38.233ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	41.940s	28.480ms	50	50	100.00
		spi_device_flash_all	6.492m	232.882ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	36.360s	26.344ms	50	50	100.00
		spi_device_flash_all	6.492m	232.882ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	36.360s	26.344ms	50	50	100.00
		spi_device_flash_all	6.492m	232.882ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.492m	232.882ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	22.420s	4.296ms	50	50	100.00
		spi_device_flash_all	6.492m	232.882ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	22.420s	4.296ms	50	50	100.00
		spi_device_flash_all	6.492m	232.882ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	22.420s	4.296ms	50	50	100.00
		spi_device_flash_all	6.492m	232.882ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	22.420s	4.296ms	50	50	100.00
		spi_device_flash_all	6.492m	232.882ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	22.420s	4.296ms	50	50	100.00
		spi_device_flash_all	6.492m	232.882ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	34.500s	103.112ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.402m	42.871ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.402m	42.871ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.402m	42.871ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.006m	8.016ms	50	50	100.00
		spi_device_read_buffer_direct	21.440s	7.805ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.402m	42.871ms	50	50	100.00
		spi_device_flash_all	6.492m	232.882ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.492m	232.882ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.492m	232.882ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	13.710s	7.098ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	13.710s	7.098ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.681m	150.742ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.778m	77.548ms	50	50	100.00
V2	stress_all	spi_device_stress_all	22.682m	131.460ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.820s	32.865us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.840s	47.244us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.700s	246.074us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.700s	246.074us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.360s	147.623us	5	5	100.00
		spi_device_csr_rw	2.920s	528.326us	20	20	100.00
		spi_device_csr_aliasing	24.870s	1.858ms	5	5	100.00
		spi_device_same_csr_outstanding	4.090s	157.517us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.360s	147.623us	5	5	100.00
		spi_device_csr_rw	2.920s	528.326us	20	20	100.00
		spi_device_csr_aliasing	24.870s	1.858ms	5	5	100.00
		spi_device_same_csr_outstanding	4.090s	157.517us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.150s	1.212ms	5	5	100.00
		spi_device_tl_intg_err	23.900s	3.865ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.900s	3.865ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.562m	57.526ms	48	50	96.00
		TOTAL			1129	1151	98.09

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.93265383867428562045491657196632053936086519140811145976754755151478077284181
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   3885131 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[53])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   3885131 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   3885131 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[949])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.20666232952891082173615741190682246532045460019208630845598313670367346233472
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2944278 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[72])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2944278 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2944278 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[968])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be *

has 2 failures:

Test spi_device_flash_mode_ignore_cmds has 2 failures.

5.spi_device_flash_mode_ignore_cmds.34954392482008512457299029246556622684688156988898889107969603255228827858397
Line 264, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 2880975283 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  tl_ul_fuzzy_flash_status_q[i] = 0xa39c30
  tl_ul_fuzzy_flash_status_q[i] = 0xafab70
  UVM_INFO @ 5903916930 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 3/4
  UVM_INFO @ 5931728994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

17.spi_device_flash_mode_ignore_cmds.103347206591349279025672642832022741036168403926460215017089952355531658113463
Line 286, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 57021005662 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 64073914869 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 7/14
  UVM_INFO @ 64073914869 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 8/14
  tl_ul_fuzzy_flash_status_q[i] = 0xf17f74
  tl_ul_fuzzy_flash_status_q[i] = 0x8965f0