SPI_DEVICE/1R1W Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.492m	69.793ms	49	50	98.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.300s	23.542us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.900s	661.591us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	41.100s	2.796ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.150s	3.628ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.360s	187.603us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.900s	661.591us	20	20	100.00
		spi_device_csr_aliasing	24.150s	3.628ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	37.195us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.190s	51.569us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	csb_read	spi_device_csb_read	0.880s	54.433us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.750s	1.862us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	17.071us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	5.340s	1.042ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.340s	1.042ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.910s	8.142ms	50	50	100.00
		spi_device_tpm_sts_read	1.190s	169.038us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	53.010s	9.513ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	31.080s	39.701ms	50	50	100.00
		spi_device_flash_all	8.234m	70.379ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	27.020s	28.688ms	50	50	100.00
		spi_device_flash_all	8.234m	70.379ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	27.020s	28.688ms	50	50	100.00
		spi_device_flash_all	8.234m	70.379ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.234m	70.379ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	52.510s	38.189ms	50	50	100.00
		spi_device_flash_all	8.234m	70.379ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	52.510s	38.189ms	50	50	100.00
		spi_device_flash_all	8.234m	70.379ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	52.510s	38.189ms	50	50	100.00
		spi_device_flash_all	8.234m	70.379ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	52.510s	38.189ms	50	50	100.00
		spi_device_flash_all	8.234m	70.379ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	52.510s	38.189ms	50	50	100.00
		spi_device_flash_all	8.234m	70.379ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	31.470s	13.582ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.575m	101.588ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.575m	101.588ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.575m	101.588ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.404m	11.756ms	50	50	100.00
		spi_device_read_buffer_direct	20.490s	5.030ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.575m	101.588ms	50	50	100.00
		spi_device_flash_all	8.234m	70.379ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.234m	70.379ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.234m	70.379ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	30.430s	3.749ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	30.430s	3.749ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.492m	69.793ms	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.547m	150.235ms	50	50	100.00
V2	stress_all	spi_device_stress_all	21.211m	126.272ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.880s	16.358us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.850s	17.210us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.940s	773.084us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.940s	773.084us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.300s	23.542us	5	5	100.00
		spi_device_csr_rw	2.900s	661.591us	20	20	100.00
		spi_device_csr_aliasing	24.150s	3.628ms	5	5	100.00
		spi_device_same_csr_outstanding	4.290s	792.095us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.300s	23.542us	5	5	100.00
		spi_device_csr_rw	2.900s	661.591us	20	20	100.00
		spi_device_csr_aliasing	24.150s	3.628ms	5	5	100.00
		spi_device_same_csr_outstanding	4.290s	792.095us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.300s	251.660us	5	5	100.00
		spi_device_tl_intg_err	23.090s	3.225ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.090s	3.225ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.418m	142.999ms	50	50	100.00
		TOTAL			1130	1151	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	7	87.50
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	98.38	93.99	98.62	89.36	97.19	95.45	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.51449008301165967878419287202493586797394106949899592323655117317715206203677
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4254116 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[101])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4254116 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4254116 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[997])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.94884016555006196825601060006415249958325962484300178304602066326926940829459
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1169048 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[96])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1169048 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1169048 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[992])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_scoreboard.sv:1032) scoreboard [scoreboard] Compare failed, downstream item: has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

28.spi_device_flash_and_tpm.51586623446234381204466479759008547447381204290834270658367955166101234173057
Line 287, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 20346386319 ps: (spi_device_scoreboard.sv:1032) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare failed, downstream item:
  -------------------------------------------------------------------------
  Name                               Type              Size  Value
  -------------------------------------------------------------------------
  host_item                          spi_item          -     @1078087