SPI_DEVICE/1R1W Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: `c42c47ec2d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.348m	66.569ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.450s	46.962us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.650s	458.115us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.600s	3.757ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.740s	1.252ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.130s	1.757ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.650s	458.115us	20	20	100.00
		spi_device_csr_aliasing	21.740s	1.252ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.660s	21.105us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.200s	61.237us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	42.929us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.740s	4.481us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.780s	16.065us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.520s	563.163us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.520s	563.163us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.330s	30.494ms	50	50	100.00
		spi_device_tpm_sts_read	1.050s	224.961us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	49.620s	17.264ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	32.580s	14.668ms	50	50	100.00
		spi_device_flash_all	7.862m	277.078ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	30.090s	41.420ms	50	50	100.00
		spi_device_flash_all	7.862m	277.078ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	30.090s	41.420ms	50	50	100.00
		spi_device_flash_all	7.862m	277.078ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.862m	277.078ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	34.560s	39.445ms	50	50	100.00
		spi_device_flash_all	7.862m	277.078ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	34.560s	39.445ms	50	50	100.00
		spi_device_flash_all	7.862m	277.078ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	34.560s	39.445ms	50	50	100.00
		spi_device_flash_all	7.862m	277.078ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	34.560s	39.445ms	50	50	100.00
		spi_device_flash_all	7.862m	277.078ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	34.560s	39.445ms	50	50	100.00
		spi_device_flash_all	7.862m	277.078ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	40.600s	56.748ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.278m	12.545ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.278m	12.545ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.278m	12.545ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.155m	6.327ms	50	50	100.00
		spi_device_read_buffer_direct	25.220s	1.829ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.278m	12.545ms	50	50	100.00
		spi_device_flash_all	7.862m	277.078ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.862m	277.078ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.862m	277.078ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	17.800s	1.974ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	17.800s	1.974ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.348m	66.569ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	15.114m	423.186ms	50	50	100.00
V2	stress_all	spi_device_stress_all	13.704m	162.762ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.870s	43.914us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.830s	14.722us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.250s	909.885us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.250s	909.885us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.450s	46.962us	5	5	100.00
		spi_device_csr_rw	2.650s	458.115us	20	20	100.00
		spi_device_csr_aliasing	21.740s	1.252ms	5	5	100.00
		spi_device_same_csr_outstanding	4.300s	424.985us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.450s	46.962us	5	5	100.00
		spi_device_csr_rw	2.650s	458.115us	20	20	100.00
		spi_device_csr_aliasing	21.740s	1.252ms	5	5	100.00
		spi_device_same_csr_outstanding	4.300s	424.985us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.190s	423.912us	5	5	100.00
		spi_device_tl_intg_err	22.220s	3.910ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.220s	3.910ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	9.984m	90.192ms	49	50	98.00
		TOTAL			1130	1151	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.39	93.99	98.62	89.36	97.21	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.54835125057650375471815994276540146628802301271985962494554058347108679528280
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    959531 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[91])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    959531 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    959531 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[987])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.109405512859975410981926366873809426717440295842071975532619364567930409568990
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2185259 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[32])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2185259 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2185259 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[928])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_scoreboard.sv:2798) [scoreboard] Check failed upload_cmd_q.size == * (* [*] vs * [*]) has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 0.spi_device_flash_mode_ignore_cmds.9552187190918226618436306744403428974691740667663519079865968810384989572523
    Line 268, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_ERROR @ 3290387976 ps: (spi_device_scoreboard.sv:2798) [uvm_test_top.env.scoreboard] Check failed upload_cmd_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 3290387976 ps: (spi_device_scoreboard.sv:2799) [uvm_test_top.env.scoreboard] Check failed upload_addr_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 3290387976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```