SPI_DEVICE/1R1W Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: `edf2fd5092`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.759m	929.983ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.420s	120.409us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.800s	283.929us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	37.510s	1.906ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.280s	2.432ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.200s	136.068us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.800s	283.929us	20	20	100.00
		spi_device_csr_aliasing	16.280s	2.432ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.740s	16.359us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.870s	264.640us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	21.098us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.770s	6.482us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.770s	28.970us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	9.270s	360.771us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.270s	360.771us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.270s	15.400ms	50	50	100.00
		spi_device_tpm_sts_read	1.040s	1.446ms	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	46.580s	8.296ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	36.440s	49.266ms	50	50	100.00
		spi_device_flash_all	10.165m	577.832ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	29.560s	35.259ms	50	50	100.00
		spi_device_flash_all	10.165m	577.832ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	29.560s	35.259ms	50	50	100.00
		spi_device_flash_all	10.165m	577.832ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	10.165m	577.832ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	39.050s	13.020ms	50	50	100.00
		spi_device_flash_all	10.165m	577.832ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	39.050s	13.020ms	50	50	100.00
		spi_device_flash_all	10.165m	577.832ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	39.050s	13.020ms	50	50	100.00
		spi_device_flash_all	10.165m	577.832ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	39.050s	13.020ms	50	50	100.00
		spi_device_flash_all	10.165m	577.832ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	39.050s	13.020ms	50	50	100.00
		spi_device_flash_all	10.165m	577.832ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	40.610s	116.767ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	3.174m	162.861ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.174m	162.861ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.174m	162.861ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.145m	16.622ms	50	50	100.00
		spi_device_read_buffer_direct	21.870s	7.151ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.174m	162.861ms	50	50	100.00
		spi_device_flash_all	10.165m	577.832ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	10.165m	577.832ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	10.165m	577.832ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	22.270s	7.563ms	49	50	98.00
V2	write_enable_disable	spi_device_cfg_cmd	22.270s	7.563ms	49	50	98.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.759m	929.983ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.362m	58.591ms	50	50	100.00
V2	stress_all	spi_device_stress_all	20.912m	479.692ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	10.994us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	15.322us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.220s	826.542us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.220s	826.542us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.420s	120.409us	5	5	100.00
		spi_device_csr_rw	2.800s	283.929us	20	20	100.00
		spi_device_csr_aliasing	16.280s	2.432ms	5	5	100.00
		spi_device_same_csr_outstanding	4.340s	426.820us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.420s	120.409us	5	5	100.00
		spi_device_csr_rw	2.800s	283.929us	20	20	100.00
		spi_device_csr_aliasing	16.280s	2.432ms	5	5	100.00
		spi_device_same_csr_outstanding	4.340s	426.820us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	1.160s	133.523us	5	5	100.00
		spi_device_tl_intg_err	21.920s	3.279ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.920s	3.279ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	33.125m	1.500s	49	50	98.00
		TOTAL			1129	1151	98.09

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	20	90.91
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	98.38	93.99	98.62	89.36	97.19	95.45	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.83054094264585227852192540373372646816007686269006912022070094628767056633106
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1094050 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[25])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1094050 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1094050 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[921])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.75875883114339291245841639276166434510137208029966344607817807981127165334516
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    936484 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[100])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    936484 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    936484 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[996])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 37.spi_device_flash_mode_ignore_cmds.18120206161649603549408937607227363607018490340587796966193907517446953022737
    Line 307, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:2235) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_cfg_cmd has 1 failures.

47.spi_device_cfg_cmd.14434272268339123650542619231584062832590861264192431403994640361181286934841
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 210677504 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x82de96) != exp '{'{other_status:'h19e58b, wel:'h1, busy:'h0}, '{other_status:'h19e58b, wel:'h1, busy:'h0}, '{other_status:'h20b7a5, wel:'h0, busy:'h0}, '{other_status:'h19e58b, wel:'h0, busy:'h0}, '{other_status:'h20b7a5, wel:'h0, busy:'h0}}
  UVM_ERROR @ 211139042 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x82de96) != exp '{'{other_status:'h19e58b, wel:'h1, busy:'h0}, '{other_status:'h19e58b, wel:'h1, busy:'h0}, '{other_status:'h20b7a5, wel:'h0, busy:'h0}, '{other_status:'h19e58b, wel:'h0, busy:'h0}, '{other_status:'h20b7a5, wel:'h0, busy:'h0}}
  UVM_ERROR @ 211402778 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x82de96) != exp '{'{other_status:'h19e58b, wel:'h1, busy:'h0}, '{other_status:'h19e58b, wel:'h1, busy:'h0}, '{other_status:'h20b7a5, wel:'h0, busy:'h0}, '{other_status:'h19e58b, wel:'h0, busy:'h0}, '{other_status:'h20b7a5, wel:'h0, busy:'h0}}
  UVM_ERROR @ 211446734 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x82de96) != exp '{'{other_status:'h19e58b, wel:'h1, busy:'h0}, '{other_status:'h19e58b, wel:'h1, busy:'h0}, '{other_status:'h20b7a5, wel:'h0, busy:'h0}, '{other_status:'h19e58b, wel:'h0, busy:'h0}, '{other_status:'h20b7a5, wel:'h0, busy:'h0}}
  UVM_ERROR @ 211952228 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x82de96) != exp '{'{other_status:'h19e58b, wel:'h1, busy:'h0}, '{other_status:'h19e58b, wel:'h1, busy:'h0}, '{other_status:'h20b7a5, wel:'h0, busy:'h0}, '{other_status:'h20b7a5, wel:'h0, busy:'h0}, '{other_status:'h38536d, wel:'h0, busy:'h0}}