SPI_DEVICE/1R1W Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: `9edf84e236`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.464m	116.552ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.200s	250.623us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.600s	109.810us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.190s	7.193ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.860s	6.090ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.690s	487.246us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.600s	109.810us	20	20	100.00
		spi_device_csr_aliasing	21.860s	6.090ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.660s	87.929us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.230s	283.315us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.860s	13.991us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.790s	1.693us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	17.526us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	12.260s	835.745us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	12.260s	835.745us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	23.600s	39.013ms	50	50	100.00
		spi_device_tpm_sts_read	1.040s	371.824us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	49.770s	87.529ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	34.710s	32.695ms	50	50	100.00
		spi_device_flash_all	5.269m	41.324ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	31.720s	55.811ms	50	50	100.00
		spi_device_flash_all	5.269m	41.324ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	31.720s	55.811ms	50	50	100.00
		spi_device_flash_all	5.269m	41.324ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.269m	41.324ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	28.120s	9.079ms	50	50	100.00
		spi_device_flash_all	5.269m	41.324ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	28.120s	9.079ms	50	50	100.00
		spi_device_flash_all	5.269m	41.324ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	28.120s	9.079ms	50	50	100.00
		spi_device_flash_all	5.269m	41.324ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	28.120s	9.079ms	50	50	100.00
		spi_device_flash_all	5.269m	41.324ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	28.120s	9.079ms	50	50	100.00
		spi_device_flash_all	5.269m	41.324ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	35.230s	43.451ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.153m	132.821ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.153m	132.821ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.153m	132.821ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	53.930s	3.889ms	50	50	100.00
		spi_device_read_buffer_direct	21.800s	3.189ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.153m	132.821ms	50	50	100.00
		spi_device_flash_all	5.269m	41.324ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.269m	41.324ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.269m	41.324ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	34.700s	7.680ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	34.700s	7.680ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.464m	116.552ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.975m	57.217ms	50	50	100.00
V2	stress_all	spi_device_stress_all	13.334m	148.934ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.780s	18.861us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	17.999us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.680s	143.043us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.680s	143.043us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.200s	250.623us	5	5	100.00
		spi_device_csr_rw	2.600s	109.810us	20	20	100.00
		spi_device_csr_aliasing	21.860s	6.090ms	5	5	100.00
		spi_device_same_csr_outstanding	4.260s	214.277us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.200s	250.623us	5	5	100.00
		spi_device_csr_rw	2.600s	109.810us	20	20	100.00
		spi_device_csr_aliasing	21.860s	6.090ms	5	5	100.00
		spi_device_same_csr_outstanding	4.260s	214.277us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.150s	358.968us	5	5	100.00
		spi_device_tl_intg_err	23.980s	1.387ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.980s	1.387ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.665m	76.354ms	48	50	96.00
		TOTAL			1129	1151	98.09

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.98	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.50119104020429178447201861123627361987584738320921346950193692854414298511589
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    862365 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[33])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    862365 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    862365 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[929])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.7715040824383083335160697683927689235448788918050566771245484414406082031488
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1002201 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[32])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1002201 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1002201 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[928])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test spi_device_flash_mode_ignore_cmds has 2 failures.
  - 12.spi_device_flash_mode_ignore_cmds.44270737314011047157510524459179822470142947891232070475560256909797789469486
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job ID: smart:900b6298-4fbd-468e-9907-b639e95ad7c3
```
  - 22.spi_device_flash_mode_ignore_cmds.37615743755131756082545402203511495195289913165121747731939373690179100217227
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job ID: smart:efc6c986-d772-467d-bdde-420fc4c7b6f8
```