SPI_DEVICE/1R1W Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: `c04cc5d074`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.780m	57.238ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.440s	301.178us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.770s	450.867us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	25.280s	7.243ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.460s	620.526us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.960s	276.667us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.770s	450.867us	20	20	100.00
		spi_device_csr_aliasing	16.460s	620.526us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	11.197us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.880s	165.504us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	18.391us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.770s	1.377us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	34.929us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	9.000s	555.618us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.000s	555.618us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.050s	13.708ms	50	50	100.00
		spi_device_tpm_sts_read	1.050s	149.675us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	53.560s	21.651ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	31.280s	22.033ms	50	50	100.00
		spi_device_flash_all	8.315m	222.091ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	30.000s	19.393ms	50	50	100.00
		spi_device_flash_all	8.315m	222.091ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	30.000s	19.393ms	50	50	100.00
		spi_device_flash_all	8.315m	222.091ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.315m	222.091ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	24.870s	4.701ms	50	50	100.00
		spi_device_flash_all	8.315m	222.091ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	24.870s	4.701ms	50	50	100.00
		spi_device_flash_all	8.315m	222.091ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	24.870s	4.701ms	50	50	100.00
		spi_device_flash_all	8.315m	222.091ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	24.870s	4.701ms	50	50	100.00
		spi_device_flash_all	8.315m	222.091ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	24.870s	4.701ms	50	50	100.00
		spi_device_flash_all	8.315m	222.091ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	48.780s	30.239ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	3.089m	18.958ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.089m	18.958ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.089m	18.958ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.667m	18.521ms	49	50	98.00
		spi_device_read_buffer_direct	23.540s	7.890ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.089m	18.958ms	50	50	100.00
		spi_device_flash_all	8.315m	222.091ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.315m	222.091ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.315m	222.091ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	40.190s	29.389ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	40.190s	29.389ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.780m	57.238ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	16.266m	416.969ms	50	50	100.00
V2	stress_all	spi_device_stress_all	10.036m	121.631ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.900s	15.314us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	18.111us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.540s	991.791us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.540s	991.791us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.440s	301.178us	5	5	100.00
		spi_device_csr_rw	2.770s	450.867us	20	20	100.00
		spi_device_csr_aliasing	16.460s	620.526us	5	5	100.00
		spi_device_same_csr_outstanding	4.440s	1.323ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.440s	301.178us	5	5	100.00
		spi_device_csr_rw	2.770s	450.867us	20	20	100.00
		spi_device_csr_aliasing	16.460s	620.526us	5	5	100.00
		spi_device_same_csr_outstanding	4.440s	1.323ms	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	1.170s	78.521us	5	5	100.00
		spi_device_tl_intg_err	24.160s	10.237ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.160s	10.237ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	29.942m	1.500s	49	50	98.00
		TOTAL			1129	1151	98.09

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	20	90.91
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.39	93.99	98.62	89.36	97.23	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.97040685818022824692385339607359411440678082185928432165325531836143169788869
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1076418 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[79])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1076418 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1076418 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[975])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.8363371024935752294625131132540964034370700111938333347643982028074214335092
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1608433 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[81])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1608433 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1608433 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[977])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_scoreboard.sv:2338) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 27.spi_device_flash_mode.40786599382868955006742785485227993290116759520511204260750848403643498733113
    Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 10191760672 ps: (spi_device_scoreboard.sv:2338) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_INFO @ 18520536132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 41.spi_device_flash_mode_ignore_cmds.42695805667864290436541945710377190204629821925271805687156965857669051928010
    Line 267, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```