SPI_DEVICE/1R1W Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: `aad711e1bc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	13.820m	87.288ms	49	50	98.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.450s	40.200us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.860s	475.624us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	39.000s	5.524ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	19.540s	2.001ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.150s	264.393us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.860s	475.624us	20	20	100.00
		spi_device_csr_aliasing	19.540s	2.001ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	11.603us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.420s	278.650us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	csb_read	spi_device_csb_read	0.880s	22.412us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.770s	5.560us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.720s	21.407us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.240s	679.440us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.240s	679.440us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.900s	85.706ms	50	50	100.00
		spi_device_tpm_sts_read	1.120s	479.005us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	53.820s	9.815ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	27.760s	33.378ms	50	50	100.00
		spi_device_flash_all	7.638m	122.398ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	29.400s	17.845ms	50	50	100.00
		spi_device_flash_all	7.638m	122.398ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	29.400s	17.845ms	50	50	100.00
		spi_device_flash_all	7.638m	122.398ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.638m	122.398ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	29.000s	3.615ms	50	50	100.00
		spi_device_flash_all	7.638m	122.398ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	29.000s	3.615ms	50	50	100.00
		spi_device_flash_all	7.638m	122.398ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	29.000s	3.615ms	50	50	100.00
		spi_device_flash_all	7.638m	122.398ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	29.000s	3.615ms	50	50	100.00
		spi_device_flash_all	7.638m	122.398ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	29.000s	3.615ms	50	50	100.00
		spi_device_flash_all	7.638m	122.398ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	44.480s	26.752ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.546m	10.929ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.546m	10.929ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.546m	10.929ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	55.920s	3.574ms	50	50	100.00
		spi_device_read_buffer_direct	18.000s	18.924ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.546m	10.929ms	50	50	100.00
		spi_device_flash_all	7.638m	122.398ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.638m	122.398ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.638m	122.398ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	23.060s	23.661ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	23.060s	23.661ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.820m	87.288ms	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.613m	483.982ms	50	50	100.00
V2	stress_all	spi_device_stress_all	13.892m	336.387ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.810s	13.901us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	19.460us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.910s	3.744ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.910s	3.744ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.450s	40.200us	5	5	100.00
		spi_device_csr_rw	2.860s	475.624us	20	20	100.00
		spi_device_csr_aliasing	19.540s	2.001ms	5	5	100.00
		spi_device_same_csr_outstanding	4.450s	391.825us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.450s	40.200us	5	5	100.00
		spi_device_csr_rw	2.860s	475.624us	20	20	100.00
		spi_device_csr_aliasing	19.540s	2.001ms	5	5	100.00
		spi_device_same_csr_outstanding	4.450s	391.825us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.550s	285.513us	5	5	100.00
		spi_device_tl_intg_err	24.190s	4.680ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.190s	4.680ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.433m	84.678ms	50	50	100.00
		TOTAL			1130	1151	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	7	87.50
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.70152465052415889671668867822591346695006751755375406652834260942383494064822
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1159906 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[43])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1159906 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1159906 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[939])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.39850067188577527788575924751263013817628850170216899225105171475949202698216
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2307943 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[91])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2307943 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2307943 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[987])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_pass_base_vseq.sv:704) [flash_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be *

has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

20.spi_device_flash_and_tpm.74131826470924293171475259897653949022933104507127957949943920560637971492828
Line 284, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 2464587319 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 2520855569 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 8/10
  UVM_INFO @ 2520855569 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 9/10
  UVM_INFO @ 2808522569 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 9/10
  UVM_INFO @ 2827987319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]