Unified Coverage Report :: Module :: spid_jedec

Module : spid_jedec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_jedec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_jedec	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_jedec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
18.78	0.00	0.00	75.11		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spid_jedec

	Line No.	Total	Covered	Percent
TOTAL		47	0	0.00
CONT_ASSIGN	65	1	0	0.00
ALWAYS	73	4	0	0.00
CONT_ASSIGN	79	1	0	0.00
ALWAYS	83	4	0	0.00
ALWAYS	91	5	0	0.00
ALWAYS	101	8	0	0.00
ALWAYS	121	4	0	0.00
CONT_ASSIGN	125	1	0	0.00
ALWAYS	132	3	0	0.00
ALWAYS	138	16	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_jedec.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_jedec.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	0	1
73	0	2
74	0	2
			==> MISSING_ELSE
79	0	1
83	0	2
84	0	1
85	0	1
			==> MISSING_ELSE
91	0	1
92	0	1
93	0	1
95	0	1
96	0	1
101	0	1
103	0	1
105	0	1
106	0	1
107	0	1
108	0	1
109	0	1
113	0	1
121	0	2
122	0	2
			==> MISSING_ELSE
125	0	1
132	0	2
133	0	1
138	0	1
140	0	1
141	0	1
143	0	1
145	0	1
146	0	1
149	0	1
			==> MISSING_ELSE
160	0	1
161	0	1
			==> MISSING_ELSE
164	0	1
168	0	1
169	0	1
			==> MISSING_ELSE
172	0	1
179	0	1
181	0	1
182	0	1
			==> MISSING_ELSE

---

Cond Coverage for Module : spid_jedec

	Total	Covered	Percent
Conditions	29	0	0.00
Logical	29	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       84
 EXPRESSION ((st_q == StCC) && outclk_p2s_sent_i)
             -------1------    --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       84
 SUB-EXPRESSION (st_q == StCC)
                -------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       103
 EXPRESSION (st_q == StIdle)
            --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       105
 EXPRESSION (cc_needed ? jedec.cc : jedec.jedec_id)
             ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       106
 EXPRESSION (st_q == StCC)
            -------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       108
 EXPRESSION (st_q == StJedecId)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       113
 EXPRESSION ((byte_sel_q >= 2'b10) ? 8'b0 : ((byte_sel_q == 2'b1) ? jedec.device_id[15:8] : jedec.device_id[7:0]))
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       113
 SUB-EXPRESSION ((byte_sel_q == 2'b1) ? jedec.device_id[15:8] : jedec.device_id[7:0])
                 ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       113
 SUB-EXPRESSION (byte_sel_q == 2'b1)
                ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       125
 EXPRESSION ((byte_sel_q == 2'b10) ? 2'b10 : ((byte_sel_q + 1'b1)))
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       125
 SUB-EXPRESSION (byte_sel_q == 2'b10)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       145
 EXPRESSION (sel_dp_i == DpReadJEDEC)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       146
 EXPRESSION (cc_needed ? StCC : StJedecId)
             ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       160
 EXPRESSION (cc_count == jedec.num_cc)
            -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Module : spid_jedec

Summary for FSM :: st_q

	Total	Covered	Percent
States	4	0	0.00	(Not included in score)
Transitions	4	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StCC	146	Not Covered
StDevId	169	Not Covered
StIdle	103	Not Covered
StJedecId	146	Not Covered

transitions	Line No.	Covered	Tests
StCC->StJedecId	161	Not Covered
StIdle->StCC	146	Not Covered
StIdle->StJedecId	146	Not Covered
StJedecId->StDevId	169	Not Covered

---

Branch Coverage for Module : spid_jedec

	Line No.	Total	Covered	Percent
Branches		32	0	0.00
TERNARY	125	2	0	0.00
IF	73	3	0	0.00
IF	83	3	0	0.00
IF	91	2	0	0.00
IF	103	7	0	0.00
IF	121	3	0	0.00
IF	132	2	0	0.00
CASE	143	10	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_jedec.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_jedec.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	125	((byte_sel_q == 2'b10)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	73	if ((!rst_ni))
-2-:	74	if (cmd_sync_pulse_i)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	83	if ((!rst_ni))
-2-:	84	if (((st_q == StCC) && outclk_p2s_sent_i))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	91	if ((!rst_out_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	103	if ((st_q == StIdle))
-2-:	105	(cc_needed) ? 
-3-:	106	if ((st_q == StCC))
-4-:	108	if ((st_q == StJedecId))
-5-:	113	((byte_sel_q >= 2'b10)) ? 
-6-:	113	((byte_sel_q == 2'b1)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	1	-	-	-	-	Not Covered
1	0	-	-	-	-	Not Covered
0	-	1	-	-	-	Not Covered
0	-	0	1	-	-	Not Covered
0	-	0	0	1	-	Not Covered
0	-	0	0	0	1	Not Covered
0	-	0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	121	if ((!rst_ni))
-2-:	122	if (next_byte)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	132	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	143	case (st_q)
-2-:	145	if ((sel_dp_i == DpReadJEDEC))
-3-:	146	(cc_needed) ? 
-4-:	160	if ((cc_count == jedec.num_cc))
-5-:	168	if (outclk_p2s_sent_i)
-6-:	181	if (outclk_p2s_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle	1	1	-	-	-	Not Covered
StIdle	1	0	-	-	-	Not Covered
StIdle	0	-	-	-	-	Not Covered
StCC	-	-	1	-	-	Not Covered
StCC	-	-	0	-	-	Not Covered
StJedecId	-	-	-	1	-	Not Covered
StJedecId	-	-	-	0	-	Not Covered
StDevId	-	-	-	-	1	Not Covered
StDevId	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered