Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
18.78	0.00	0.00	75.11		0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	18.78	0.00	0.00	75.11		0.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
18.78	0.00	0.00	75.11		0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.20	70.94	74.27	75.00	0.00	76.99	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
spi_device_csr_assert	100.00						100.00
tlul_assert_device	33.33	0.00				0.00	100.00
u_clk_csb_buf	0.00	0.00
u_clk_csb_mux	0.00	0.00	0.00
u_clk_spi	0.00	0.00	0.00
u_clk_spi_in_buf	0.00	0.00
u_clk_spi_in_mux	0.00	0.00	0.00
u_clk_spi_out_buf	0.00	0.00
u_clk_spi_out_mux	0.00	0.00	0.00
u_cmdparse	0.00	0.00	0.00		0.00	0.00
u_csb_buf	0.00	0.00
u_csb_rst_out_scan_mux	0.00	0.00	0.00
u_csb_rst_scan_mux	0.00	0.00	0.00
u_flash_readbuf_flip_pulse_sync	0.00	0.00	0.00			0.00
u_flash_readbuf_watermark_pulse_sync	0.00	0.00	0.00			0.00
u_intr_cmdfifo_not_empty	0.00	0.00	0.00			0.00
u_intr_payload_not_empty	0.00	0.00	0.00			0.00
u_intr_payload_overflow	0.00	0.00	0.00			0.00
u_intr_readbuf_flip	0.00	0.00	0.00			0.00
u_intr_readbuf_watermark	0.00	0.00	0.00			0.00
u_intr_tpm_cmdaddr_notempty	0.00	0.00	0.00			0.00
u_intr_tpm_rdfifo_cmd_end	0.00	0.00	0.00			0.00
u_intr_tpm_rdfifo_drop	0.00	0.00	0.00			0.00
u_intr_upload_edge	0.00	0.00				0.00
u_jedec	0.00	0.00	0.00		0.00	0.00
u_p2s	0.00	0.00	0.00			0.00
u_passthrough	0.00	0.00	0.00		0.00	0.00
u_read_en_pipe_stg1	0.00	0.00				0.00
u_read_en_pipe_stg2	0.00	0.00				0.00
u_read_intercept_pipe_stg1	0.00	0.00				0.00
u_read_intercept_pipe_stg2	0.00	0.00				0.00
u_read_pipe_stg1	0.00	0.00				0.00
u_read_pipe_stg2	0.00	0.00				0.00
u_readcmd	0.00	0.00	0.00		0.00	0.00
u_reg	94.43	99.53	99.30	73.96		99.35	100.00
u_rst_spi_out_sync	0.00	0.00				0.00
u_s2p	0.00	0.00	0.00			0.00
u_spi_tpm	0.00	0.00	0.00		0.00	0.00
u_spid_addr_4b	0.00	0.00	0.00			0.00
u_spid_csb_sync	0.00	0.00	0.00			0.00
u_spid_dpram	0.00	0.00	0.00			0.00
u_spid_status	0.00	0.00	0.00			0.00
u_sys_csb_syncd	0.00	0.00				0.00
u_sys_sram_arbiter	0.00	0.00	0.00			0.00
u_sys_tpm_csb_sync	0.00	0.00				0.00
u_tlul2sram_egress	0.00	0.00	0.00			0.00
u_tlul2sram_ingress	0.00	0.00	0.00			0.00
u_tpm_csb_buf	0.00	0.00
u_tpm_csb_rst_scan_mux	0.00	0.00	0.00
u_tpm_csb_rst_sync	0.00	0.00	0.00			0.00
u_tpm_rst_out_scan_mux	0.00	0.00	0.00
u_tpm_rst_out_sync	0.00	0.00				0.00
u_upload	0.00	0.00	0.00		0.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
TOTAL		229	0	0.00
CONT_ASSIGN	173	1	0	0.00
CONT_ASSIGN	309	1	0	0.00
CONT_ASSIGN	372	1	0	0.00
CONT_ASSIGN	373	1	0	0.00
CONT_ASSIGN	376	1	0	0.00
CONT_ASSIGN	377	1	0	0.00
CONT_ASSIGN	379	1	0	0.00
CONT_ASSIGN	394	1	0	0.00
CONT_ASSIGN	527	1	0	0.00
CONT_ASSIGN	534	1	0	0.00
CONT_ASSIGN	536	1	0	0.00
ALWAYS	539	4	0	0.00
CONT_ASSIGN	547	1	0	0.00
CONT_ASSIGN	553	1	0	0.00
CONT_ASSIGN	554	1	0	0.00
CONT_ASSIGN	559	1	0	0.00
CONT_ASSIGN	560	1	0	0.00
CONT_ASSIGN	564	1	0	0.00
ALWAYS	569	0	0
ALWAYS	569	2	0	0.00
CONT_ASSIGN	574	1	0	0.00
CONT_ASSIGN	575	1	0	0.00
ALWAYS	583	0	0
ALWAYS	583	12	0	0.00
CONT_ASSIGN	647	1	0	0.00
CONT_ASSIGN	648	1	0	0.00
CONT_ASSIGN	649	1	0	0.00
CONT_ASSIGN	710	1	0	0.00
ALWAYS	828	3	0	0.00
ALWAYS	834	8	0	0.00
ALWAYS	872	9	0	0.00
ALWAYS	896	24	0	0.00
CONT_ASSIGN	964	1	0	0.00
CONT_ASSIGN	965	1	0	0.00
ALWAYS	1028	7	0	0.00
ALWAYS	1041	13	0	0.00
ALWAYS	1078	3	0	0.00
CONT_ASSIGN	1217	1	0	0.00
CONT_ASSIGN	1220	1	0	0.00
CONT_ASSIGN	1224	1	0	0.00
CONT_ASSIGN	1225	1	0	0.00
CONT_ASSIGN	1226	1	0	0.00
CONT_ASSIGN	1228	1	0	0.00
CONT_ASSIGN	1229	1	0	0.00
CONT_ASSIGN	1232	1	0	0.00
CONT_ASSIGN	1282	1	0	0.00
CONT_ASSIGN	1313	1	0	0.00
CONT_ASSIGN	1396	1	0	0.00
CONT_ASSIGN	1397	1	0	0.00
CONT_ASSIGN	1398	1	0	0.00
CONT_ASSIGN	1399	1	0	0.00
CONT_ASSIGN	1400	1	0	0.00
CONT_ASSIGN	1402	1	0	0.00
CONT_ASSIGN	1406	1	0	0.00
CONT_ASSIGN	1413	1	0	0.00
CONT_ASSIGN	1414	1	0	0.00
CONT_ASSIGN	1416	1	0	0.00
CONT_ASSIGN	1420	1	0	0.00
CONT_ASSIGN	1423	1	0	0.00
CONT_ASSIGN	1426	1	0	0.00
CONT_ASSIGN	1429	1	0	0.00
CONT_ASSIGN	1432	1	0	0.00
CONT_ASSIGN	1435	1	0	0.00
CONT_ASSIGN	1442	1	0	0.00
CONT_ASSIGN	1443	1	0	0.00
CONT_ASSIGN	1482	1	0	0.00
CONT_ASSIGN	1585	1	0	0.00
CONT_ASSIGN	1593	1	0	0.00
CONT_ASSIGN	1594	1	0	0.00
CONT_ASSIGN	1595	1	0	0.00
CONT_ASSIGN	1596	1	0	0.00
CONT_ASSIGN	1597	1	0	0.00
CONT_ASSIGN	1600	1	0	0.00
CONT_ASSIGN	1607	1	0	0.00
CONT_ASSIGN	1614	1	0	0.00
CONT_ASSIGN	1614	1	0	0.00
CONT_ASSIGN	1614	1	0	0.00
CONT_ASSIGN	1614	1	0	0.00
CONT_ASSIGN	1614	1	0	0.00
CONT_ASSIGN	1617	1	0	0.00
CONT_ASSIGN	1618	1	0	0.00
CONT_ASSIGN	1619	1	0	0.00
CONT_ASSIGN	1620	1	0	0.00
CONT_ASSIGN	1621	1	0	0.00
CONT_ASSIGN	1622	1	0	0.00
CONT_ASSIGN	1624	1	0	0.00
CONT_ASSIGN	1628	1	0	0.00
CONT_ASSIGN	1630	1	0	0.00
CONT_ASSIGN	1631	1	0	0.00
CONT_ASSIGN	1638	1	0	0.00
CONT_ASSIGN	1640	1	0	0.00
CONT_ASSIGN	1641	1	0	0.00
CONT_ASSIGN	1650	1	0	0.00
CONT_ASSIGN	1651	1	0	0.00
CONT_ASSIGN	1652	1	0	0.00
CONT_ASSIGN	1653	1	0	0.00
CONT_ASSIGN	1716	1	0	0.00
CONT_ASSIGN	1718	1	0	0.00
ALWAYS	1723	4	0	0.00
ALWAYS	1732	0	0
ALWAYS	1732	9	0	0.00
CONT_ASSIGN	1749	1	0	0.00
CONT_ASSIGN	1749	1	0	0.00
CONT_ASSIGN	1749	1	0	0.00
CONT_ASSIGN	1749	1	0	0.00
CONT_ASSIGN	1749	1	0	0.00
CONT_ASSIGN	1750	1	0	0.00
CONT_ASSIGN	1750	1	0	0.00
CONT_ASSIGN	1750	1	0	0.00
CONT_ASSIGN	1750	1	0	0.00
CONT_ASSIGN	1750	1	0	0.00
CONT_ASSIGN	1751	1	0	0.00
CONT_ASSIGN	1751	1	0	0.00
CONT_ASSIGN	1751	1	0	0.00
CONT_ASSIGN	1751	1	0	0.00
CONT_ASSIGN	1751	1	0	0.00
CONT_ASSIGN	1752	1	0	0.00
CONT_ASSIGN	1752	1	0	0.00
CONT_ASSIGN	1752	1	0	0.00
CONT_ASSIGN	1752	1	0	0.00
CONT_ASSIGN	1752	1	0	0.00
CONT_ASSIGN	1754	1	0	0.00
CONT_ASSIGN	1754	1	0	0.00
CONT_ASSIGN	1754	1	0	0.00
CONT_ASSIGN	1754	1	0	0.00
CONT_ASSIGN	1754	1	0	0.00
CONT_ASSIGN	1755	1	0	0.00
CONT_ASSIGN	1755	1	0	0.00
CONT_ASSIGN	1755	1	0	0.00
CONT_ASSIGN	1755	1	0	0.00
CONT_ASSIGN	1755	1	0	0.00
CONT_ASSIGN	1756	1	0	0.00
CONT_ASSIGN	1756	1	0	0.00
CONT_ASSIGN	1756	1	0	0.00
CONT_ASSIGN	1756	1	0	0.00
CONT_ASSIGN	1756	1	0	0.00
CONT_ASSIGN	1797	1	0	0.00
CONT_ASSIGN	1799	1	0	0.00
CONT_ASSIGN	1800	1	0	0.00
CONT_ASSIGN	1801	1	0	0.00
CONT_ASSIGN	1802	1	0	0.00
CONT_ASSIGN	1803	1	0	0.00
CONT_ASSIGN	1805	1	0	0.00
CONT_ASSIGN	1806	1	0	0.00
CONT_ASSIGN	1807	1	0	0.00
CONT_ASSIGN	1863	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
173	0	1
309	0	1
372	0	1
373	0	1
376	0	1
377	0	1
379	0	1
394	0	1
527	0	1
534	0	1
536	0	1
539	0	1
540	0	1
541	0	1
542	0	1
			==> MISSING_ELSE
547	0	1
553	0	1
554	0	1
559	0	1
560	0	1
564	0	1
569	0	1
570	0	1
574	0	1
575	0	1
583	0	1
584	0	1
603	0	1
604	0	1
608	0	1
609	0	1
611	0	1
612	0	1
614	0	1
615	0	1
617	0	1
618	0	1
647	0	1
648	0	1
649	0	1
710	0	1
828	0	2
829	0	1
834	0	1
836	0	1
837	0	1
844	0	1
848	0	1
849	0	1
853	0	1
854	0	1
872	0	1
874	0	1
879	0	1
885	0	1
886	0	1
887	0	1
888	0	1
889	0	1
890	0	1
			==> MISSING_ELSE
896	0	1
897	0	1
898	0	1
899	0	1
901	0	1
903	0	1
905	0	1
907	0	1
911	0	1
913	0	1
914	0	1
915	0	1
918	0	1
920	0	1
921	0	1
922	0	1
927	0	1
929	0	1
930	0	1
931	0	1
935	0	1
937	0	1
938	0	1
939	0	1
964	0	1
965	0	1
1028	0	1
1029	0	1
1030	0	1
1031	0	1
1033	0	1
1034	0	1
1035	0	1
1041	0	1
1042	0	1
1044	0	1
1046	0	1
1047	0	1
1051	0	1
1053	0	1
1054	0	1
1058	0	1
1059	0	1
1060	0	1
1062	0	1
1063	0	1
1078	0	2
1079	0	1
1217	0	1
1220	0	1
1224	0	1
1225	0	1
1226	0	1
1228	0	1
1229	0	1
1232	0	1
1282	0	1
1313	0	1
1396	0	1
1397	0	1
1398	0	1
1399	0	1
1400	0	1
1402	0	1
1406	0	1
1413	0	1
1414	0	1
1416	0	1
1420	0	1
1423	0	1
1426	0	1
1429	0	1
1432	0	1
1435	0	1
1442	0	1
1443	0	1
1482	0	1
1585	0	1
1593	0	1
1594	0	1
1595	0	1
1596	0	1
1597	0	1
1600	0	1
1607	0	1
1614	0	5
1617	0	1
1618	0	1
1619	0	1
1620	0	1
1621	0	1
1622	0	1
1624	0	1
1628	0	1
1630	0	1
1631	0	1
1638	0	1
1640	0	1
1641	0	1
1650	0	1
1651	0	1
1652	0	1
1653	0	1
1716	0	1
1718	0	1
1723	0	1
1724	0	1
1725	0	1
1726	0	1
			==> MISSING_ELSE
1732	0	1
1733	0	1
1735	0	1
1738	0	1
1739	0	1
1740	0	1
1741	0	1
1743	0	1
1744	0	1
1749	0	5
1750	0	5
1751	0	5
1752	0	5
1754	0	5
1755	0	5
1756	0	5
1797	0	1
1799	0	1
1800	0	1
1801	0	1
1802	0	1
1803	0	1
1805	0	1
1806	0	1
1807	0	1
1863	0	1

---

Cond Coverage for Module : spi_device

	Total	Covered	Percent
Conditions	51	0	0.00
Logical	51	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       173
 EXPRESSION (payload_depth != '0)
            ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       702
 EXPRESSION (rst_ni & ((~rst_csb_buf)))
             ---1--   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       736
 EXPRESSION (rst_ni & ((~rst_tpm_csb_buf)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       858
 EXPRESSION (cmd_only_dp_sel == DpUpload)
            --------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       885
 EXPRESSION (((!sck_csb)) && ((spi_mode == FlashMode) || (spi_mode == PassThrough)))
             ------1-----    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       885
 SUB-EXPRESSION ((spi_mode == FlashMode) || (spi_mode == PassThrough))
                 -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       885
 SUB-EXPRESSION (spi_mode == FlashMode)
                -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       885
 SUB-EXPRESSION (spi_mode == PassThrough)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1044
 EXPRESSION (cfg_tpm_en && ((!sck_tpm_csb_buf)))
             -----1----    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1217
 EXPRESSION (reg2hw.flash_status.busy.qe && reg2hw.flash_status.wel.qe && reg2hw.flash_status.status.qe)
             -------------1-------------    -------------2------------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       1228
 EXPRESSION (cmd_only_dp_sel == DpWrEn)
            -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1229
 EXPRESSION (cmd_only_dp_sel == DpWrDi)
            -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1442
 EXPRESSION (cmd_only_dp_sel == DpEn4B)
            -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1443
 EXPRESSION (cmd_only_dp_sel == DpEx4B)
            -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1607
 EXPRESSION (reg2hw.tpm_status.wrfifo_pending.qe & ((~reg2hw.tpm_status.wrfifo_pending.q)))
             -----------------1-----------------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1725
 EXPRESSION ((i != SysSramFwEgress) && (i != SysSramFwIngress))
             -----------1----------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1725
 SUB-EXPRESSION (i != SysSramFwEgress)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1725
 SUB-EXPRESSION (i != SysSramFwIngress)
                -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1797
 EXPRESSION (tpm_rst_in_n | rst_spi_in_n)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       1863
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	63	35	55.56
Total Bits	466	350	75.11
Total Bits 0->1	233	175	75.11
Total Bits 1->0	233	175	75.11

Ports	63	35	55.56
Port Bits	466	350	75.11
Port Bits 0->1	233	175	75.11
Port Bits 1->0	233	175	75.11

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T6	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T5,T8,T9	Yes	T5,T8,T9	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T2,T3,T6	Yes	T2,T3,T6	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	OUTPUT
cio_sck_i	No	No		No		INPUT
cio_csb_i	No	No		No		INPUT
cio_sd_o[3:0]	No	No		No		OUTPUT
cio_sd_en_o[3:0]	No	No		No		OUTPUT
cio_sd_i[3:0]	No	No		No		INPUT
cio_tpm_csb_i	No	No		No		INPUT
passthrough_o.s_en[3:0]	No	No		No		OUTPUT
passthrough_o.s[3:0]	No	No		No		OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	No	No		No		OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	No	No		No		OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T1,T10,T4	Yes	T1,T10,T4	OUTPUT
passthrough_i.s[3:0]	No	No		No		INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T3,T6,T11	Yes	T3,T6,T11	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T6,T11,T12	Yes	T6,T11,T12	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T6,T11,T12	Yes	T6,T11,T12	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T3,T6,T11	Yes	T3,T6,T11	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T3,T6,T11	Yes	T3,T6,T11	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T3,T6,T11	Yes	T3,T6,T11	OUTPUT
intr_tpm_rdfifo_cmd_end_o	Yes	Yes	T3,T6,T11	Yes	T3,T6,T11	OUTPUT
intr_tpm_rdfifo_drop_o	Yes	Yes	T3,T6,T11	Yes	T3,T6,T11	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.b_ram_lcfg.test	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.test	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.test	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.test	No	No		No		INPUT
sck_monitor_o	No	No		No		OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	No	No		No		INPUT
scan_rst_ni	No	No		No		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
Branches		32	0	0.00
IF	539	3	0	0.00
IF	828	2	0	0.00
CASE	844	4	0	0.00
IF	885	3	0	0.00
CASE	901	7	0	0.00
IF	1028	2	0	0.00
IF	1044	5	0	0.00
IF	1078	2	0	0.00
IF	1725	2	0	0.00
IF	1735	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	539	if ((!rst_ni))
-2-:	541	if (sys_csb_deasserted_pulse)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	828	if ((!rst_spi_out_n))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	844	case (cmd_dp_sel)
-2-:	858	if ((cmd_only_dp_sel == DpUpload))

Branches:

-1-	-2-	Status	Tests
DpReadCmd DpReadSFDP	-	Not Covered
DpUpload	-	Not Covered
default	1	Not Covered
default	0	Not Covered

	LineNo.	Expression
-1-:	885	if (((!sck_csb) && ((spi_mode == FlashMode) || (spi_mode == PassThrough))))
-2-:	888	if (cfg_tpm_en)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	901	case (spi_mode)
-2-:	903	case (cmd_dp_sel)

Branches:

-1-	-2-	Status	Tests
FlashMode PassThrough	DpNone	Not Covered
FlashMode PassThrough	DpReadCmd DpReadSFDP	Not Covered
FlashMode PassThrough	DpReadStatus	Not Covered
FlashMode PassThrough	DpReadJEDEC	Not Covered
FlashMode PassThrough	DpUpload	Not Covered
FlashMode PassThrough	default	Not Covered
default	-	Not Covered

	LineNo.	Expression
-1-:	1028	if (cmd_read_pipeline_sel)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	1044	if ((cfg_tpm_en && (!sck_tpm_csb_buf)))
-2-:	1051	case (spi_mode)
-3-:	1058	if (intercept_en_out)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	FlashMode	-	Not Covered
0	PassThrough	1	Not Covered
0	PassThrough	0	Not Covered
0	default	-	Not Covered

	LineNo.	Expression
-1-:	1078	if ((!rst_spi_out_n))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	1725	if (((i != SysSramFwEgress) && (i != SysSramFwIngress)))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	1735	if (sys_sram_hw_req)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered