Unified Coverage Report :: Module :: spid_status

Module : spid_status

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_status	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_spid_status

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
18.78	0.00	0.00	75.11		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_csb_rst_scan_mux	0.00	0.00	0.00
u_sck2csb_status	0.00	0.00				0.00
u_stage_to_commit	0.00	0.00				0.00
u_sw_status_update_sync	0.00	0.00	0.00			0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spid_status

	Line No.	Total	Covered	Percent
TOTAL		65	0	0.00
CONT_ASSIGN	95	1	0	0.00
CONT_ASSIGN	98	1	0	0.00
ALWAYS	166	6	0	0.00
ALWAYS	177	8	0	0.00
ALWAYS	190	4	0	0.00
ALWAYS	202	7	0	0.00
CONT_ASSIGN	224	1	0	0.00
CONT_ASSIGN	225	1	0	0.00
CONT_ASSIGN	226	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
ALWAYS	264	3	0	0.00
ALWAYS	309	4	0	0.00
ALWAYS	322	5	0	0.00
ALWAYS	336	3	0	0.00
ALWAYS	344	6	0	0.00
CONT_ASSIGN	358	1	0	0.00
ALWAYS	365	3	0	0.00
ALWAYS	370	9	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
95	0	1
98	0	1
166	0	1
167	0	1
168	0	1
169	0	1
170	0	1
171	0	1
			==> MISSING_ELSE
177	0	1
178	0	1
179	0	1
180	0	1
181	0	1
182	0	1
183	0	1
184	0	1
			==> MISSING_ELSE
190	0	1
191	0	1
192	0	1
193	0	1
			==> MISSING_ELSE
202	0	1
203	0	1
204	0	1
205	0	1
206	0	1
			==> MISSING_ELSE
208	0	1
209	0	1
			==> MISSING_ELSE
224	0	1
225	0	1
226	0	1
241	0	1
264	0	1
265	0	1
267	0	1
309	0	1
310	0	1
311	0	1
312	0	1
			==> MISSING_ELSE
322	0	1
323	0	1
324	0	1
326	0	1
327	0	1
336	0	1
337	0	1
339	0	1
344	0	1
346	0	1
348	0	1
350	0	1
351	0	1
352	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
358	0	1
365	0	2
366	0	1
370	0	1
372	0	1
374	0	1
376	0	1
378	0	1
379	0	1
381	0	1
382	0	1
			==> MISSING_ELSE
387	0	1

---

Cond Coverage for Module : spid_status

	Total	Covered	Percent
Conditions	18	0	0.00
Logical	18	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       170
 EXPRESSION (sck_sw_we && (sck_sw_status[BitBusy] == 1'b0))
             ----1----    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       170
 SUB-EXPRESSION (sck_sw_status[BitBusy] == 1'b0)
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       183
 EXPRESSION (sck_sw_we && (sck_sw_status[BitWe] == 1'b0))
             ----1----    ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       183
 SUB-EXPRESSION (sck_sw_status[BitWe] == 1'b0)
                ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       351
 EXPRESSION (cmd_info_idx_i == 5'(StatusCmdIdx[i]))
            -------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       358
 EXPRESSION ((st_q == StIdle) ? sck_status_committed[(8 * byte_sel_d)+:8] : sck_status_committed[(8 * byte_sel_q)+:8])
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       358
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       378
 EXPRESSION (sel_dp_i == DpReadStatus)
            -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Module : spid_status

	Line No.	Total	Covered	Percent
Branches		36	0	0.00
TERNARY	358	2	0	0.00
IF	166	4	0	0.00
IF	177	5	0	0.00
IF	190	3	0	0.00
IF	203	3	0	0.00
IF	208	2	0	0.00
IF	264	2	0	0.00
IF	309	3	0	0.00
IF	322	2	0	0.00
IF	336	2	0	0.00
IF	346	2	0	0.00
IF	365	2	0	0.00
CASE	376	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	358	((st_q == StIdle)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	166	if ((!sys_rst_ni))
-2-:	168	if (inclk_busy_set_i)
-3-:	170	if ((sck_sw_we && (sck_sw_status[BitBusy] == 1'b0)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	177	if ((!sys_rst_ni))
-2-:	179	if (inclk_we_set_i)
-3-:	181	if (inclk_we_clr_i)
-4-:	183	if ((sck_sw_we && (sck_sw_status[BitWe] == 1'b0)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Not Covered
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	190	if ((!sys_rst_ni))
-2-:	192	if (sck_sw_we)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	203	if (inclk_we_set_i)
-2-:	205	if (inclk_we_clr_i)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	208	if (inclk_busy_set_i)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	264	if ((!sys_rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	309	if ((!sys_rst_ni))
-2-:	311	if (sys_csb_deasserted_pulse_i)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	322	if ((!rst_out_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	336	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	346	if (byte_sel_update)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	365	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	376	case (st_q)
-2-:	378	if ((sel_dp_i == DpReadStatus))

Branches:

-1-	-2-	Status	Tests
StIdle	1	Not Covered
StIdle	0	Not Covered
StActive	-	Not Covered
default	-	Not Covered