Unified Coverage Report :: Module :: spi_p2s

Module : spi_p2s

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_p2s	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_p2s

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
18.78	0.00	0.00	75.11		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_p2s

	Line No.	Total	Covered	Percent
TOTAL		34	0	0.00
ALWAYS	58	5	0	0.00
CONT_ASSIGN	79	1	0	0.00
ALWAYS	98	5	0	0.00
ALWAYS	110	4	0	0.00
CONT_ASSIGN	130	1	0	0.00
ALWAYS	134	5	0	0.00
CONT_ASSIGN	166	1	0	0.00
ALWAYS	170	6	0	0.00
CONT_ASSIGN	179	1	0	0.00
ALWAYS	183	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	0	1
60	0	1
62	0	1
66	0	1
70	0	1
79	0	1
98	0	1
100	0	1
101	0	1
102	0	1
103	0	1
110	0	1
112	0	1
116	0	1
120	0	1
130	0	1
134	0	1
136	0	1
138	0	1
143	0	1
148	0	1
166	0	1
170	0	1
171	0	1
172	0	1
173	0	1
174	0	1
175	0	1
			==> MISSING_ELSE
179	0	1
183	0	1
185	0	1
186	0	1
187	0	1
188	0	1

---

Cond Coverage for Module : spi_p2s

	Total	Covered	Percent
Conditions	42	0	0.00
Logical	42	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (csb_i ? 4'b0 : out_enable)
             --1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       101
 EXPRESSION (cnt == 3'h6)
            ------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       102
 EXPRESSION (cnt == 3'h2)
            ------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       103
 EXPRESSION (cnt == 3'b0)
            ------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       112
 EXPRESSION (order_i ? ({1'b0, out_shift_d[7:1]}) : ({out_shift_d[6:0], 1'b0}))
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       116
 EXPRESSION (order_i ? ({2'b0, out_shift_d[7:2]}) : ({out_shift_d[5:0], 2'b0}))
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       120
 EXPRESSION (order_i ? ({4'b0, out_shift_d[7:4]}) : ({out_shift_d[3:0], 4'b0}))
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       130
 EXPRESSION (first_beat ? data_i : out_shift)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       138
 EXPRESSION (order_i ? (((!first_beat)) ? out_shift[0] : data_i[0]) : (((!first_beat)) ? out_shift[7] : data_i[7]))
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       138
 SUB-EXPRESSION (((!first_beat)) ? out_shift[0] : data_i[0])
                 -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       138
 SUB-EXPRESSION (((!first_beat)) ? out_shift[7] : data_i[7])
                 -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       143
 EXPRESSION (order_i ? (((!first_beat)) ? out_shift[1:0] : data_i[1:0]) : (((!first_beat)) ? out_shift[7:6] : data_i[7:6]))
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       143
 SUB-EXPRESSION (((!first_beat)) ? out_shift[1:0] : data_i[1:0])
                 -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       143
 SUB-EXPRESSION (((!first_beat)) ? out_shift[7:6] : data_i[7:6])
                 -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       148
 EXPRESSION (order_i ? (((!first_beat)) ? out_shift[3:0] : data_i[3:0]) : (((!first_beat)) ? out_shift[7:4] : data_i[7:4]))
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       148
 SUB-EXPRESSION (((!first_beat)) ? out_shift[3:0] : data_i[3:0])
                 -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       148
 SUB-EXPRESSION (((!first_beat)) ? out_shift[7:4] : data_i[7:4])
                 -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       179
 EXPRESSION (cnt == '0)
            -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       186
 EXPRESSION (cnt == 3'('h00000007))
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       187
 EXPRESSION (cnt == 3'('h00000003))
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       188
 EXPRESSION (cnt == 3'('b1))
            --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Module : spi_p2s

	Line No.	Total	Covered	Percent
Branches		40	0	0.00
TERNARY	79	2	0	0.00
TERNARY	130	2	0	0.00
CASE	60	4	0	0.00
CASE	100	4	0	0.00
CASE	110	7	0	0.00
CASE	136	13	0	0.00
IF	170	4	0	0.00
CASE	185	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	(csb_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	130	(first_beat) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	60	case (io_mode)

Branches:

-1-	Status	Tests
SingleIO	Not Covered
DualIO	Not Covered
QuadIO	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	100	case (io_mode)

Branches:

-1-	Status	Tests
SingleIO	Not Covered
DualIO	Not Covered
QuadIO	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	110	case (io_mode)
-2-:	112	(order_i) ? 
-3-:	116	(order_i) ? 
-4-:	120	(order_i) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
SingleIO	1	-	-	Not Covered
SingleIO	0	-	-	Not Covered
DualIO	-	1	-	Not Covered
DualIO	-	0	-	Not Covered
QuadIO	-	-	1	Not Covered
QuadIO	-	-	0	Not Covered
default	-	-	-	Not Covered

	LineNo.	Expression
-1-:	136	case (io_mode)
-2-:	138	(order_i) ? 
-3-:	138	((!first_beat)) ? 
-4-:	138	((!first_beat)) ? 
-5-:	143	(order_i) ? 
-6-:	143	((!first_beat)) ? 
-7-:	143	((!first_beat)) ? 
-8-:	148	(order_i) ? 
-9-:	148	((!first_beat)) ? 
-10-:	148	((!first_beat)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	Status	Tests
SingleIO	1	1	-	-	-	-	-	-	-	Not Covered
SingleIO	1	0	-	-	-	-	-	-	-	Not Covered
SingleIO	0	-	1	-	-	-	-	-	-	Not Covered
SingleIO	0	-	0	-	-	-	-	-	-	Not Covered
DualIO	-	-	-	1	1	-	-	-	-	Not Covered
DualIO	-	-	-	1	0	-	-	-	-	Not Covered
DualIO	-	-	-	0	-	1	-	-	-	Not Covered
DualIO	-	-	-	0	-	0	-	-	-	Not Covered
QuadIO	-	-	-	-	-	-	1	1	-	Not Covered
QuadIO	-	-	-	-	-	-	1	0	-	Not Covered
QuadIO	-	-	-	-	-	-	0	-	1	Not Covered
QuadIO	-	-	-	-	-	-	0	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	170	if ((!rst_ni))
-2-:	172	if (last_beat)
-3-:	174	if (data_valid_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	185	case (io_mode)

Branches:

-1-	Status	Tests
SingleIO	Not Covered
DualIO	Not Covered
QuadIO	Not Covered
default	Not Covered