Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 0 | 0.00 |
ALWAYS | 31 | 3 | 0 | 0.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 0 | 0.00 |
CONT_ASSIGN | 97 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
0 |
1 |
32 |
0 |
1 |
34 |
0 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
0 |
1 |
90 |
0 |
1 |
92 |
0 |
1 |
97 |
0 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 0 | 0.00 |
Logical | 8 | 0 | 0.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
0 |
0.00 |
IF |
31 |
2 |
0 |
0.00 |
IF |
89 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 0 | 0.00 |
ALWAYS | 31 | 3 | 0 | 0.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 0 | 0.00 |
CONT_ASSIGN | 97 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
0 |
1 |
32 |
0 |
1 |
34 |
0 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
0 |
1 |
90 |
0 |
1 |
92 |
0 |
1 |
97 |
0 |
1 |
Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 0 | 0.00 |
Logical | 8 | 0 | 0.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
0 |
0.00 |
IF |
31 |
2 |
0 |
0.00 |
IF |
89 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 0 | 0.00 |
ALWAYS | 31 | 3 | 0 | 0.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 0 | 0.00 |
CONT_ASSIGN | 97 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
0 |
1 |
32 |
0 |
1 |
34 |
0 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
0 |
1 |
90 |
0 |
1 |
92 |
0 |
1 |
97 |
0 |
1 |
Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 0 | 0.00 |
Logical | 8 | 0 | 0.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
0 |
0.00 |
IF |
31 |
2 |
0 |
0.00 |
IF |
89 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 0 | 0.00 |
ALWAYS | 31 | 3 | 0 | 0.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 0 | 0.00 |
CONT_ASSIGN | 97 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
0 |
1 |
32 |
0 |
1 |
34 |
0 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
0 |
1 |
90 |
0 |
1 |
92 |
0 |
1 |
97 |
0 |
1 |
Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
| Total | Covered | Percent |
Conditions | 8 | 0 | 0.00 |
Logical | 8 | 0 | 0.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
0 |
0.00 |
IF |
31 |
2 |
0 |
0.00 |
IF |
89 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|