Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
18.78 0.00 0.00 75.11 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 0.00 0.00 0.00



Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
18.78 0.00 0.00 75.11 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 0.00 0.00 0.00



Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 0.00 u_upload


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 0.00 0.00 0.00

Line Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
TOTAL700.00
ALWAYS31300.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS89300.00
CONT_ASSIGN97100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 0 1
32 0 1
34 0 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 0 1
90 0 1
92 0 1
97 0 1


Cond Coverage for Module : prim_pulse_sync
TotalCoveredPercent
Conditions800.00
Logical800.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered
11Not Covered

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
Branches 4 0 0.00
IF 31 2 0 0.00
IF 89 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
Line No.TotalCoveredPercent
TOTAL700.00
ALWAYS31300.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS89300.00
CONT_ASSIGN97100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 0 1
32 0 1
34 0 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 0 1
90 0 1
92 0 1
97 0 1


Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
TotalCoveredPercent
Conditions800.00
Logical800.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered
11Not Covered

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
Line No.TotalCoveredPercent
Branches 4 0 0.00
IF 31 2 0 0.00
IF 89 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
Line No.TotalCoveredPercent
TOTAL700.00
ALWAYS31300.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS89300.00
CONT_ASSIGN97100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 0 1
32 0 1
34 0 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 0 1
90 0 1
92 0 1
97 0 1


Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
TotalCoveredPercent
Conditions800.00
Logical800.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered
11Not Covered

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
Line No.TotalCoveredPercent
Branches 4 0 0.00
IF 31 2 0 0.00
IF 89 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
Line No.TotalCoveredPercent
TOTAL700.00
ALWAYS31300.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS89300.00
CONT_ASSIGN97100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 0 1
32 0 1
34 0 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 0 1
90 0 1
92 0 1
97 0 1


Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
TotalCoveredPercent
Conditions800.00
Logical800.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered
11Not Covered

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
Line No.TotalCoveredPercent
Branches 4 0 0.00
IF 31 2 0 0.00
IF 89 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%