Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3398 |
0 |
0 |
T5 |
2266 |
1 |
0 |
0 |
T8 |
8518 |
50 |
0 |
0 |
T9 |
10170 |
1 |
0 |
0 |
T12 |
1330 |
0 |
0 |
0 |
T15 |
8031 |
272 |
0 |
0 |
T16 |
5106 |
14 |
0 |
0 |
T18 |
0 |
6 |
0 |
0 |
T19 |
0 |
120 |
0 |
0 |
T20 |
0 |
233 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T25 |
3902 |
0 |
0 |
0 |
T26 |
35486 |
0 |
0 |
0 |
T27 |
35122 |
0 |
0 |
0 |
T28 |
27601 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1168 |
0 |
0 |
T2 |
180562 |
481 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
34 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
18 |
0 |
0 |
T24 |
6536 |
6 |
0 |
0 |
T26 |
0 |
45 |
0 |
0 |
T29 |
0 |
7 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T51 |
0 |
190 |
0 |
0 |
T52 |
0 |
12 |
0 |
0 |
T53 |
0 |
8 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1299 |
0 |
0 |
T2 |
180562 |
428 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
70 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
17 |
0 |
0 |
T24 |
6536 |
3 |
0 |
0 |
T26 |
0 |
44 |
0 |
0 |
T29 |
0 |
7 |
0 |
0 |
T35 |
0 |
7 |
0 |
0 |
T51 |
0 |
239 |
0 |
0 |
T53 |
0 |
7 |
0 |
0 |
T54 |
0 |
79 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1572 |
0 |
0 |
T2 |
180562 |
463 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
44 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
42 |
0 |
0 |
T24 |
6536 |
9 |
0 |
0 |
T26 |
0 |
72 |
0 |
0 |
T29 |
0 |
10 |
0 |
0 |
T35 |
0 |
10 |
0 |
0 |
T51 |
0 |
187 |
0 |
0 |
T52 |
0 |
29 |
0 |
0 |
T53 |
0 |
35 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
7612 |
0 |
0 |
T2 |
180562 |
466 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
44 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
146 |
0 |
0 |
T24 |
6536 |
85 |
0 |
0 |
T26 |
0 |
627 |
0 |
0 |
T29 |
0 |
105 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T51 |
0 |
229 |
0 |
0 |
T52 |
0 |
23 |
0 |
0 |
T53 |
0 |
115 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
6675 |
0 |
0 |
T2 |
180562 |
411 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
60 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
253 |
0 |
0 |
T24 |
6536 |
62 |
0 |
0 |
T26 |
0 |
388 |
0 |
0 |
T29 |
0 |
242 |
0 |
0 |
T35 |
0 |
146 |
0 |
0 |
T51 |
0 |
216 |
0 |
0 |
T52 |
0 |
20 |
0 |
0 |
T53 |
0 |
261 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
7090 |
0 |
0 |
T2 |
180562 |
430 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
34 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
435 |
0 |
0 |
T24 |
6536 |
2 |
0 |
0 |
T26 |
0 |
727 |
0 |
0 |
T29 |
0 |
260 |
0 |
0 |
T35 |
0 |
108 |
0 |
0 |
T51 |
0 |
225 |
0 |
0 |
T52 |
0 |
5 |
0 |
0 |
T53 |
0 |
219 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
6375 |
0 |
0 |
T2 |
180562 |
450 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
74 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
23 |
0 |
0 |
T24 |
6536 |
7 |
0 |
0 |
T26 |
0 |
494 |
0 |
0 |
T29 |
0 |
265 |
0 |
0 |
T35 |
0 |
92 |
0 |
0 |
T51 |
0 |
200 |
0 |
0 |
T52 |
0 |
19 |
0 |
0 |
T53 |
0 |
11 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
7545 |
0 |
0 |
T2 |
180562 |
448 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
74 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
158 |
0 |
0 |
T24 |
6536 |
53 |
0 |
0 |
T26 |
0 |
709 |
0 |
0 |
T29 |
0 |
156 |
0 |
0 |
T35 |
0 |
107 |
0 |
0 |
T51 |
0 |
242 |
0 |
0 |
T52 |
0 |
16 |
0 |
0 |
T53 |
0 |
24 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
6576 |
0 |
0 |
T2 |
180562 |
481 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
78 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
161 |
0 |
0 |
T24 |
6536 |
0 |
0 |
0 |
T26 |
0 |
702 |
0 |
0 |
T29 |
0 |
237 |
0 |
0 |
T35 |
0 |
127 |
0 |
0 |
T51 |
0 |
225 |
0 |
0 |
T53 |
0 |
221 |
0 |
0 |
T54 |
0 |
864 |
0 |
0 |
T55 |
0 |
1476 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
6064 |
0 |
0 |
T2 |
180562 |
417 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
58 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
32 |
0 |
0 |
T24 |
6536 |
50 |
0 |
0 |
T26 |
0 |
522 |
0 |
0 |
T29 |
0 |
144 |
0 |
0 |
T35 |
0 |
119 |
0 |
0 |
T51 |
0 |
197 |
0 |
0 |
T53 |
0 |
150 |
0 |
0 |
T54 |
0 |
795 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
6722 |
0 |
0 |
T2 |
180562 |
487 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
85 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
159 |
0 |
0 |
T24 |
6536 |
3 |
0 |
0 |
T26 |
0 |
784 |
0 |
0 |
T29 |
0 |
160 |
0 |
0 |
T35 |
0 |
6 |
0 |
0 |
T51 |
0 |
203 |
0 |
0 |
T52 |
0 |
10 |
0 |
0 |
T53 |
0 |
235 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3221 |
0 |
0 |
T2 |
180562 |
406 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
69 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
135 |
0 |
0 |
T24 |
6536 |
21 |
0 |
0 |
T26 |
0 |
224 |
0 |
0 |
T29 |
0 |
58 |
0 |
0 |
T35 |
0 |
53 |
0 |
0 |
T51 |
0 |
236 |
0 |
0 |
T52 |
0 |
8 |
0 |
0 |
T53 |
0 |
14 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3038 |
0 |
0 |
T2 |
180562 |
441 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
35 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
93 |
0 |
0 |
T24 |
6536 |
28 |
0 |
0 |
T26 |
0 |
169 |
0 |
0 |
T29 |
0 |
8 |
0 |
0 |
T35 |
0 |
6 |
0 |
0 |
T51 |
0 |
240 |
0 |
0 |
T52 |
0 |
6 |
0 |
0 |
T53 |
0 |
25 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3474 |
0 |
0 |
T2 |
180562 |
447 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
64 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
121 |
0 |
0 |
T24 |
6536 |
8 |
0 |
0 |
T26 |
0 |
358 |
0 |
0 |
T29 |
0 |
66 |
0 |
0 |
T35 |
0 |
58 |
0 |
0 |
T51 |
0 |
189 |
0 |
0 |
T53 |
0 |
62 |
0 |
0 |
T54 |
0 |
388 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3354 |
0 |
0 |
T2 |
180562 |
425 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
39 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
84 |
0 |
0 |
T24 |
6536 |
0 |
0 |
0 |
T26 |
0 |
215 |
0 |
0 |
T29 |
0 |
45 |
0 |
0 |
T35 |
0 |
44 |
0 |
0 |
T51 |
0 |
238 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
78 |
0 |
0 |
T54 |
0 |
491 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3270 |
0 |
0 |
T2 |
180562 |
455 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
71 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
74 |
0 |
0 |
T24 |
6536 |
27 |
0 |
0 |
T26 |
0 |
219 |
0 |
0 |
T29 |
0 |
10 |
0 |
0 |
T35 |
0 |
45 |
0 |
0 |
T51 |
0 |
207 |
0 |
0 |
T52 |
0 |
12 |
0 |
0 |
T53 |
0 |
44 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3449 |
0 |
0 |
T2 |
180562 |
484 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
29 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
88 |
0 |
0 |
T24 |
6536 |
49 |
0 |
0 |
T26 |
0 |
320 |
0 |
0 |
T29 |
0 |
59 |
0 |
0 |
T35 |
0 |
28 |
0 |
0 |
T51 |
0 |
204 |
0 |
0 |
T52 |
0 |
19 |
0 |
0 |
T53 |
0 |
46 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3753 |
0 |
0 |
T2 |
180562 |
433 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
87 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
107 |
0 |
0 |
T24 |
6536 |
26 |
0 |
0 |
T26 |
0 |
419 |
0 |
0 |
T29 |
0 |
36 |
0 |
0 |
T35 |
0 |
5 |
0 |
0 |
T51 |
0 |
222 |
0 |
0 |
T52 |
0 |
8 |
0 |
0 |
T53 |
0 |
55 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3528 |
0 |
0 |
T2 |
180562 |
412 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
48 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
194 |
0 |
0 |
T24 |
6536 |
36 |
0 |
0 |
T26 |
0 |
418 |
0 |
0 |
T29 |
0 |
61 |
0 |
0 |
T35 |
0 |
68 |
0 |
0 |
T51 |
0 |
197 |
0 |
0 |
T53 |
0 |
88 |
0 |
0 |
T54 |
0 |
451 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3395 |
0 |
0 |
T2 |
180562 |
426 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
87 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
76 |
0 |
0 |
T24 |
6536 |
25 |
0 |
0 |
T26 |
0 |
310 |
0 |
0 |
T29 |
0 |
9 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T51 |
0 |
207 |
0 |
0 |
T52 |
0 |
32 |
0 |
0 |
T53 |
0 |
58 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3129 |
0 |
0 |
T2 |
180562 |
504 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
85 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
74 |
0 |
0 |
T24 |
6536 |
19 |
0 |
0 |
T26 |
0 |
202 |
0 |
0 |
T29 |
0 |
42 |
0 |
0 |
T35 |
0 |
61 |
0 |
0 |
T51 |
0 |
259 |
0 |
0 |
T52 |
0 |
12 |
0 |
0 |
T53 |
0 |
53 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
2940 |
0 |
0 |
T2 |
180562 |
397 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
63 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
24 |
0 |
0 |
T24 |
6536 |
46 |
0 |
0 |
T26 |
0 |
218 |
0 |
0 |
T29 |
0 |
6 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T51 |
0 |
224 |
0 |
0 |
T52 |
0 |
9 |
0 |
0 |
T53 |
0 |
151 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3353 |
0 |
0 |
T2 |
180562 |
395 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
54 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
88 |
0 |
0 |
T24 |
6536 |
102 |
0 |
0 |
T26 |
0 |
78 |
0 |
0 |
T29 |
0 |
53 |
0 |
0 |
T35 |
0 |
9 |
0 |
0 |
T51 |
0 |
224 |
0 |
0 |
T52 |
0 |
6 |
0 |
0 |
T53 |
0 |
18 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3331 |
0 |
0 |
T2 |
180562 |
422 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
43 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
108 |
0 |
0 |
T24 |
6536 |
0 |
0 |
0 |
T26 |
0 |
231 |
0 |
0 |
T29 |
0 |
52 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T51 |
0 |
207 |
0 |
0 |
T52 |
0 |
16 |
0 |
0 |
T53 |
0 |
63 |
0 |
0 |
T54 |
0 |
365 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3425 |
0 |
0 |
T2 |
180562 |
460 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
94 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
65 |
0 |
0 |
T24 |
6536 |
51 |
0 |
0 |
T26 |
0 |
102 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T51 |
0 |
228 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
93 |
0 |
0 |
T54 |
0 |
441 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3471 |
0 |
0 |
T2 |
180562 |
405 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
33 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
74 |
0 |
0 |
T24 |
6536 |
55 |
0 |
0 |
T26 |
0 |
350 |
0 |
0 |
T29 |
0 |
54 |
0 |
0 |
T35 |
0 |
9 |
0 |
0 |
T51 |
0 |
240 |
0 |
0 |
T53 |
0 |
8 |
0 |
0 |
T54 |
0 |
476 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3545 |
0 |
0 |
T2 |
180562 |
471 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
64 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
140 |
0 |
0 |
T24 |
6536 |
65 |
0 |
0 |
T26 |
0 |
145 |
0 |
0 |
T29 |
0 |
45 |
0 |
0 |
T35 |
0 |
7 |
0 |
0 |
T51 |
0 |
247 |
0 |
0 |
T52 |
0 |
18 |
0 |
0 |
T53 |
0 |
17 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3418 |
0 |
0 |
T2 |
180562 |
465 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
40 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
198 |
0 |
0 |
T24 |
6536 |
53 |
0 |
0 |
T26 |
0 |
160 |
0 |
0 |
T29 |
0 |
55 |
0 |
0 |
T35 |
0 |
41 |
0 |
0 |
T51 |
0 |
214 |
0 |
0 |
T52 |
0 |
6 |
0 |
0 |
T53 |
0 |
67 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3398 |
0 |
0 |
T2 |
180562 |
420 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
33 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
170 |
0 |
0 |
T24 |
6536 |
34 |
0 |
0 |
T26 |
0 |
346 |
0 |
0 |
T29 |
0 |
62 |
0 |
0 |
T35 |
0 |
36 |
0 |
0 |
T51 |
0 |
285 |
0 |
0 |
T52 |
0 |
31 |
0 |
0 |
T53 |
0 |
16 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3806 |
0 |
0 |
T2 |
180562 |
440 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
53 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T19 |
0 |
4 |
0 |
0 |
T21 |
0 |
197 |
0 |
0 |
T24 |
6536 |
40 |
0 |
0 |
T26 |
0 |
271 |
0 |
0 |
T29 |
0 |
40 |
0 |
0 |
T51 |
0 |
237 |
0 |
0 |
T52 |
0 |
6 |
0 |
0 |
T53 |
0 |
58 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3584 |
0 |
0 |
T2 |
180562 |
466 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
25 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
177 |
0 |
0 |
T24 |
6536 |
17 |
0 |
0 |
T26 |
0 |
294 |
0 |
0 |
T29 |
0 |
58 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T51 |
0 |
265 |
0 |
0 |
T52 |
0 |
2 |
0 |
0 |
T53 |
0 |
122 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3355 |
0 |
0 |
T2 |
180562 |
423 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
59 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
98 |
0 |
0 |
T24 |
6536 |
66 |
0 |
0 |
T26 |
0 |
238 |
0 |
0 |
T29 |
0 |
39 |
0 |
0 |
T35 |
0 |
25 |
0 |
0 |
T51 |
0 |
207 |
0 |
0 |
T53 |
0 |
50 |
0 |
0 |
T54 |
0 |
436 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3763 |
0 |
0 |
T2 |
180562 |
430 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
63 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
89 |
0 |
0 |
T24 |
6536 |
27 |
0 |
0 |
T26 |
0 |
314 |
0 |
0 |
T29 |
0 |
30 |
0 |
0 |
T51 |
0 |
246 |
0 |
0 |
T52 |
0 |
2 |
0 |
0 |
T53 |
0 |
106 |
0 |
0 |
T54 |
0 |
432 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3600 |
0 |
0 |
T2 |
180562 |
446 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
39 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
187 |
0 |
0 |
T24 |
6536 |
52 |
0 |
0 |
T26 |
0 |
246 |
0 |
0 |
T29 |
0 |
35 |
0 |
0 |
T35 |
0 |
73 |
0 |
0 |
T51 |
0 |
203 |
0 |
0 |
T52 |
0 |
8 |
0 |
0 |
T53 |
0 |
77 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
3243 |
0 |
0 |
T2 |
180562 |
469 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
51 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
138 |
0 |
0 |
T24 |
6536 |
0 |
0 |
0 |
T26 |
0 |
194 |
0 |
0 |
T29 |
0 |
7 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T51 |
0 |
201 |
0 |
0 |
T52 |
0 |
3 |
0 |
0 |
T53 |
0 |
45 |
0 |
0 |
T54 |
0 |
504 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1489 |
0 |
0 |
T2 |
180562 |
499 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
86 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
25 |
0 |
0 |
T24 |
6536 |
6 |
0 |
0 |
T26 |
0 |
49 |
0 |
0 |
T29 |
0 |
12 |
0 |
0 |
T35 |
0 |
7 |
0 |
0 |
T51 |
0 |
216 |
0 |
0 |
T52 |
0 |
8 |
0 |
0 |
T53 |
0 |
7 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1435 |
0 |
0 |
T2 |
180562 |
458 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
46 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
47 |
0 |
0 |
T24 |
6536 |
1 |
0 |
0 |
T26 |
0 |
60 |
0 |
0 |
T29 |
0 |
5 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T51 |
0 |
232 |
0 |
0 |
T53 |
0 |
37 |
0 |
0 |
T54 |
0 |
90 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1483 |
0 |
0 |
T2 |
180562 |
541 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
41 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
18 |
0 |
0 |
T24 |
6536 |
11 |
0 |
0 |
T26 |
0 |
52 |
0 |
0 |
T29 |
0 |
9 |
0 |
0 |
T35 |
0 |
9 |
0 |
0 |
T51 |
0 |
205 |
0 |
0 |
T52 |
0 |
10 |
0 |
0 |
T53 |
0 |
15 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1391 |
0 |
0 |
T2 |
180562 |
461 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
87 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
29 |
0 |
0 |
T24 |
6536 |
6 |
0 |
0 |
T26 |
0 |
51 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T51 |
0 |
199 |
0 |
0 |
T52 |
0 |
15 |
0 |
0 |
T53 |
0 |
16 |
0 |
0 |
T54 |
0 |
122 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1817 |
0 |
0 |
T2 |
180562 |
467 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
36 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
49 |
0 |
0 |
T24 |
6536 |
9 |
0 |
0 |
T26 |
0 |
79 |
0 |
0 |
T29 |
0 |
23 |
0 |
0 |
T35 |
0 |
10 |
0 |
0 |
T51 |
0 |
181 |
0 |
0 |
T52 |
0 |
12 |
0 |
0 |
T53 |
0 |
26 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
2832 |
0 |
0 |
T2 |
180562 |
417 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
81 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
53 |
0 |
0 |
T24 |
6536 |
23 |
0 |
0 |
T26 |
0 |
219 |
0 |
0 |
T29 |
0 |
55 |
0 |
0 |
T51 |
0 |
215 |
0 |
0 |
T52 |
0 |
6 |
0 |
0 |
T53 |
0 |
55 |
0 |
0 |
T56 |
0 |
23 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1501 |
0 |
0 |
T2 |
180562 |
393 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
91 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
33 |
0 |
0 |
T24 |
6536 |
4 |
0 |
0 |
T26 |
0 |
50 |
0 |
0 |
T29 |
0 |
8 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T51 |
0 |
269 |
0 |
0 |
T52 |
0 |
7 |
0 |
0 |
T53 |
0 |
15 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1483 |
0 |
0 |
T2 |
180562 |
430 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
71 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T24 |
6536 |
5 |
0 |
0 |
T26 |
0 |
55 |
0 |
0 |
T29 |
0 |
2 |
0 |
0 |
T35 |
0 |
11 |
0 |
0 |
T51 |
0 |
226 |
0 |
0 |
T52 |
0 |
6 |
0 |
0 |
T53 |
0 |
5 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1191 |
0 |
0 |
T2 |
180562 |
447 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
26 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
17 |
0 |
0 |
T24 |
6536 |
4 |
0 |
0 |
T26 |
0 |
25 |
0 |
0 |
T29 |
0 |
8 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T51 |
0 |
213 |
0 |
0 |
T52 |
0 |
7 |
0 |
0 |
T53 |
0 |
13 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1393 |
0 |
0 |
T2 |
180562 |
481 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
78 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
19 |
0 |
0 |
T24 |
6536 |
3 |
0 |
0 |
T26 |
0 |
49 |
0 |
0 |
T29 |
0 |
8 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T51 |
0 |
234 |
0 |
0 |
T52 |
0 |
13 |
0 |
0 |
T53 |
0 |
14 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1333 |
0 |
0 |
T2 |
180562 |
453 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
32 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
31 |
0 |
0 |
T24 |
6536 |
10 |
0 |
0 |
T26 |
0 |
21 |
0 |
0 |
T29 |
0 |
6 |
0 |
0 |
T51 |
0 |
275 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
22 |
0 |
0 |
T54 |
0 |
48 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1273 |
0 |
0 |
T2 |
180562 |
435 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
88 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
29 |
0 |
0 |
T24 |
6536 |
0 |
0 |
0 |
T26 |
0 |
42 |
0 |
0 |
T29 |
0 |
5 |
0 |
0 |
T51 |
0 |
200 |
0 |
0 |
T52 |
0 |
11 |
0 |
0 |
T53 |
0 |
19 |
0 |
0 |
T54 |
0 |
81 |
0 |
0 |
T55 |
0 |
84 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1820 |
0 |
0 |
T2 |
180562 |
430 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
76 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
61 |
0 |
0 |
T24 |
6536 |
12 |
0 |
0 |
T26 |
0 |
120 |
0 |
0 |
T29 |
0 |
18 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T51 |
0 |
209 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
47 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1354 |
0 |
0 |
T2 |
180562 |
476 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
66 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
20 |
0 |
0 |
T24 |
6536 |
4 |
0 |
0 |
T26 |
0 |
49 |
0 |
0 |
T29 |
0 |
11 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T51 |
0 |
230 |
0 |
0 |
T52 |
0 |
9 |
0 |
0 |
T53 |
0 |
7 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1976 |
0 |
0 |
T2 |
180562 |
484 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
61 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
45 |
0 |
0 |
T24 |
6536 |
5 |
0 |
0 |
T26 |
0 |
105 |
0 |
0 |
T29 |
0 |
1 |
0 |
0 |
T51 |
0 |
218 |
0 |
0 |
T52 |
0 |
24 |
0 |
0 |
T53 |
0 |
15 |
0 |
0 |
T54 |
0 |
277 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1441 |
0 |
0 |
T2 |
180562 |
420 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
65 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
33 |
0 |
0 |
T24 |
6536 |
0 |
0 |
0 |
T26 |
0 |
65 |
0 |
0 |
T29 |
0 |
17 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T51 |
0 |
213 |
0 |
0 |
T52 |
0 |
3 |
0 |
0 |
T53 |
0 |
24 |
0 |
0 |
T54 |
0 |
128 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1251 |
0 |
0 |
T2 |
180562 |
471 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
45 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
18 |
0 |
0 |
T24 |
6536 |
4 |
0 |
0 |
T26 |
0 |
30 |
0 |
0 |
T29 |
0 |
4 |
0 |
0 |
T51 |
0 |
248 |
0 |
0 |
T53 |
0 |
18 |
0 |
0 |
T54 |
0 |
56 |
0 |
0 |
T55 |
0 |
83 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1286 |
0 |
0 |
T2 |
180562 |
450 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
38 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
25 |
0 |
0 |
T24 |
6536 |
6 |
0 |
0 |
T26 |
0 |
21 |
0 |
0 |
T29 |
0 |
9 |
0 |
0 |
T35 |
0 |
5 |
0 |
0 |
T51 |
0 |
194 |
0 |
0 |
T52 |
0 |
8 |
0 |
0 |
T53 |
0 |
10 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1315 |
0 |
0 |
T2 |
180562 |
478 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
110 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
25 |
0 |
0 |
T24 |
6536 |
8 |
0 |
0 |
T26 |
0 |
34 |
0 |
0 |
T29 |
0 |
9 |
0 |
0 |
T51 |
0 |
188 |
0 |
0 |
T52 |
0 |
31 |
0 |
0 |
T53 |
0 |
16 |
0 |
0 |
T54 |
0 |
39 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1426 |
0 |
0 |
T2 |
180562 |
471 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
146 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
22 |
0 |
0 |
T24 |
6536 |
8 |
0 |
0 |
T26 |
0 |
44 |
0 |
0 |
T29 |
0 |
8 |
0 |
0 |
T35 |
0 |
7 |
0 |
0 |
T51 |
0 |
219 |
0 |
0 |
T52 |
0 |
18 |
0 |
0 |
T53 |
0 |
15 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1235 |
0 |
0 |
T2 |
180562 |
435 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
69 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
11 |
0 |
0 |
T24 |
6536 |
3 |
0 |
0 |
T26 |
0 |
37 |
0 |
0 |
T29 |
0 |
4 |
0 |
0 |
T35 |
0 |
9 |
0 |
0 |
T51 |
0 |
226 |
0 |
0 |
T52 |
0 |
2 |
0 |
0 |
T53 |
0 |
10 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2291755 |
1288 |
0 |
0 |
T2 |
180562 |
450 |
0 |
0 |
T3 |
962 |
0 |
0 |
0 |
T4 |
20041 |
69 |
0 |
0 |
T6 |
955 |
0 |
0 |
0 |
T7 |
4461 |
0 |
0 |
0 |
T10 |
3313 |
0 |
0 |
0 |
T11 |
903 |
0 |
0 |
0 |
T13 |
1537 |
0 |
0 |
0 |
T14 |
4363 |
0 |
0 |
0 |
T21 |
0 |
15 |
0 |
0 |
T24 |
6536 |
0 |
0 |
0 |
T26 |
0 |
26 |
0 |
0 |
T29 |
0 |
8 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T51 |
0 |
228 |
0 |
0 |
T52 |
0 |
9 |
0 |
0 |
T53 |
0 |
18 |
0 |
0 |
T57 |
0 |
4 |
0 |
0 |