Unified Coverage Report :: Module :: prim_ram_1r1w_async_adv

Module : prim_ram_1r1w_async_adv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem	0.00	0.00				0.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem	0.00	0.00				0.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_spid_dpram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_mem	0.00	0.00				0.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_spid_dpram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_mem	0.00	0.00				0.00

Line Coverage for Module : prim_ram_1r1w_async_adv

	Line No.	Total	Covered	Percent
TOTAL		28	0	0.00
ALWAYS	118	3	0	0.00
CONT_ASSIGN	125	1	0	0.00
CONT_ASSIGN	126	1	0	0.00
CONT_ASSIGN	128	1	0	0.00
CONT_ASSIGN	129	1	0	0.00
CONT_ASSIGN	130	1	0	0.00
CONT_ASSIGN	131	1	0	0.00
CONT_ASSIGN	132	1	0	0.00
ALWAYS	180	8	0	0.00
CONT_ASSIGN	203	1	0	0.00
CONT_ASSIGN	234	1	0	0.00
CONT_ASSIGN	235	1	0	0.00
CONT_ASSIGN	236	1	0	0.00
CONT_ASSIGN	237	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	258	1	0	0.00
CONT_ASSIGN	259	1	0	0.00
CONT_ASSIGN	261	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' or '../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
118	0	1
119	0	1
121	0	1
125	0	1
126	0	1
128	0	1
129	0	1
130	0	1
131	0	1
132	0	1
180	0	1
181	0	1
185	0	1
186	0	1
187	0	1
190	0	1
191	0	1
193	0	1
203	0	1
234	0	1
235	0	1
236	0	1
237	0	1
239	0	1
240	0	1
258	0	1
259	0	1
261	0	1

---

Branch Coverage for Module : prim_ram_1r1w_async_adv

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	118	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' or '../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	118	if ((!rst_b_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem

	Line No.	Total	Covered	Percent
TOTAL		28	0	0.00
ALWAYS	118	3	0	0.00
CONT_ASSIGN	125	1	0	0.00
CONT_ASSIGN	126	1	0	0.00
CONT_ASSIGN	128	1	0	0.00
CONT_ASSIGN	129	1	0	0.00
CONT_ASSIGN	130	1	0	0.00
CONT_ASSIGN	131	1	0	0.00
CONT_ASSIGN	132	1	0	0.00
ALWAYS	180	8	0	0.00
CONT_ASSIGN	203	1	0	0.00
CONT_ASSIGN	234	1	0	0.00
CONT_ASSIGN	235	1	0	0.00
CONT_ASSIGN	236	1	0	0.00
CONT_ASSIGN	237	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	258	1	0	0.00
CONT_ASSIGN	259	1	0	0.00
CONT_ASSIGN	261	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' or '../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
118	0	1
119	0	1
121	0	1
125	0	1
126	0	1
128	0	1
129	0	1
130	0	1
131	0	1
132	0	1
180	0	1
181	0	1
185	0	1
186	0	1
187	0	1
190	0	1
191	0	1
193	0	1
203	0	1
234	0	1
235	0	1
236	0	1
237	0	1
239	0	1
240	0	1
258	0	1
259	0	1
261	0	1

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	118	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' or '../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	118	if ((!rst_b_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem

	Line No.	Total	Covered	Percent
TOTAL		28	0	0.00
ALWAYS	118	3	0	0.00
CONT_ASSIGN	125	1	0	0.00
CONT_ASSIGN	126	1	0	0.00
CONT_ASSIGN	128	1	0	0.00
CONT_ASSIGN	129	1	0	0.00
CONT_ASSIGN	130	1	0	0.00
CONT_ASSIGN	131	1	0	0.00
CONT_ASSIGN	132	1	0	0.00
ALWAYS	180	8	0	0.00
CONT_ASSIGN	203	1	0	0.00
CONT_ASSIGN	234	1	0	0.00
CONT_ASSIGN	235	1	0	0.00
CONT_ASSIGN	236	1	0	0.00
CONT_ASSIGN	237	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	258	1	0	0.00
CONT_ASSIGN	259	1	0	0.00
CONT_ASSIGN	261	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' or '../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
118	0	1
119	0	1
121	0	1
125	0	1
126	0	1
128	0	1
129	0	1
130	0	1
131	0	1
132	0	1
180	0	1
181	0	1
185	0	1
186	0	1
187	0	1
190	0	1
191	0	1
193	0	1
203	0	1
234	0	1
235	0	1
236	0	1
237	0	1
239	0	1
240	0	1
258	0	1
259	0	1
261	0	1

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	118	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv' or '../src/lowrisc_prim_ram_1r1w_async_adv_0.1/rtl/prim_ram_1r1w_async_adv.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	118	if ((!rst_b_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered