584c3d46af| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.510s | 153.963us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 2.430s | 350.549us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 35.900s | 3.747ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 23.570s | 1.808ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 3.730s | 156.727us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.430s | 350.549us | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 23.570s | 1.808ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.700s | 11.521us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 1.980s | 29.107us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | csb_read | spi_device_csb_read | 0 | 50 | 0.00 | ||
| V2 | mem_parity | spi_device_mem_parity | 0 | 20 | 0.00 | ||
| V2 | mem_cfg | spi_device_ram_cfg | 0 | 1 | 0.00 | ||
| V2 | tpm_read | spi_device_tpm_rw | 0 | 50 | 0.00 | ||
| V2 | tpm_write | spi_device_tpm_rw | 0 | 50 | 0.00 | ||
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 0 | 50 | 0.00 | ||
| spi_device_tpm_sts_read | 0 | 50 | 0.00 | ||||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 0 | 50 | 0.00 | ||
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | cmd_info_slots | spi_device_flash_all | 0 | 50 | 0.00 | ||
| V2 | cmd_read_status | spi_device_intercept | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | cmd_read_jedec | spi_device_intercept | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | cmd_read_sfdp | spi_device_intercept | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | cmd_fast_read | spi_device_intercept | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | cmd_read_pipeline | spi_device_intercept | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | flash_cmd_upload | spi_device_upload | 0 | 50 | 0.00 | ||
| V2 | mailbox_command | spi_device_mailbox | 0 | 50 | 0.00 | ||
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 0 | 50 | 0.00 | ||
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 0 | 50 | 0.00 | ||
| V2 | cmd_read_buffer | spi_device_flash_mode | 0 | 50 | 0.00 | ||
| spi_device_read_buffer_direct | 0 | 50 | 0.00 | ||||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | quad_spi | spi_device_flash_all | 0 | 50 | 0.00 | ||
| V2 | dual_spi | spi_device_flash_all | 0 | 50 | 0.00 | ||
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 0 | 50 | 0.00 | ||
| V2 | write_enable_disable | spi_device_cfg_cmd | 0 | 50 | 0.00 | ||
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 0 | 50 | 0.00 | ||
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 0 | 50 | 0.00 | ||
| V2 | stress_all | spi_device_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | spi_device_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | spi_device_intr_test | 0.790s | 40.753us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 6.450s | 2.061ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 6.450s | 2.061ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.510s | 153.963us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.430s | 350.549us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 23.570s | 1.808ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.330s | 422.856us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.510s | 153.963us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.430s | 350.549us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 23.570s | 1.808ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.330s | 422.856us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 90 | 961 | 9.37 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 0 | 5 | 0.00 | ||
| spi_device_tl_intg_err | 19.620s | 1.170ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 19.620s | 1.170ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 20 | 25 | 80.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_device_flash_mode_ignore_cmds | 0 | 50 | 0.00 | |||
| TOTAL | 175 | 1151 | 15.20 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 22 | 22 | 3 | 13.64 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 59.33 | 70.94 | 74.27 | 75.00 | 0.00 | 76.99 | 100.00 | 18.12 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 488 failures:
Test spi_device_csb_read has 33 failures.
0.spi_device_csb_read.80142206864448052657800882065472151181434829961229788724788448734146816950896
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_csb_read/latest/run.log
1.spi_device_csb_read.47148129107219699221283943644910367640856518251227393863108466372435283951868
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_csb_read/latest/run.log
... and 31 more failures.
Test spi_device_ram_cfg has 1 failures.
Test spi_device_tpm_all has 18 failures.
0.spi_device_tpm_all.16341586257668339874414092090616062464267031905443803980901466123840319945931
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_tpm_all/latest/run.log
2.spi_device_tpm_all.94720548315480130275597849057436023606108143678563700021124216403006680683965
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_tpm_all/latest/run.log
... and 16 more failures.
Test spi_device_tpm_rw has 18 failures.
0.spi_device_tpm_rw.54126782001536578987986436113404517270018607488752890499343348661329919569139
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_tpm_rw/latest/run.log
2.spi_device_tpm_rw.83991143977619515659953507741265710201648268160679714621074769949513309429414
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_tpm_rw/latest/run.log
... and 16 more failures.
Test spi_device_pass_addr_payload_swap has 18 failures.
0.spi_device_pass_addr_payload_swap.50047710682696674925792239692796578978020256511059336111843903246673621934995
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_pass_addr_payload_swap/latest/run.log
2.spi_device_pass_addr_payload_swap.76260479452609172894416714899281254928923433279366336665400167912154480146067
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_pass_addr_payload_swap/latest/run.log
... and 16 more failures.
... and 17 more tests.
Job killed most likely because its dependent job failed. has 488 failures:
0.spi_device_mem_parity.81804483296538196087222975637594815454624029430285913055587515940792235153871
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log
1.spi_device_mem_parity.77349280532051450871039995852134067289681128215701226679019208913155972240200
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log
... and 16 more failures.
0.spi_device_tpm_read_hw_reg.91406181560008464014495663264620103061639174338252582062462421092910552704808
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_tpm_read_hw_reg/latest/run.log
2.spi_device_tpm_read_hw_reg.29414665923592532638868034005643656810160773601959537308643537592826008148081
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_tpm_read_hw_reg/latest/run.log
... and 16 more failures.
0.spi_device_tpm_sts_read.54551366087507948115564296047991816762004201360283472337873168829916820688976
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_tpm_sts_read/latest/run.log
2.spi_device_tpm_sts_read.75235591777915468554363028325596848952398460303129925743268783989841532592878
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_tpm_sts_read/latest/run.log
... and 16 more failures.
0.spi_device_pass_cmd_filtering.8039534949599104836749463001558935173608870800195477697241371536742514672914
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_pass_cmd_filtering/latest/run.log
2.spi_device_pass_cmd_filtering.96012249494147562067446337616041328877425442437468210619509935873070779183455
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_pass_cmd_filtering/latest/run.log
... and 16 more failures.
0.spi_device_intercept.39413746504198814034650727438648963287017974968259152562367581750392672288005
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_intercept/latest/run.log
2.spi_device_intercept.33341847534867153118666468449785796793747532553245232091937836584972212179200
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_intercept/latest/run.log
... and 16 more failures.