SPI_DEVICE/1R1W Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: `3707c48f56`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.365m	713.389ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.460s	137.629us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.850s	99.295us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.680s	2.169ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.220s	911.486us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.860s	289.294us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.850s	99.295us	20	20	100.00
		spi_device_csr_aliasing	23.220s	911.486us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	13.204us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.990s	53.043us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	21.503us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.840s	1.176us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	16.649us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.560s	545.303us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.560s	545.303us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.330s	15.131ms	50	50	100.00
		spi_device_tpm_sts_read	1.030s	534.879us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	59.000s	22.045ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	23.180s	8.766ms	50	50	100.00
		spi_device_flash_all	8.495m	74.555ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	45.360s	175.978ms	50	50	100.00
		spi_device_flash_all	8.495m	74.555ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	45.360s	175.978ms	50	50	100.00
		spi_device_flash_all	8.495m	74.555ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.495m	74.555ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	23.720s	2.417ms	50	50	100.00
		spi_device_flash_all	8.495m	74.555ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	23.720s	2.417ms	50	50	100.00
		spi_device_flash_all	8.495m	74.555ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	23.720s	2.417ms	50	50	100.00
		spi_device_flash_all	8.495m	74.555ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	23.720s	2.417ms	50	50	100.00
		spi_device_flash_all	8.495m	74.555ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	23.720s	2.417ms	50	50	100.00
		spi_device_flash_all	8.495m	74.555ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	56.240s	16.961ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.567m	23.182ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.567m	23.182ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.567m	23.182ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.091m	5.384ms	50	50	100.00
		spi_device_read_buffer_direct	24.700s	3.399ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.567m	23.182ms	50	50	100.00
		spi_device_flash_all	8.495m	74.555ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.495m	74.555ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.495m	74.555ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	17.650s	1.629ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	17.650s	1.629ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.365m	713.389ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.792m	300.144ms	50	50	100.00
V2	stress_all	spi_device_stress_all	19.624m	128.588ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	18.188us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.840s	12.855us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.520s	2.318ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.520s	2.318ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.460s	137.629us	5	5	100.00
		spi_device_csr_rw	2.850s	99.295us	20	20	100.00
		spi_device_csr_aliasing	23.220s	911.486us	5	5	100.00
		spi_device_same_csr_outstanding	4.230s	333.892us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.460s	137.629us	5	5	100.00
		spi_device_csr_rw	2.850s	99.295us	20	20	100.00
		spi_device_csr_aliasing	23.220s	911.486us	5	5	100.00
		spi_device_same_csr_outstanding	4.230s	333.892us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.260s	283.619us	5	5	100.00
		spi_device_tl_intg_err	22.620s	820.818us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.620s	820.818us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.663m	419.372ms	49	50	98.00
		TOTAL			1130	1151	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	98.38	93.99	98.62	89.36	97.19	95.45	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.100680063663421866018349329851033620509900340133053802016013432136184616857024
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   3750161 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[78])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   3750161 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   3750161 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[974])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.65996934138213969450981631285965673669346374409315295430038932884572689788835
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4252023 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[15])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4252023 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4252023 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[911])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 19.spi_device_flash_mode_ignore_cmds.69769784761401402291120264055307530038536796387901748322540951471117114491705
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job ID: smart:c1098d02-2b45-4912-a3b8-d7e0e15fd0be
```