SPI_DEVICE/1R1W Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.824m	57.001ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.410s	24.129us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.060s	123.304us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	25.560s	2.610ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.200s	303.734us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.010s	60.441us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.060s	123.304us	20	20	100.00
		spi_device_csr_aliasing	21.200s	303.734us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	11.051us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.230s	195.374us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	31.890us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.750s	1.888us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.770s	16.314us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	5.740s	140.611us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.740s	140.611us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.960s	45.885ms	50	50	100.00
		spi_device_tpm_sts_read	1.060s	152.180us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	55.520s	11.075ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	36.890s	52.783ms	50	50	100.00
		spi_device_flash_all	6.064m	86.766ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	24.100s	8.569ms	50	50	100.00
		spi_device_flash_all	6.064m	86.766ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	24.100s	8.569ms	50	50	100.00
		spi_device_flash_all	6.064m	86.766ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.064m	86.766ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	38.020s	27.911ms	50	50	100.00
		spi_device_flash_all	6.064m	86.766ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	38.020s	27.911ms	50	50	100.00
		spi_device_flash_all	6.064m	86.766ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	38.020s	27.911ms	50	50	100.00
		spi_device_flash_all	6.064m	86.766ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	38.020s	27.911ms	50	50	100.00
		spi_device_flash_all	6.064m	86.766ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	38.020s	27.911ms	50	50	100.00
		spi_device_flash_all	6.064m	86.766ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	32.650s	81.667ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.137m	42.493ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.137m	42.493ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.137m	42.493ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	41.560s	4.464ms	50	50	100.00
		spi_device_read_buffer_direct	24.520s	8.432ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.137m	42.493ms	50	50	100.00
		spi_device_flash_all	6.064m	86.766ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.064m	86.766ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.064m	86.766ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	32.040s	3.556ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	32.040s	3.556ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.824m	57.001ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.068m	281.777ms	50	50	100.00
V2	stress_all	spi_device_stress_all	25.221m	283.958ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.810s	96.861us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.850s	42.846us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.380s	426.403us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.380s	426.403us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.410s	24.129us	5	5	100.00
		spi_device_csr_rw	3.060s	123.304us	20	20	100.00
		spi_device_csr_aliasing	21.200s	303.734us	5	5	100.00
		spi_device_same_csr_outstanding	4.300s	390.700us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.410s	24.129us	5	5	100.00
		spi_device_csr_rw	3.060s	123.304us	20	20	100.00
		spi_device_csr_aliasing	21.200s	303.734us	5	5	100.00
		spi_device_same_csr_outstanding	4.300s	390.700us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.110s	318.976us	5	5	100.00
		spi_device_tl_intg_err	23.890s	17.483ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.890s	17.483ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.128m	179.908ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.55023597192818960437151187610059783741903245228243910982405216289697434973469
      Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4407918 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[30])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4407918 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4407918 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[926])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.113720798946384608072254107903948652128699831842046895069831103291798509822207
      Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    957375 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[12])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    957375 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    957375 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[908])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

Past Results

• Latest
• 2024.08.10_08.30.49
• 2024.08.09_08.01.03
• 2024.08.08_09.14.28
• 2024.08.07_09.08.10
• 2024.08.06_09.37.37
• 2024.08.05_11.07.47
• 2024.08.04_06.55.36